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Commit 6c0a555e authored by Larry Finger's avatar Larry Finger Committed by Greg Kroah-Hartman
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staging: r8188eu: Simplify code related to SupportICType 

This member of struct odm_dm_struct is always set to ODM_RTL8188E for this
driver. Accordingly, the code can be simplified. A number of routines
now are no longer needed and are deleted.
Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 0735ea67
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Showing with 191 additions and 666 deletions
drivers/staging/rtl8188eu/hal/Hal8188ERateAdaptive.c
View file @ 6c0a555e
...@@ -529,8 +529,6 @@ ODM_RASupport_Init( ...@@ -529,8 +529,6 @@ ODM_RASupport_Init(
{ {
ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RASupport_Init()\n")); ODM_RT_TRACE(dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("=====>ODM_RASupport_Init()\n"));
/* 2012/02/14 MH Be noticed, the init must be after IC type is recognized!!!!! */
if (dm_odm->SupportICType == ODM_RTL8188E)
dm_odm->RaSupport88E = true; dm_odm->RaSupport88E = true;
} }
......
drivers/staging/rtl8188eu/hal/odm.c
View file @ 6c0a555e
...@@ -182,9 +182,6 @@ void ODM_DMInit(struct odm_dm_struct *pDM_Odm) ...@@ -182,9 +182,6 @@ void ODM_DMInit(struct odm_dm_struct *pDM_Odm)
odm_DIGInit(pDM_Odm); odm_DIGInit(pDM_Odm);
odm_RateAdaptiveMaskInit(pDM_Odm); odm_RateAdaptiveMaskInit(pDM_Odm);
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
;
} else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
odm_PrimaryCCA_Init(pDM_Odm); /* Gary */ odm_PrimaryCCA_Init(pDM_Odm); /* Gary */
odm_DynamicBBPowerSavingInit(pDM_Odm); odm_DynamicBBPowerSavingInit(pDM_Odm);
odm_DynamicTxPowerInit(pDM_Odm); odm_DynamicTxPowerInit(pDM_Odm);
...@@ -195,7 +192,6 @@ void ODM_DMInit(struct odm_dm_struct *pDM_Odm) ...@@ -195,7 +192,6 @@ void ODM_DMInit(struct odm_dm_struct *pDM_Odm)
(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
odm_InitHybridAntDiv(pDM_Odm); odm_InitHybridAntDiv(pDM_Odm);
}
} }
/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */ /* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
...@@ -215,9 +211,7 @@ void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm) ...@@ -215,9 +211,7 @@ void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm)
/* NeilChen--2012--08--24-- */ /* NeilChen--2012--08--24-- */
/* Fix Leave LPS issue */ /* Fix Leave LPS issue */
if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/* in LPS mode */ if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/* in LPS mode */
((pDM_Odm->SupportICType & (ODM_RTL8723A)) || (pDM_Odm->SupportInterface == ODM_ITRF_SDIO)) {
(pDM_Odm->SupportICType & (ODM_RTL8188E) &&
((pDM_Odm->SupportInterface == ODM_ITRF_SDIO))))) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG is in LPS mode\n")); ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG is in LPS mode\n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n")); ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
odm_DIGbyRSSI_LPS(pDM_Odm); odm_DIGbyRSSI_LPS(pDM_Odm);
...@@ -238,13 +232,9 @@ void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm) ...@@ -238,13 +232,9 @@ void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm)
(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
odm_HwAntDiv(pDM_Odm); odm_HwAntDiv(pDM_Odm);
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
;
} else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
ODM_TXPowerTrackingCheck(pDM_Odm); ODM_TXPowerTrackingCheck(pDM_Odm);
odm_EdcaTurboCheck(pDM_Odm); odm_EdcaTurboCheck(pDM_Odm);
odm_DynamicTxPower(pDM_Odm); odm_DynamicTxPower(pDM_Odm);
}
} }
/* Init /.. Fixed HW value. Only init time. */ /* Init /.. Fixed HW value. Only init time. */
...@@ -455,10 +445,6 @@ void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm) ...@@ -455,10 +445,6 @@ void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm)
pDM_Odm->bCckHighPower = (bool) PHY_QueryBBReg(adapter, 0x824, BIT9); pDM_Odm->bCckHighPower = (bool) PHY_QueryBBReg(adapter, 0x824, BIT9);
pDM_Odm->RFPathRxEnable = (u8) PHY_QueryBBReg(adapter, 0xc04, 0x0F); pDM_Odm->RFPathRxEnable = (u8) PHY_QueryBBReg(adapter, 0xc04, 0x0F);
if (pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D))
pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
if (pDM_Odm->SupportICType & (ODM_RTL8723A))
pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
ODM_InitDebugSetting(pDM_Odm); ODM_InitDebugSetting(pDM_Odm);
} }
...@@ -544,8 +530,6 @@ void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI) ...@@ -544,8 +530,6 @@ void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI)
if (pDM_DigTable->CurIGValue != CurrentIGI) { if (pDM_DigTable->CurIGValue != CurrentIGI) {
PHY_SetBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); PHY_SetBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
if (pDM_Odm->SupportICType != ODM_RTL8188E)
PHY_SetBBReg(adapter, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x).\n", CurrentIGI)); ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x).\n", CurrentIGI));
/* pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; */ /* pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; */
pDM_DigTable->CurIGValue = CurrentIGI; pDM_DigTable->CurIGValue = CurrentIGI;
...@@ -566,9 +550,6 @@ void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm) ...@@ -566,9 +550,6 @@ void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm)
u8 bFwCurrentInPSMode = false; u8 bFwCurrentInPSMode = false;
u8 CurrentIGI = pDM_Odm->RSSI_Min; u8 CurrentIGI = pDM_Odm->RSSI_Min;
if (!(pDM_Odm->SupportICType & (ODM_RTL8723A | ODM_RTL8188E)))
return;
CurrentIGI = CurrentIGI + RSSI_OFFSET_DIG; CurrentIGI = CurrentIGI + RSSI_OFFSET_DIG;
bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode; bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
...@@ -665,58 +646,16 @@ void odm_DIG(struct odm_dm_struct *pDM_Odm) ...@@ -665,58 +646,16 @@ void odm_DIG(struct odm_dm_struct *pDM_Odm)
return; return;
} }
if (pDM_Odm->SupportICType == ODM_RTL8192D) {
if (*(pDM_Odm->pMacPhyMode) == ODM_DMSP) {
if (*(pDM_Odm->pbMasterOfDMSP)) {
DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
} else {
DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_1);
FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1);
}
} else {
if (*(pDM_Odm->pBandType) == ODM_BAND_5G) {
DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
} else {
DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_1);
FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1);
}
}
} else {
DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
}
/* 1 Boundary Decision */ /* 1 Boundary Decision */
if ((pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8723A)) &&
((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) {
dm_dig_max = DM_DIG_MAX_NIC_HP;
dm_dig_min = DM_DIG_MIN_NIC_HP;
DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
} else {
dm_dig_max = DM_DIG_MAX_NIC; dm_dig_max = DM_DIG_MAX_NIC;
dm_dig_min = DM_DIG_MIN_NIC; dm_dig_min = DM_DIG_MIN_NIC;
DIG_MaxOfMin = DM_DIG_MAX_AP; DIG_MaxOfMin = DM_DIG_MAX_AP;
}
if (pDM_Odm->bLinked) { if (pDM_Odm->bLinked) {
/* 2 8723A Series, offset need to be 10 */
if (pDM_Odm->SupportICType == (ODM_RTL8723A)) {
/* 2 Upper Bound */
if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC)
pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC)
pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
else
pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
/* 2 If BT is Concurrent, need to set Lower Bound */
DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
} else {
/* 2 Modify DIG upper bound */ /* 2 Modify DIG upper bound */
if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max) if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
pDM_DigTable->rx_gain_range_max = dm_dig_max; pDM_DigTable->rx_gain_range_max = dm_dig_max;
...@@ -738,8 +677,7 @@ void odm_DIG(struct odm_dm_struct *pDM_Odm) ...@@ -738,8 +677,7 @@ void odm_DIG(struct odm_dm_struct *pDM_Odm)
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
("odm_DIG() : pDM_Odm->RSSI_Min=%d\n", ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n",
pDM_Odm->RSSI_Min)); pDM_Odm->RSSI_Min));
} else if ((pDM_Odm->SupportICType == ODM_RTL8188E) && } else if (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) {
(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) {
/* 1 Lower Bound for 88E AntDiv */ /* 1 Lower Bound for 88E AntDiv */
if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) {
DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max; DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max;
...@@ -750,7 +688,6 @@ void odm_DIG(struct odm_dm_struct *pDM_Odm) ...@@ -750,7 +688,6 @@ void odm_DIG(struct odm_dm_struct *pDM_Odm)
} else { } else {
DIG_Dynamic_MIN = dm_dig_min; DIG_Dynamic_MIN = dm_dig_min;
} }
}
} else { } else {
pDM_DigTable->rx_gain_range_max = dm_dig_max; pDM_DigTable->rx_gain_range_max = dm_dig_max;
DIG_Dynamic_MIN = dm_dig_min; DIG_Dynamic_MIN = dm_dig_min;
...@@ -806,14 +743,6 @@ void odm_DIG(struct odm_dm_struct *pDM_Odm) ...@@ -806,14 +743,6 @@ void odm_DIG(struct odm_dm_struct *pDM_Odm)
if (FirstConnect) { if (FirstConnect) {
CurrentIGI = pDM_Odm->RSSI_Min; CurrentIGI = pDM_Odm->RSSI_Min;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n")); ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
} else {
if (pDM_Odm->SupportICType == ODM_RTL8192D) {
if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D)
CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D)
CurrentIGI = CurrentIGI + 1; /* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D)
CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
} else { } else {
if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
...@@ -822,7 +751,6 @@ void odm_DIG(struct odm_dm_struct *pDM_Odm) ...@@ -822,7 +751,6 @@ void odm_DIG(struct odm_dm_struct *pDM_Odm)
else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */
} }
}
} else { } else {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n"));
if (FirstDisConnect) { if (FirstDisConnect) {
...@@ -872,7 +800,6 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) ...@@ -872,7 +800,6 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
return; return;
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
/* hold ofdm counter */ /* hold ofdm counter */
PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */
PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */
...@@ -893,11 +820,9 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) ...@@ -893,11 +820,9 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail +
FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
if (pDM_Odm->SupportICType == ODM_RTL8188E) {
ret_value = PHY_QueryBBReg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord); ret_value = PHY_QueryBBReg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord);
FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff);
FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16);
}
/* hold cck counter */ /* hold cck counter */
PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1);
...@@ -921,24 +846,6 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) ...@@ -921,24 +846,6 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
if (pDM_Odm->SupportICType >= ODM_RTL8723A) {
/* reset false alarm counter registers */
PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1);
PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0);
PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1);
PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0);
/* update ofdm counter */
PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); /* update page C counter */
PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); /* update page D counter */
/* reset CCK CCA counter */
PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0);
PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2);
/* reset CCK FA counter */
PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0);
PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n")); ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n",
...@@ -949,19 +856,6 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) ...@@ -949,19 +856,6 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n",
FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
} else { /* FOR ODM_IC_11AC_SERIES */
/* read OFDM FA counter */
FalseAlmCnt->Cnt_Ofdm_fail = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_11AC, bMaskLWord);
FalseAlmCnt->Cnt_Cck_fail = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_11AC, bMaskLWord);
FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail;
/* reset OFDM FA coutner */
PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1);
PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0);
/* reset CCK FA counter */
PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11AC, BIT15, 0);
PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11AC, BIT15, 1);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all));
...@@ -1027,20 +921,6 @@ void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm) ...@@ -1027,20 +921,6 @@ void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm)
void odm_DynamicBBPowerSaving(struct odm_dm_struct *pDM_Odm) void odm_DynamicBBPowerSaving(struct odm_dm_struct *pDM_Odm)
{ {
if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8723A))
return;
if (!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE))
return;
/* 1 2.Power Saving for 92C */
if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->RFType == ODM_2T2R)) {
odm_1R_CCA(pDM_Odm);
} else {
/* 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable. */
/* 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns. */
/* 1 3.Power Saving for 88C */
ODM_RF_Saving(pDM_Odm, false);
}
} }
void odm_1R_CCA(struct odm_dm_struct *pDM_Odm) void odm_1R_CCA(struct odm_dm_struct *pDM_Odm)
...@@ -1118,10 +998,6 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) ...@@ -1118,10 +998,6 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal)
if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) { if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
if (pDM_PSTable->CurRFState == RF_Save) { if (pDM_PSTable->CurRFState == RF_Save) {
/* <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode. */
/* Suggested by SD3 Yu-Nan. 2011.01.20. */
if (pDM_Odm->SupportICType == ODM_RTL8723A)
PHY_SetBBReg(adapter, 0x874 , BIT5, 0x1); /* Reg874[5]=1b'1 */
PHY_SetBBReg(adapter, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ PHY_SetBBReg(adapter, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */
PHY_SetBBReg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */ PHY_SetBBReg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */
PHY_SetBBReg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ PHY_SetBBReg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */
...@@ -1135,9 +1011,6 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) ...@@ -1135,9 +1011,6 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal)
PHY_SetBBReg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); PHY_SetBBReg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
PHY_SetBBReg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74); PHY_SetBBReg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74);
PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); PHY_SetBBReg(adapter, 0x818, BIT28, 0x0);
if (pDM_Odm->SupportICType == ODM_RTL8723A)
PHY_SetBBReg(adapter, 0x874, BIT5, 0x0); /* Reg874[5]=1b'0 */
} }
pDM_PSTable->PreRFState = pDM_PSTable->CurRFState; pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
} }
...@@ -1384,13 +1257,6 @@ void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm) ...@@ -1384,13 +1257,6 @@ void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm)
void odm_DynamicTxPowerNIC(struct odm_dm_struct *pDM_Odm) void odm_DynamicTxPowerNIC(struct odm_dm_struct *pDM_Odm)
{ {
if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
return;
if (pDM_Odm->SupportICType == ODM_RTL8188E) {
/* ??? */
/* This part need to be redefined. */
}
} }
/* 3============================================================ */ /* 3============================================================ */
...@@ -1567,9 +1433,6 @@ void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm) ...@@ -1567,9 +1433,6 @@ void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm)
return; return;
} }
if (pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D))
;
else if (pDM_Odm->SupportICType == ODM_RTL8188E)
ODM_AntennaDiversityInit_88E(pDM_Odm); ODM_AntennaDiversityInit_88E(pDM_Odm);
} }
...@@ -1601,7 +1464,6 @@ void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm) ...@@ -1601,7 +1464,6 @@ void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm)
return; return;
} }
if (pDM_Odm->SupportICType == ODM_RTL8188E)
ODM_AntennaDiversity_88E(pDM_Odm); ODM_AntennaDiversity_88E(pDM_Odm);
} }
...@@ -1766,252 +1628,3 @@ void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm) ...@@ -1766,252 +1628,3 @@ void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm)
pDM_SWAT_Table->ANTA_ON = true; pDM_SWAT_Table->ANTA_ON = true;
pDM_SWAT_Table->ANTB_ON = true; pDM_SWAT_Table->ANTB_ON = true;
} }
/* 2 8723A ANT DETECT */
static void odm_PHY_SaveAFERegisters(struct odm_dm_struct *pDM_Odm, u32 *AFEReg, u32 *AFEBackup, u32 RegisterNum)
{
struct adapter *adapter = pDM_Odm->Adapter;
u32 i;
/* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */
for (i = 0; i < RegisterNum; i++)
AFEBackup[i] = PHY_QueryBBReg(adapter, AFEReg[i], bMaskDWord);
}
static void odm_PHY_ReloadAFERegisters(struct odm_dm_struct *pDM_Odm, u32 *AFEReg, u32 *AFEBackup, u32 RegiesterNum)
{
struct adapter *adapter = pDM_Odm->Adapter;
u32 i;
for (i = 0; i < RegiesterNum; i++)
PHY_SetBBReg(adapter, AFEReg[i], bMaskDWord, AFEBackup[i]);
}
/* 2 8723A ANT DETECT */
/* Description: */
/* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */
/* This function is cooperated with BB team Neil. */
bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode)
{
struct adapter *adapter = pDM_Odm->Adapter;
struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u32 CurrentChannel, RfLoopReg;
u8 n;
u32 Reg88c, Regc08, Reg874, Regc50;
u8 initial_gain = 0x5a;
u32 PSD_report_tmp;
u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
bool bResult = true;
u32 AFE_Backup[16];
u32 AFE_REG_8723A[16] = {
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN,
rFPGA0_XCD_SwitchControl, rBlue_Tooth};
if (!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C)))
return bResult;
if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
return bResult;
if (pDM_Odm->SupportICType == ODM_RTL8192C) {
/* Which path in ADC/DAC is turnned on for PSD: both I/Q */
PHY_SetBBReg(adapter, 0x808, BIT10|BIT11, 0x3);
/* Ageraged number: 8 */
PHY_SetBBReg(adapter, 0x808, BIT12|BIT13, 0x1);
/* pts = 128; */
PHY_SetBBReg(adapter, 0x808, BIT14|BIT15, 0x0);
}
/* 1 Backup Current RF/BB Settings */
CurrentChannel = PHY_QueryRFReg(adapter, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
RfLoopReg = PHY_QueryRFReg(adapter, RF_PATH_A, 0x00, bRFRegOffsetMask);
PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A); /* change to Antenna A */
/* Step 1: USE IQK to transmitter single tone */
udelay(10);
/* Store A Path Register 88c, c08, 874, c50 */
Reg88c = PHY_QueryBBReg(adapter, rFPGA0_AnalogParameter4, bMaskDWord);
Regc08 = PHY_QueryBBReg(adapter, rOFDM0_TRMuxPar, bMaskDWord);
Reg874 = PHY_QueryBBReg(adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
Regc50 = PHY_QueryBBReg(adapter, rOFDM0_XAAGCCore1, bMaskDWord);
/* Store AFE Registers */
odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
/* Set PSD 128 pts */
PHY_SetBBReg(adapter, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); /* 128 pts */
/* To SET CH1 to do */
PHY_SetRFReg(adapter, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01); /* Channel 1 */
/* AFE all on step */
PHY_SetBBReg(adapter, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rRx_CCK, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rStandby, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rSleep, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
PHY_SetBBReg(adapter, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
/* 3 wire Disable */
PHY_SetBBReg(adapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
/* BB IQK Setting */
PHY_SetBBReg(adapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
PHY_SetBBReg(adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
/* IQK setting tone@ 4.34Mhz */
PHY_SetBBReg(adapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
PHY_SetBBReg(adapter, rTx_IQK, bMaskDWord, 0x01007c00);
/* Page B init */
PHY_SetBBReg(adapter, rConfig_AntA, bMaskDWord, 0x00080000);
PHY_SetBBReg(adapter, rConfig_AntA, bMaskDWord, 0x0f600000);
PHY_SetBBReg(adapter, rRx_IQK, bMaskDWord, 0x01004800);
PHY_SetBBReg(adapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
PHY_SetBBReg(adapter, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
PHY_SetBBReg(adapter, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
PHY_SetBBReg(adapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
/* RF loop Setting */
PHY_SetRFReg(adapter, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
/* IQK Single tone start */
PHY_SetBBReg(adapter, rFPGA0_IQK, bMaskDWord, 0x80800000);
PHY_SetBBReg(adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
udelay(1000);
PSD_report_tmp = 0x0;
for (n = 0; n < 2; n++) {
PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
if (PSD_report_tmp > AntA_report)
AntA_report = PSD_report_tmp;
}
PSD_report_tmp = 0x0;
PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); /* change to Antenna B */
udelay(10);
for (n = 0; n < 2; n++) {
PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
if (PSD_report_tmp > AntB_report)
AntB_report = PSD_report_tmp;
}
/* change to open case */
PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0); /* change to Ant A and B all open case */
udelay(10);
for (n = 0; n < 2; n++) {
PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
if (PSD_report_tmp > AntO_report)
AntO_report = PSD_report_tmp;
}
/* Close IQK Single Tone function */
PHY_SetBBReg(adapter, rFPGA0_IQK, bMaskDWord, 0x00000000);
PSD_report_tmp = 0x0;
/* 1 Return to antanna A */
PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
PHY_SetBBReg(adapter, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
PHY_SetBBReg(adapter, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
PHY_SetBBReg(adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
PHY_SetBBReg(adapter, rOFDM0_XAAGCCore1, 0x7F, 0x40);
PHY_SetBBReg(adapter, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
PHY_SetRFReg(adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
PHY_SetRFReg(adapter, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
/* Reload AFE Registers */
odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, AntA_report));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, AntB_report));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d\n", 2416, AntO_report));
if (pDM_Odm->SupportICType == ODM_RTL8723A) {
/* 2 Test Ant B based on Ant A is ON */
if (mode == ANTTESTB) {
if (AntA_report >= 100) {
if (AntB_report > (AntA_report+1)) {
pDM_SWAT_Table->ANTB_ON = false;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
} else {
pDM_SWAT_Table->ANTB_ON = true;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
}
} else {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */
bResult = false;
}
} else if (mode == ANTTESTALL) {
/* 2 Test Ant A and B based on DPDT Open */
if ((AntO_report >= 100)&(AntO_report < 118)) {
if (AntA_report > (AntO_report+1)) {
pDM_SWAT_Table->ANTA_ON = false;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is OFF"));
} else {
pDM_SWAT_Table->ANTA_ON = true;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is ON"));
}
if (AntB_report > (AntO_report+2)) {
pDM_SWAT_Table->ANTB_ON = false;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is OFF"));
} else {
pDM_SWAT_Table->ANTB_ON = true;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is ON"));
}
}
}
} else if (pDM_Odm->SupportICType == ODM_RTL8192C) {
if (AntA_report >= 100) {
if (AntB_report > (AntA_report+2)) {
pDM_SWAT_Table->ANTA_ON = false;
pDM_SWAT_Table->ANTB_ON = true;
PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna B\n"));
} else if (AntA_report > (AntB_report+2)) {
pDM_SWAT_Table->ANTA_ON = true;
pDM_SWAT_Table->ANTB_ON = false;
PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
} else {
pDM_SWAT_Table->ANTA_ON = true;
pDM_SWAT_Table->ANTB_ON = true;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
("ODM_SingleDualAntennaDetection(): Dual Antenna\n"));
}
} else {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
pDM_SWAT_Table->ANTA_ON = true; /* Set Antenna A on as default */
pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */
bResult = false;
}
}
return bResult;
}
drivers/staging/rtl8188eu/hal/odm_HWConfig.c
View file @ 6c0a555e
...@@ -113,7 +113,6 @@ static void odm_RxPhyStatus92CSeries_Parsing(struct odm_dm_struct *dm_odm, ...@@ -113,7 +113,6 @@ static void odm_RxPhyStatus92CSeries_Parsing(struct odm_dm_struct *dm_odm,
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1;
if (isCCKrate) { if (isCCKrate) {
u8 report;
u8 cck_agc_rpt; u8 cck_agc_rpt;
dm_odm->PhyDbgInfo.NumQryPhyStatusCCK++; dm_odm->PhyDbgInfo.NumQryPhyStatusCCK++;
...@@ -127,7 +126,6 @@ static void odm_RxPhyStatus92CSeries_Parsing(struct odm_dm_struct *dm_odm, ...@@ -127,7 +126,6 @@ static void odm_RxPhyStatus92CSeries_Parsing(struct odm_dm_struct *dm_odm,
/* 2011.11.28 LukeLee: 88E use different LNA & VGA gain table */ /* 2011.11.28 LukeLee: 88E use different LNA & VGA gain table */
/* The RSSI formula should be modified according to the gain table */ /* The RSSI formula should be modified according to the gain table */
/* In 88E, cck_highpwr is always set to 1 */ /* In 88E, cck_highpwr is always set to 1 */
if (dm_odm->SupportICType & (ODM_RTL8188E|ODM_RTL8812)) {
LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); LNA_idx = ((cck_agc_rpt & 0xE0) >> 5);
VGA_idx = (cck_agc_rpt & 0x1F); VGA_idx = (cck_agc_rpt & 0x1F);
switch (LNA_idx) { switch (LNA_idx) {
...@@ -174,67 +172,6 @@ static void odm_RxPhyStatus92CSeries_Parsing(struct odm_dm_struct *dm_odm, ...@@ -174,67 +172,6 @@ static void odm_RxPhyStatus92CSeries_Parsing(struct odm_dm_struct *dm_odm,
if (PWDB_ALL > 100) if (PWDB_ALL > 100)
PWDB_ALL = 100; PWDB_ALL = 100;
} }
} else {
if (!cck_highpwr) {
report = (cck_agc_rpt & 0xc0)>>6;
switch (report) {
/* 03312009 modified by cosa */
/* Modify the RF RNA gain value to -40, -20, -2, 14 by Jenyu's suggestion */
/* Note: different RF with the different RNA gain. */
case 0x3:
rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
break;
case 0x2:
rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
break;
case 0x1:
rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
break;
case 0x0:
rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
break;
}
} else {
report = (cck_agc_rpt & 0x60)>>5;
switch (report) {
case 0x3:
rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f)<<1) ;
break;
case 0x2:
rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f)<<1);
break;
case 0x1:
rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f)<<1);
break;
case 0x0:
rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f)<<1);
break;
}
}
PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
/* Modification for ext-LNA board */
if (dm_odm->BoardType == ODM_BOARD_HIGHPWR) {
if ((cck_agc_rpt>>7) == 0) {
PWDB_ALL = (PWDB_ALL > 94) ? 100 : (PWDB_ALL+6);
} else {
if (PWDB_ALL > 38)
PWDB_ALL -= 16;
else
PWDB_ALL = (PWDB_ALL <= 16) ? (PWDB_ALL>>2) : (PWDB_ALL-12);
}
/* CCK modification */
if (PWDB_ALL > 25 && PWDB_ALL <= 60)
PWDB_ALL += 6;
} else {/* Modification for int-LNA board */
if (PWDB_ALL > 99)
PWDB_ALL -= 8;
else if (PWDB_ALL > 50 && PWDB_ALL <= 68)
PWDB_ALL += 4;
}
}
pPhyInfo->RxPWDBAll = PWDB_ALL; pPhyInfo->RxPWDBAll = PWDB_ALL;
pPhyInfo->BTRxRSSIPercentage = PWDB_ALL; pPhyInfo->BTRxRSSIPercentage = PWDB_ALL;
...@@ -356,6 +293,8 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm, ...@@ -356,6 +293,8 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm,
u32 OFDM_pkt = 0; u32 OFDM_pkt = 0;
u32 Weighting = 0; u32 Weighting = 0;
struct sta_info *pEntry; struct sta_info *pEntry;
u8 antsel_tr_mux;
struct fast_ant_train *pDM_FatTable = &dm_odm->DM_FatTable;
if (pPktinfo->StationID == 0xFF) if (pPktinfo->StationID == 0xFF)
return; return;
...@@ -368,9 +307,6 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm, ...@@ -368,9 +307,6 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm,
isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M) && (pPktinfo->Rate <= DESC92C_RATE11M)) ? true : false; isCCKrate = ((pPktinfo->Rate >= DESC92C_RATE1M) && (pPktinfo->Rate <= DESC92C_RATE11M)) ? true : false;
/* Smart Antenna Debug Message------------------ */ /* Smart Antenna Debug Message------------------ */
if (dm_odm->SupportICType == ODM_RTL8188E) {
u8 antsel_tr_mux;
struct fast_ant_train *pDM_FatTable = &dm_odm->DM_FatTable;
if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV) { if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV) {
if (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) { if (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) {
...@@ -389,7 +325,6 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm, ...@@ -389,7 +325,6 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm,
ODM_AntselStatistics_88E(dm_odm, antsel_tr_mux, pPktinfo->StationID, pPhyInfo->RxPWDBAll); ODM_AntselStatistics_88E(dm_odm, antsel_tr_mux, pPktinfo->StationID, pPhyInfo->RxPWDBAll);
} }
} }
}
/* Smart Antenna Debug Message------------------ */ /* Smart Antenna Debug Message------------------ */
UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK; UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK;
...@@ -517,12 +452,10 @@ enum HAL_STATUS ODM_ConfigRFWithHeaderFile(struct odm_dm_struct *dm_odm, ...@@ -517,12 +452,10 @@ enum HAL_STATUS ODM_ConfigRFWithHeaderFile(struct odm_dm_struct *dm_odm,
enum ODM_RF_RADIO_PATH rfpath) enum ODM_RF_RADIO_PATH rfpath)
{ {
ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===>ODM_ConfigRFWithHeaderFile\n")); ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===>ODM_ConfigRFWithHeaderFile\n"));
if (dm_odm->SupportICType == ODM_RTL8188E) {
if (rfpath == ODM_RF_PATH_A) if (rfpath == ODM_RF_PATH_A)
READ_AND_CONFIG(8188E, _RadioA_1T_); READ_AND_CONFIG(8188E, _RadioA_1T_);
ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_A:Rtl8188ERadioA_1TArray\n")); ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_A:Rtl8188ERadioA_1TArray\n"));
ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_B:Rtl8188ERadioB_1TArray\n")); ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> ODM_ConfigRFWithHeaderFile() Radio_B:Rtl8188ERadioB_1TArray\n"));
}
ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", rfpath)); ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("ODM_ConfigRFWithHeaderFile: Radio No %x\n", rfpath));
return HAL_STATUS_SUCCESS; return HAL_STATUS_SUCCESS;
...@@ -531,7 +464,6 @@ enum HAL_STATUS ODM_ConfigRFWithHeaderFile(struct odm_dm_struct *dm_odm, ...@@ -531,7 +464,6 @@ enum HAL_STATUS ODM_ConfigRFWithHeaderFile(struct odm_dm_struct *dm_odm,
enum HAL_STATUS ODM_ConfigBBWithHeaderFile(struct odm_dm_struct *dm_odm, enum HAL_STATUS ODM_ConfigBBWithHeaderFile(struct odm_dm_struct *dm_odm,
enum odm_bb_config_type config_tp) enum odm_bb_config_type config_tp)
{ {
if (dm_odm->SupportICType == ODM_RTL8188E) {
if (config_tp == CONFIG_BB_PHY_REG) { if (config_tp == CONFIG_BB_PHY_REG) {
READ_AND_CONFIG(8188E, _PHY_REG_1T_); READ_AND_CONFIG(8188E, _PHY_REG_1T_);
} else if (config_tp == CONFIG_BB_AGC_TAB) { } else if (config_tp == CONFIG_BB_AGC_TAB) {
...@@ -541,14 +473,12 @@ enum HAL_STATUS ODM_ConfigBBWithHeaderFile(struct odm_dm_struct *dm_odm, ...@@ -541,14 +473,12 @@ enum HAL_STATUS ODM_ConfigBBWithHeaderFile(struct odm_dm_struct *dm_odm,
ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
(" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_PGArray\n")); (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8188EPHY_REG_PGArray\n"));
} }
}
return HAL_STATUS_SUCCESS; return HAL_STATUS_SUCCESS;
} }
enum HAL_STATUS ODM_ConfigMACWithHeaderFile(struct odm_dm_struct *dm_odm) enum HAL_STATUS ODM_ConfigMACWithHeaderFile(struct odm_dm_struct *dm_odm)
{ {
u8 result = HAL_STATUS_SUCCESS; u8 result = HAL_STATUS_SUCCESS;
if (dm_odm->SupportICType == ODM_RTL8188E)
result = READ_AND_CONFIG(8188E, _MAC_REG_); result = READ_AND_CONFIG(8188E, _MAC_REG_);
return result; return result;
} }
drivers/staging/rtl8188eu/hal/odm_RTL8188E.c
View file @ 6c0a555e
...@@ -184,9 +184,6 @@ static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm) ...@@ -184,9 +184,6 @@ static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm)
void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *dm_odm) void ODM_AntennaDiversityInit_88E(struct odm_dm_struct *dm_odm)
{ {
if (dm_odm->SupportICType != ODM_RTL8188E)
return;
ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->AntDivType=%d\n", dm_odm->AntDivType)); ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->AntDivType=%d\n", dm_odm->AntDivType));
ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->bIsMPChip=%s\n", (dm_odm->bIsMPChip ? "true" : "false"))); ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_odm->bIsMPChip=%s\n", (dm_odm->bIsMPChip ? "true" : "false")));
...@@ -349,7 +346,7 @@ void ODM_AntennaDiversity_88E(struct odm_dm_struct *dm_odm) ...@@ -349,7 +346,7 @@ void ODM_AntennaDiversity_88E(struct odm_dm_struct *dm_odm)
struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
struct adapter *adapter = dm_odm->Adapter; struct adapter *adapter = dm_odm->Adapter;
if ((dm_odm->SupportICType != ODM_RTL8188E) || (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV))) if (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV))
return; return;
if (!dm_odm->bLinked) { if (!dm_odm->bLinked) {
ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E(): No Link.\n")); ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_AntennaDiversity_88E(): No Link.\n"));
......
drivers/staging/rtl8188eu/include/odm.h
View file @ 6c0a555e
...@@ -1183,8 +1183,6 @@ void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId, ...@@ -1183,8 +1183,6 @@ void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId,
void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm); void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm);
bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode);
void odm_dtc(struct odm_dm_struct *pDM_Odm); void odm_dtc(struct odm_dm_struct *pDM_Odm);
#endif #endif
drivers/staging/rtl8188eu/include/odm_debug.h
View file @ 6c0a555e
...@@ -94,18 +94,7 @@ ...@@ -94,18 +94,7 @@
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \ #define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \
if (((comp) & pDM_Odm->DebugComponents) && \ if (((comp) & pDM_Odm->DebugComponents) && \
(level <= pDM_Odm->DebugLevel)) { \ (level <= pDM_Odm->DebugLevel)) { \
if (pDM_Odm->SupportICType == ODM_RTL8192C) \
DbgPrint("[ODM-92C] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8192D) \
DbgPrint("[ODM-92D] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8723A) \
DbgPrint("[ODM-8723A] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8188E) \
DbgPrint("[ODM-8188E] "); \ DbgPrint("[ODM-8188E] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8812) \
DbgPrint("[ODM-8812] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8821) \
DbgPrint("[ODM-8821] "); \
RT_PRINTK fmt; \ RT_PRINTK fmt; \
} }
......
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