Commit 6c5ef620 authored by Mitch Williams's avatar Mitch Williams Committed by David S. Miller

i40e: tighten up ring enable/disable flow

Change the do/while to a for loop, so we don't hit the delay each
time, even when the register is ready for action.
Don't bother to set or clear the QENA_STAT bit as it is
read-only.

Change-ID: Ie464718804dd79f6d726f291caa9b0c872b49978
Signed-off-by: default avatarMitch Williams <mitch.a.williams@intel.com>
Signed-off-by: default avatarJesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: default avatarKavindya Deegala <kavindya.s.deegala@intel.com>
Signed-off-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 81b8c011
...@@ -3108,13 +3108,13 @@ static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable) ...@@ -3108,13 +3108,13 @@ static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
pf_q = vsi->base_queue; pf_q = vsi->base_queue;
for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
j = 1000; for (j = 0; j < 50; j++) {
do {
usleep_range(1000, 2000);
tx_reg = rd32(hw, I40E_QTX_ENA(pf_q)); tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
} while (j-- && ((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
^ (tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)) & 1); ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
break;
usleep_range(1000, 2000);
}
/* Skip if the queue is already in the requested state */ /* Skip if the queue is already in the requested state */
if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) if (enable && (tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
continue; continue;
...@@ -3124,8 +3124,7 @@ static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable) ...@@ -3124,8 +3124,7 @@ static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
/* turn on/off the queue */ /* turn on/off the queue */
if (enable) { if (enable) {
wr32(hw, I40E_QTX_HEAD(pf_q), 0); wr32(hw, I40E_QTX_HEAD(pf_q), 0);
tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK | tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
I40E_QTX_ENA_QENA_STAT_MASK;
} else { } else {
tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
} }
...@@ -3172,12 +3171,13 @@ static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable) ...@@ -3172,12 +3171,13 @@ static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
pf_q = vsi->base_queue; pf_q = vsi->base_queue;
for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
j = 1000; for (j = 0; j < 50; j++) {
do {
usleep_range(1000, 2000);
rx_reg = rd32(hw, I40E_QRX_ENA(pf_q)); rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
} while (j-- && ((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
^ (rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT)) & 1); ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
break;
usleep_range(1000, 2000);
}
if (enable) { if (enable) {
/* is STAT set ? */ /* is STAT set ? */
...@@ -3191,11 +3191,9 @@ static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable) ...@@ -3191,11 +3191,9 @@ static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
/* turn on/off the queue */ /* turn on/off the queue */
if (enable) if (enable)
rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK | rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
I40E_QRX_ENA_QENA_STAT_MASK;
else else
rx_reg &= ~(I40E_QRX_ENA_QENA_REQ_MASK | rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
I40E_QRX_ENA_QENA_STAT_MASK);
wr32(hw, I40E_QRX_ENA(pf_q), rx_reg); wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
/* wait for the change to finish */ /* wait for the change to finish */
......
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