Commit 6cf72f41 authored by Terry Bowman's avatar Terry Bowman Committed by Wolfram Sang

i2c: piix4: Enable EFCH MMIO for Family 17h+

Enable EFCH MMIO using check for SMBus PCI revision ID value 0x51 or
greater. This PCI revision ID check will enable family 17h and future
AMD processors with the same EFCH SMBus controller HW.
Signed-off-by: default avatarTerry Bowman <terry.bowman@amd.com>
Reviewed-by: default avatarAndy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: default avatarJean Delvare <jdelvare@suse.de>
Signed-off-by: default avatarWolfram Sang <wsa@kernel.org>
parent 381a3083
...@@ -229,6 +229,18 @@ static void piix4_sb800_region_release(struct device *dev, ...@@ -229,6 +229,18 @@ static void piix4_sb800_region_release(struct device *dev,
release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE); release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE);
} }
static bool piix4_sb800_use_mmio(struct pci_dev *PIIX4_dev)
{
/*
* cd6h/cd7h port I/O accesses can be disabled on AMD processors
* w/ SMBus PCI revision ID 0x51 or greater. MMIO is supported on
* the same processors and is the recommended access method.
*/
return (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
PIIX4_dev->revision >= 0x51);
}
static int piix4_setup(struct pci_dev *PIIX4_dev, static int piix4_setup(struct pci_dev *PIIX4_dev,
const struct pci_device_id *id) const struct pci_device_id *id)
{ {
...@@ -339,7 +351,7 @@ static int piix4_setup_sb800_smba(struct pci_dev *PIIX4_dev, ...@@ -339,7 +351,7 @@ static int piix4_setup_sb800_smba(struct pci_dev *PIIX4_dev,
u8 smba_en_hi; u8 smba_en_hi;
int retval; int retval;
mmio_cfg.use_mmio = 0; mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev);
retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg); retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg);
if (retval) if (retval)
return retval; return retval;
...@@ -461,7 +473,7 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, ...@@ -461,7 +473,7 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT; piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
} }
} else { } else {
mmio_cfg.use_mmio = 0; mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev);
retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg); retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg);
if (retval) { if (retval) {
release_region(piix4_smba, SMBIOSIZE); release_region(piix4_smba, SMBIOSIZE);
...@@ -944,6 +956,7 @@ static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, ...@@ -944,6 +956,7 @@ static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
return -ENOMEM; return -ENOMEM;
} }
adapdata->mmio_cfg.use_mmio = piix4_sb800_use_mmio(dev);
adapdata->smba = smba; adapdata->smba = smba;
adapdata->sb800_main = sb800_main; adapdata->sb800_main = sb800_main;
adapdata->port = port << piix4_port_shift_sb800; adapdata->port = port << piix4_port_shift_sb800;
......
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