Commit 6cfa9238 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS fixes from Ralf Baechle:
 "Fixes for a number of small glitches in various corners of the MIPS
  tree.  No particular areas is standing out.

  With this applied all MIPS defconfigs are building fine.  No merge
  conflicts are expected."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: Delete definition of SA_RESTORER.
  MIPS: Fix ISA level which causes secondary cache init bypassing and more
  MIPS: Fix build error cavium-octeon without CONFIG_SMP
  MIPS: Kconfig: Rename SNIPROM too
  MIPS: Alchemy: Fix typo "CONFIG_DEBUG_PCI"
  MIPS: Unbreak function tracer for 64-bit kernel.
parents 00fa6fe9 80fa8181
...@@ -657,7 +657,7 @@ config SNI_RM ...@@ -657,7 +657,7 @@ config SNI_RM
bool "SNI RM200/300/400" bool "SNI RM200/300/400"
select FW_ARC if CPU_LITTLE_ENDIAN select FW_ARC if CPU_LITTLE_ENDIAN
select FW_ARC32 if CPU_LITTLE_ENDIAN select FW_ARC32 if CPU_LITTLE_ENDIAN
select SNIPROM if CPU_BIG_ENDIAN select FW_SNIPROM if CPU_BIG_ENDIAN
select ARCH_MAY_HAVE_PC_FDC select ARCH_MAY_HAVE_PC_FDC
select BOOT_ELF32 select BOOT_ELF32
select CEVT_R4K select CEVT_R4K
...@@ -1144,7 +1144,7 @@ config DEFAULT_SGI_PARTITION ...@@ -1144,7 +1144,7 @@ config DEFAULT_SGI_PARTITION
config FW_ARC32 config FW_ARC32
bool bool
config SNIPROM config FW_SNIPROM
bool bool
config BOOT_ELF32 config BOOT_ELF32
......
...@@ -174,7 +174,10 @@ static int octeon_kexec_prepare(struct kimage *image) ...@@ -174,7 +174,10 @@ static int octeon_kexec_prepare(struct kimage *image)
static void octeon_generic_shutdown(void) static void octeon_generic_shutdown(void)
{ {
int cpu, i; int i;
#ifdef CONFIG_SMP
int cpu;
#endif
struct cvmx_bootmem_desc *bootmem_desc; struct cvmx_bootmem_desc *bootmem_desc;
void *named_block_array_ptr; void *named_block_array_ptr;
......
...@@ -72,6 +72,12 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ ...@@ -72,6 +72,12 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */
* *
* SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
* Unix names RESETHAND and NODEFER respectively. * Unix names RESETHAND and NODEFER respectively.
*
* SA_RESTORER used to be defined as 0x04000000 but only the O32 ABI ever
* supported its use and no libc was using it, so the entire sa-restorer
* functionality was removed with lmo commit 39bffc12c3580ab for 2.5.48
* retaining only the SA_RESTORER definition as a reminder to avoid
* accidental reuse of the mask bit.
*/ */
#define SA_ONSTACK 0x08000000 #define SA_ONSTACK 0x08000000
#define SA_RESETHAND 0x80000000 #define SA_RESETHAND 0x80000000
...@@ -84,8 +90,6 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ ...@@ -84,8 +90,6 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */
#define SA_NOMASK SA_NODEFER #define SA_NOMASK SA_NODEFER
#define SA_ONESHOT SA_RESETHAND #define SA_ONESHOT SA_RESETHAND
#define SA_RESTORER 0x04000000 /* Only for o32 */
#define MINSIGSTKSZ 2048 #define MINSIGSTKSZ 2048
#define SIGSTKSZ 8192 #define SIGSTKSZ 8192
......
...@@ -1227,10 +1227,8 @@ __cpuinit void cpu_probe(void) ...@@ -1227,10 +1227,8 @@ __cpuinit void cpu_probe(void)
if (c->options & MIPS_CPU_FPU) { if (c->options & MIPS_CPU_FPU) {
c->fpu_id = cpu_get_fpu_id(); c->fpu_id = cpu_get_fpu_id();
if (c->isa_level == MIPS_CPU_ISA_M32R1 || if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
c->isa_level == MIPS_CPU_ISA_M32R2 || MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
c->isa_level == MIPS_CPU_ISA_M64R1 ||
c->isa_level == MIPS_CPU_ISA_M64R2) {
if (c->fpu_id & MIPS_FPIR_3D) if (c->fpu_id & MIPS_FPIR_3D)
c->ases |= MIPS_ASE_MIPS3D; c->ases |= MIPS_ASE_MIPS3D;
} }
......
...@@ -46,10 +46,9 @@ ...@@ -46,10 +46,9 @@
PTR_L a5, PT_R9(sp) PTR_L a5, PT_R9(sp)
PTR_L a6, PT_R10(sp) PTR_L a6, PT_R10(sp)
PTR_L a7, PT_R11(sp) PTR_L a7, PT_R11(sp)
#else
PTR_ADDIU sp, PT_SIZE
#endif #endif
.endm PTR_ADDIU sp, PT_SIZE
.endm
.macro RETURN_BACK .macro RETURN_BACK
jr ra jr ra
...@@ -68,7 +67,11 @@ NESTED(ftrace_caller, PT_SIZE, ra) ...@@ -68,7 +67,11 @@ NESTED(ftrace_caller, PT_SIZE, ra)
.globl _mcount .globl _mcount
_mcount: _mcount:
b ftrace_stub b ftrace_stub
#ifdef CONFIG_32BIT
addiu sp,sp,8 addiu sp,sp,8
#else
nop
#endif
/* When tracing is activated, it calls ftrace_caller+8 (aka here) */ /* When tracing is activated, it calls ftrace_caller+8 (aka here) */
lw t1, function_trace_stop lw t1, function_trace_stop
......
...@@ -1571,7 +1571,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu) ...@@ -1571,7 +1571,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
#endif #endif
if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
status_set |= ST0_XX; status_set |= ST0_XX;
if (cpu_has_dsp) if (cpu_has_dsp)
status_set |= ST0_MX; status_set |= ST0_MX;
......
...@@ -1247,10 +1247,8 @@ static void __cpuinit setup_scache(void) ...@@ -1247,10 +1247,8 @@ static void __cpuinit setup_scache(void)
return; return;
default: default:
if (c->isa_level == MIPS_CPU_ISA_M32R1 || if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
c->isa_level == MIPS_CPU_ISA_M32R2 || MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
c->isa_level == MIPS_CPU_ISA_M64R1 ||
c->isa_level == MIPS_CPU_ISA_M64R2) {
#ifdef CONFIG_MIPS_CPU_SCACHE #ifdef CONFIG_MIPS_CPU_SCACHE
if (mips_sc_init ()) { if (mips_sc_init ()) {
scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
......
...@@ -98,10 +98,8 @@ static inline int __init mips_sc_probe(void) ...@@ -98,10 +98,8 @@ static inline int __init mips_sc_probe(void)
c->scache.flags |= MIPS_CACHE_NOT_PRESENT; c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
/* Ignore anything but MIPSxx processors */ /* Ignore anything but MIPSxx processors */
if (c->isa_level != MIPS_CPU_ISA_M32R1 && if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
c->isa_level != MIPS_CPU_ISA_M32R2 && MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
c->isa_level != MIPS_CPU_ISA_M64R1 &&
c->isa_level != MIPS_CPU_ISA_M64R2)
return 0; return 0;
/* Does this MIPS32/MIPS64 CPU have a config2 register? */ /* Does this MIPS32/MIPS64 CPU have a config2 register? */
......
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
#include <asm/mach-au1x00/au1000.h> #include <asm/mach-au1x00/au1000.h>
#include <asm/tlbmisc.h> #include <asm/tlbmisc.h>
#ifdef CONFIG_DEBUG_PCI #ifdef CONFIG_PCI_DEBUG
#define DBG(x...) printk(KERN_DEBUG x) #define DBG(x...) printk(KERN_DEBUG x)
#else #else
#define DBG(x...) do {} while (0) #define DBG(x...) do {} while (0)
...@@ -162,7 +162,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, ...@@ -162,7 +162,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
if (status & (1 << 29)) { if (status & (1 << 29)) {
*data = 0xffffffff; *data = 0xffffffff;
error = -1; error = -1;
DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d", DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n",
access_type, bus->number, device); access_type, bus->number, device);
} else if ((status >> 28) & 0xf) { } else if ((status >> 28) & 0xf) {
DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n", DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment