Commit 6ddcba9d authored by Maciej W. Rozycki's avatar Maciej W. Rozycki Committed by Thomas Bogendoerfer

MIPS: Sanitise Cavium switch cases in TLB handler synthesizers

It makes no sense to fall through to `break'.  Therefore reorder the
switch statements so as to have the Cavium cases first, followed by the
default case, which improves readability and pacifies code analysis
tools.  No change in semantics, assembly produced is exactly the same.
Reported-by: default avatarkernel test robot <lkp@intel.com>
Signed-off-by: default avatarMaciej W. Rozycki <macro@orcam.me.uk>
Fixes: bc431d21 ("MIPS: Fix fall-through warnings for Clang")
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 244eae91
......@@ -2159,16 +2159,14 @@ static void build_r4000_tlb_load_handler(void)
uasm_i_tlbr(&p);
switch (current_cpu_type()) {
default:
if (cpu_has_mips_r2_exec_hazard) {
uasm_i_ehb(&p);
fallthrough;
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
break;
}
default:
if (cpu_has_mips_r2_exec_hazard)
uasm_i_ehb(&p);
break;
}
/* Examine entrylo 0 or 1 based on ptr. */
......@@ -2235,15 +2233,14 @@ static void build_r4000_tlb_load_handler(void)
uasm_i_tlbr(&p);
switch (current_cpu_type()) {
default:
if (cpu_has_mips_r2_exec_hazard) {
uasm_i_ehb(&p);
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
break;
}
default:
if (cpu_has_mips_r2_exec_hazard)
uasm_i_ehb(&p);
break;
}
/* Examine entrylo 0 or 1 based on ptr. */
......
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