Commit 6de481e5 authored by Thierry Reding's avatar Thierry Reding

arm64: tegra: Hook up MMC and BPMP to memory controller

Use the interconnects property to hook up the MMC and BPMP to the memory
controller. This is needed to set the correct bus-level DMA mask, which
is a prerequisite for adding IOMMU support.
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent eed280df
......@@ -156,6 +156,9 @@ mmc@3460000 {
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
resets = <&bpmp TEGRA234_RESET_SDMMC4>;
reset-names = "sdhci";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>,
<&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>;
interconnect-names = "dma-mem", "write";
nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
......@@ -288,6 +291,11 @@ bpmp: bpmp {
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>,
<&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>;
interconnect-names = "read", "write", "dma-mem", "dma-write";
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
......
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