remoteproc: k3-dsp: Add a remoteproc driver of K3 C66x DSPs
The Texas Instrument's K3 J721E SoCs have two C66x DSP Subsystems in MAIN voltage domain that are based on the TI's standard TMS320C66x DSP CorePac module. Each subsystem has a Fixed/Floating-Point DSP CPU, with 32 KB each of L1P & L1D SRAMs that can be configured and partitioned as either RAM and/or Cache, and 288 KB of L2 SRAM with 256 KB of memory configurable as either RAM and/or Cache. The CorePac also includes an Internal DMA (IDMA), External Memory Controller (EMC), Extended Memory Controller (XMC) with a Region Address Translator (RAT) unit for 32-bit to 48-bit address extension/translations, an Interrupt Controller (INTC) and a Powerdown Controller (PDC). A new remoteproc module is added to perform the device management of these DSP devices. The support is limited to images using only external DDR memory at the moment, the loading support to internal memories and any on-chip RAM memories will be added in a subsequent patch. RAT support is also left for a future patch, and as such the reserved memory carveout regions are all expected to be using memory regions within the first 2 GB. Error Recovery and Power Management features are not currently supported. The C66x remote processors do not have an MMU, and so require fixed memory carveout regions matching the firmware image addresses. Support for this is provided by mandating multiple memory regions to be attached to the remoteproc device. The first memory region will be used to serve as the DMA pool for all dynamic allocations like the vrings and vring buffers. The remaining memory regions are mapped into the kernel at device probe time, and are used to provide address translations for firmware image segments without the need for any RSC_CARVEOUT entries. Any firmware image using memory outside of the supplied reserved memory carveout regions will be errored out. The driver uses various TI-SCI interfaces to talk to the System Controller (DMSC) for managing configuration, power and reset management of these cores. IPC between the A72 cores and the DSP cores is supported through the virtio rpmsg stack using shared memory and OMAP Mailboxes. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20200721223617.20312-6-s-anna@ti.comSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Showing
Please register or sign in to comment