Commit 6f211ed4 authored by Anusha Srivatsa's avatar Anusha Srivatsa Committed by Paulo Zanoni

drm/i915/icl: Set TBT IO in Aux transaction

For a TBT sequence, we need to set the IO type to TBT
in  DDI_AUX_CTL.

v2: Avoid duplications.(Paulo)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1532648115-29795-2-git-send-email-anusha.srivatsa@intel.com
parent 2b7edeb0
...@@ -5558,6 +5558,7 @@ enum { ...@@ -5558,6 +5558,7 @@ enum {
#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
#define DP_AUX_CH_CTL_TBT_IO (1 << 11)
#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
......
...@@ -1208,15 +1208,23 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, ...@@ -1208,15 +1208,23 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
int send_bytes, int send_bytes,
uint32_t unused) uint32_t unused)
{ {
return DP_AUX_CH_CTL_SEND_BUSY | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
DP_AUX_CH_CTL_DONE | uint32_t ret;
DP_AUX_CH_CTL_INTERRUPT |
DP_AUX_CH_CTL_TIME_OUT_ERROR | ret = DP_AUX_CH_CTL_SEND_BUSY |
DP_AUX_CH_CTL_TIME_OUT_MAX | DP_AUX_CH_CTL_DONE |
DP_AUX_CH_CTL_RECEIVE_ERROR | DP_AUX_CH_CTL_INTERRUPT |
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | DP_AUX_CH_CTL_TIME_OUT_ERROR |
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | DP_AUX_CH_CTL_TIME_OUT_MAX |
DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); DP_AUX_CH_CTL_RECEIVE_ERROR |
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
if (intel_dig_port->tc_type == TC_PORT_TBT)
ret |= DP_AUX_CH_CTL_TBT_IO;
return ret;
} }
static int static int
......
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