Commit 706b74fd authored by Rajmohan Mani's avatar Rajmohan Mani Committed by Kamal Mostafa

xhci: Workaround to get Intel xHCI reset working more reliably

commit a5964396 upstream.

Existing Intel xHCI controllers require a delay of 1 mS,
after setting the CMD_RESET bit in command register, before
accessing any HC registers. This allows the HC to complete
the reset operation and be ready for HC register access.
Without this delay, the subsequent HC register access,
may result in a system hang, very rarely.

Verified CherryView / Braswell platforms go through over
5000 warm reboot cycles (which was not possible without
this patch), without any xHCI reset hang.
Signed-off-by: default avatarRajmohan Mani <rajmohan.mani@intel.com>
Tested-by: default avatarJoe Lawrence <joe.lawrence@stratus.com>
Signed-off-by: default avatarMathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: default avatarKamal Mostafa <kamal@canonical.com>
parent c8f9a561
...@@ -176,6 +176,16 @@ int xhci_reset(struct xhci_hcd *xhci) ...@@ -176,6 +176,16 @@ int xhci_reset(struct xhci_hcd *xhci)
command |= CMD_RESET; command |= CMD_RESET;
writel(command, &xhci->op_regs->command); writel(command, &xhci->op_regs->command);
/* Existing Intel xHCI controllers require a delay of 1 mS,
* after setting the CMD_RESET bit, and before accessing any
* HC registers. This allows the HC to complete the
* reset operation and be ready for HC register access.
* Without this delay, the subsequent HC register access,
* may result in a system hang very rarely.
*/
if (xhci->quirks & XHCI_INTEL_HOST)
udelay(1000);
ret = xhci_handshake(xhci, &xhci->op_regs->command, ret = xhci_handshake(xhci, &xhci->op_regs->command,
CMD_RESET, 0, 10 * 1000 * 1000); CMD_RESET, 0, 10 * 1000 * 1000);
if (ret) if (ret)
......
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