Commit 71f777ed authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "A first set of batches of fixes for 3.13.  The diffstat is large
  mostly because we're adding a defconfig for a family that's been
  lacking it, and there's some missing clock information added for i.MX
  and OMAP.

  The at91 new code is around dealing with RTC/RTT reset at boot to fix
  possible hangs due to pending wakeup interrupts coming in during early
  boot"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (29 commits)
  ARM: OMAP2+: Fix build for dra7xx without omap4 and 5
  ARM: OMAP2+: omap_device: maintain sane runtime pm status around suspend/resume
  doc: devicetree: Add bindings documentation for omap-des driver
  ARM: dts: doc: Document missing compatible property for omap-sham driver
  ARM: OMAP3: Beagle: fix return value check in beagle_opp_init()
  ARM: at91: fix hanged boot due to early rtt-interrupt
  ARM: at91: fix hanged boot due to early rtc-interrupt
  video: exynos_mipi_dsim: Remove unused variable
  ARM: highbank: only select errata 764369 if SMP
  ARM: sti: only select errata 764369 if SMP
  ARM: tegra: init fuse before setting reset handler
  ARM: vt8500: add defconfig for v6/v7 chips
  ARM: integrator_cp: Set LCD{0,1} enable lines when turning on CLCD
  ARM: OMAP: devicetree: fix SPI node compatible property syntax items
  pinctrl: single: call pcs_soc->rearm() whenever IRQ mask is changed
  ARM: OMAP2+: smsc911x: fix return value check in gpmc_smsc911x_init()
  MAINTAINERS: drop discontinued mailing list
  ARM: dts: i.MX51: Fix OTG PHY clock
  ARM: imx: set up pllv3 POWER and BYPASS sequentially
  ARM: imx: pllv3 needs relock in .set_rate() call
  ...
parents dd3190ee 6886059f
OMAP SoC DES crypto Module
Required properties:
- compatible : Should contain "ti,omap4-des"
- ti,hwmods: Name of the hwmod associated with the DES module
- reg : Offset and length of the register set for the module
- interrupts : the interrupt-specifier for the DES module
- clocks : A phandle to the functional clock node of the DES module
corresponding to each entry in clock-names
- clock-names : Name of the functional clock, should be "fck"
Optional properties:
- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
Documentation/devicetree/bindings/dma/dma.txt
Each entry corresponds to an entry in dma-names
- dma-names: DMA request names should include "tx" and "rx" if present
Example:
/* DRA7xx SoC */
des: des@480a5000 {
compatible = "ti,omap4-des";
ti,hwmods = "des";
reg = <0x480a5000 0xa0>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 117>, <&sdma 116>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
...@@ -6,7 +6,7 @@ Required properties: ...@@ -6,7 +6,7 @@ Required properties:
SHAM versions: SHAM versions:
- "ti,omap2-sham" for OMAP2 & OMAP3. - "ti,omap2-sham" for OMAP2 & OMAP3.
- "ti,omap4-sham" for OMAP4 and AM33XX. - "ti,omap4-sham" for OMAP4 and AM33XX.
Note that these two versions are incompatible. - "ti,omap5-sham" for OMAP5, DRA7 and AM43XX.
- ti,hwmods: Name of the hwmod associated with the SHAM module - ti,hwmods: Name of the hwmod associated with the SHAM module
- reg : Offset and length of the register set for the module - reg : Offset and length of the register set for the module
- interrupts : the interrupt-specifier for the SHAM module. - interrupts : the interrupt-specifier for the SHAM module.
......
...@@ -2,8 +2,8 @@ OMAP2+ McSPI device ...@@ -2,8 +2,8 @@ OMAP2+ McSPI device
Required properties: Required properties:
- compatible : - compatible :
- "ti,omap2-spi" for OMAP2 & OMAP3. - "ti,omap2-mcspi" for OMAP2 & OMAP3.
- "ti,omap4-spi" for OMAP4+. - "ti,omap4-mcspi" for OMAP4+.
- ti,spi-num-cs : Number of chipselect supported by the instance. - ti,spi-num-cs : Number of chipselect supported by the instance.
- ti,hwmods: Name of the hwmod associated to the McSPI - ti,hwmods: Name of the hwmod associated to the McSPI
- ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as - ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
......
...@@ -1070,7 +1070,6 @@ S: Maintained ...@@ -1070,7 +1070,6 @@ S: Maintained
ARM/NOMADIK ARCHITECTURE ARM/NOMADIK ARCHITECTURE
M: Alessandro Rubini <rubini@unipv.it> M: Alessandro Rubini <rubini@unipv.it>
M: Linus Walleij <linus.walleij@linaro.org> M: Linus Walleij <linus.walleij@linaro.org>
M: STEricsson <STEricsson_nomadik_linux@list.st.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained S: Maintained
F: arch/arm/mach-nomadik/ F: arch/arm/mach-nomadik/
......
...@@ -190,7 +190,7 @@ esdhc4: esdhc@70024000 { ...@@ -190,7 +190,7 @@ esdhc4: esdhc@70024000 {
usbphy0: usbphy@0 { usbphy0: usbphy@0 {
compatible = "usb-nop-xceiv"; compatible = "usb-nop-xceiv";
clocks = <&clks 124>; clocks = <&clks 75>;
clock-names = "main_clk"; clock-names = "main_clk";
status = "okay"; status = "okay";
}; };
......
CONFIG_IRQ_DOMAIN_DEBUG=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_ARCH_MULTI_V6=y
CONFIG_ARCH_WM8750=y
CONFIG_ARCH_WM8850=y
CONFIG_ARM_ERRATA_720789=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_ARM_ERRATA_775420=y
CONFIG_HAVE_ARM_ARCH_TIMER=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_HIGHPTE=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_PM_RUNTIME=y
CONFIG_NET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_PROC_DEVICETREE=y
CONFIG_EEPROM_93CX6=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
CONFIG_VIA_VELOCITY=y
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_PHYLIB=y
CONFIG_INPUT_MATRIXKMAP=y
CONFIG_SERIAL_VT8500=y
CONFIG_SERIAL_VT8500_CONSOLE=y
CONFIG_I2C=y
CONFIG_I2C_WMT=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_PINCTRL_WM8750=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_POWER_SUPPLY=y
CONFIG_POWER_RESET=y
CONFIG_MFD_SYSCON=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_GPIO=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_UHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_USB_GPIO_VBUS=y
CONFIG_USB_ULPI=y
CONFIG_MMC=y
CONFIG_MMC_DEBUG=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_VT8500=y
CONFIG_DMADEVICES=y
CONFIG_COMMON_CLK_DEBUG=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_PWM=y
CONFIG_PWM_VT8500=y
CONFIG_RESET_CONTROLLER=y
CONFIG_GENERIC_PHY=y
CONFIG_EXT4_FS=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_KERNEL=y
CONFIG_LOCKUP_DETECTOR=y
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
# Makefile for the linux kernel. # Makefile for the linux kernel.
# #
obj-y := irq.o gpio.o setup.o obj-y := irq.o gpio.o setup.o sysirq_mask.o
obj-m := obj-m :=
obj-n := obj-n :=
obj- := obj- :=
......
...@@ -351,6 +351,8 @@ static void __init at91sam9260_initialize(void) ...@@ -351,6 +351,8 @@ static void __init at91sam9260_initialize(void)
arm_pm_idle = at91sam9_idle; arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart; arm_pm_restart = at91sam9_alt_restart;
at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);
/* Register GPIO subsystem */ /* Register GPIO subsystem */
at91_gpio_init(at91sam9260_gpio, 3); at91_gpio_init(at91sam9260_gpio, 3);
} }
......
...@@ -293,6 +293,8 @@ static void __init at91sam9261_initialize(void) ...@@ -293,6 +293,8 @@ static void __init at91sam9261_initialize(void)
arm_pm_idle = at91sam9_idle; arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart; arm_pm_restart = at91sam9_alt_restart;
at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);
/* Register GPIO subsystem */ /* Register GPIO subsystem */
at91_gpio_init(at91sam9261_gpio, 3); at91_gpio_init(at91sam9261_gpio, 3);
} }
......
...@@ -330,6 +330,9 @@ static void __init at91sam9263_initialize(void) ...@@ -330,6 +330,9 @@ static void __init at91sam9263_initialize(void)
arm_pm_idle = at91sam9_idle; arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart; arm_pm_restart = at91sam9_alt_restart;
at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
/* Register GPIO subsystem */ /* Register GPIO subsystem */
at91_gpio_init(at91sam9263_gpio, 5); at91_gpio_init(at91sam9263_gpio, 5);
} }
......
...@@ -379,6 +379,9 @@ static void __init at91sam9g45_initialize(void) ...@@ -379,6 +379,9 @@ static void __init at91sam9g45_initialize(void)
arm_pm_idle = at91sam9_idle; arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9g45_restart; arm_pm_restart = at91sam9g45_restart;
at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
/* Register GPIO subsystem */ /* Register GPIO subsystem */
at91_gpio_init(at91sam9g45_gpio, 5); at91_gpio_init(at91sam9g45_gpio, 5);
} }
......
...@@ -224,7 +224,13 @@ static void __init at91sam9n12_map_io(void) ...@@ -224,7 +224,13 @@ static void __init at91sam9n12_map_io(void)
at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE); at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
} }
static void __init at91sam9n12_initialize(void)
{
at91_sysirq_mask_rtc(AT91SAM9N12_BASE_RTC);
}
AT91_SOC_START(at91sam9n12) AT91_SOC_START(at91sam9n12)
.map_io = at91sam9n12_map_io, .map_io = at91sam9n12_map_io,
.register_clocks = at91sam9n12_register_clocks, .register_clocks = at91sam9n12_register_clocks,
.init = at91sam9n12_initialize,
AT91_SOC_END AT91_SOC_END
...@@ -296,6 +296,9 @@ static void __init at91sam9rl_initialize(void) ...@@ -296,6 +296,9 @@ static void __init at91sam9rl_initialize(void)
arm_pm_idle = at91sam9_idle; arm_pm_idle = at91sam9_idle;
arm_pm_restart = at91sam9_alt_restart; arm_pm_restart = at91sam9_alt_restart;
at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
/* Register GPIO subsystem */ /* Register GPIO subsystem */
at91_gpio_init(at91sam9rl_gpio, 4); at91_gpio_init(at91sam9rl_gpio, 4);
} }
......
...@@ -322,6 +322,11 @@ static void __init at91sam9x5_map_io(void) ...@@ -322,6 +322,11 @@ static void __init at91sam9x5_map_io(void)
at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE); at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
} }
static void __init at91sam9x5_initialize(void)
{
at91_sysirq_mask_rtc(AT91SAM9X5_BASE_RTC);
}
/* -------------------------------------------------------------------- /* --------------------------------------------------------------------
* Interrupt initialization * Interrupt initialization
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
...@@ -329,4 +334,5 @@ static void __init at91sam9x5_map_io(void) ...@@ -329,4 +334,5 @@ static void __init at91sam9x5_map_io(void)
AT91_SOC_START(at91sam9x5) AT91_SOC_START(at91sam9x5)
.map_io = at91sam9x5_map_io, .map_io = at91sam9x5_map_io,
.register_clocks = at91sam9x5_register_clocks, .register_clocks = at91sam9x5_register_clocks,
.init = at91sam9x5_initialize,
AT91_SOC_END AT91_SOC_END
...@@ -34,6 +34,8 @@ extern int __init at91_aic_of_init(struct device_node *node, ...@@ -34,6 +34,8 @@ extern int __init at91_aic_of_init(struct device_node *node,
struct device_node *parent); struct device_node *parent);
extern int __init at91_aic5_of_init(struct device_node *node, extern int __init at91_aic5_of_init(struct device_node *node,
struct device_node *parent); struct device_node *parent);
extern void __init at91_sysirq_mask_rtc(u32 rtc_base);
extern void __init at91_sysirq_mask_rtt(u32 rtt_base);
/* Timer */ /* Timer */
......
...@@ -48,6 +48,11 @@ ...@@ -48,6 +48,11 @@
#define AT91SAM9N12_BASE_USART2 0xf8024000 #define AT91SAM9N12_BASE_USART2 0xf8024000
#define AT91SAM9N12_BASE_USART3 0xf8028000 #define AT91SAM9N12_BASE_USART3 0xf8028000
/*
* System Peripherals
*/
#define AT91SAM9N12_BASE_RTC 0xfffffeb0
/* /*
* Internal Memory. * Internal Memory.
*/ */
......
...@@ -54,6 +54,11 @@ ...@@ -54,6 +54,11 @@
#define AT91SAM9X5_BASE_USART1 0xf8020000 #define AT91SAM9X5_BASE_USART1 0xf8020000
#define AT91SAM9X5_BASE_USART2 0xf8024000 #define AT91SAM9X5_BASE_USART2 0xf8024000
/*
* System Peripherals
*/
#define AT91SAM9X5_BASE_RTC 0xfffffeb0
/* /*
* Internal Memory. * Internal Memory.
*/ */
......
...@@ -72,6 +72,11 @@ ...@@ -72,6 +72,11 @@
#define SAMA5D3_BASE_USART2 0xf8020000 #define SAMA5D3_BASE_USART2 0xf8020000
#define SAMA5D3_BASE_USART3 0xf8024000 #define SAMA5D3_BASE_USART3 0xf8024000
/*
* System Peripherals
*/
#define SAMA5D3_BASE_RTC 0xfffffeb0
/* /*
* Internal Memory * Internal Memory
*/ */
......
...@@ -371,7 +371,13 @@ static void __init sama5d3_map_io(void) ...@@ -371,7 +371,13 @@ static void __init sama5d3_map_io(void)
at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE); at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE);
} }
static void __init sama5d3_initialize(void)
{
at91_sysirq_mask_rtc(SAMA5D3_BASE_RTC);
}
AT91_SOC_START(sama5d3) AT91_SOC_START(sama5d3)
.map_io = sama5d3_map_io, .map_io = sama5d3_map_io,
.register_clocks = sama5d3_register_clocks, .register_clocks = sama5d3_register_clocks,
.init = sama5d3_initialize,
AT91_SOC_END AT91_SOC_END
/*
* sysirq_mask.c - System-interrupt masking
*
* Copyright (C) 2013 Johan Hovold <jhovold@gmail.com>
*
* Functions to disable system interrupts from backup-powered peripherals.
*
* The RTC and RTT-peripherals are generally powered by backup power (VDDBU)
* and are not reset on wake-up, user, watchdog or software reset. This means
* that their interrupts may be enabled during early boot (e.g. after a user
* reset).
*
* As the RTC and RTT share the system-interrupt line with the PIT, an
* interrupt occurring before a handler has been installed would lead to the
* system interrupt being disabled and prevent the system from booting.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/io.h>
#include <mach/at91_rtt.h>
#include "generic.h"
#define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */
#define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */
void __init at91_sysirq_mask_rtc(u32 rtc_base)
{
void __iomem *base;
u32 mask;
base = ioremap(rtc_base, 64);
if (!base)
return;
mask = readl_relaxed(base + AT91_RTC_IMR);
if (mask) {
pr_info("AT91: Disabling rtc irq\n");
writel_relaxed(mask, base + AT91_RTC_IDR);
(void)readl_relaxed(base + AT91_RTC_IMR); /* flush */
}
iounmap(base);
}
void __init at91_sysirq_mask_rtt(u32 rtt_base)
{
void __iomem *base;
void __iomem *reg;
u32 mode;
base = ioremap(rtt_base, 16);
if (!base)
return;
reg = base + AT91_RTT_MR;
mode = readl_relaxed(reg);
if (mode & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)) {
pr_info("AT91: Disabling rtt irq\n");
mode &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
writel_relaxed(mode, reg);
(void)readl_relaxed(reg); /* flush */
}
iounmap(base);
}
...@@ -7,7 +7,7 @@ config ARCH_HIGHBANK ...@@ -7,7 +7,7 @@ config ARCH_HIGHBANK
select ARCH_SUPPORTS_BIG_ENDIAN select ARCH_SUPPORTS_BIG_ENDIAN
select ARCH_WANT_OPTIONAL_GPIOLIB select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_AMBA select ARM_AMBA
select ARM_ERRATA_764369 select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_775420 select ARM_ERRATA_775420
select ARM_ERRATA_798181 if SMP select ARM_ERRATA_798181 if SMP
select ARM_GIC select ARM_GIC
......
...@@ -102,8 +102,8 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o ...@@ -102,8 +102,8 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
ifeq ($(CONFIG_PM),y) ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
# i.MX6SL reuses pm-imx6q.c # i.MX6SL reuses i.MX6Q code
obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o
endif endif
# i.MX5 based machines # i.MX5 based machines
......
...@@ -122,13 +122,14 @@ static struct clk_div_table clk_enet_ref_table[] = { ...@@ -122,13 +122,14 @@ static struct clk_div_table clk_enet_ref_table[] = {
{ .val = 1, .div = 10, }, { .val = 1, .div = 10, },
{ .val = 2, .div = 5, }, { .val = 2, .div = 5, },
{ .val = 3, .div = 4, }, { .val = 3, .div = 4, },
{ /* sentinel */ }
}; };
static struct clk_div_table post_div_table[] = { static struct clk_div_table post_div_table[] = {
{ .val = 2, .div = 1, }, { .val = 2, .div = 1, },
{ .val = 1, .div = 2, }, { .val = 1, .div = 2, },
{ .val = 0, .div = 4, }, { .val = 0, .div = 4, },
{ } { /* sentinel */ }
}; };
static struct clk_div_table video_div_table[] = { static struct clk_div_table video_div_table[] = {
...@@ -136,7 +137,7 @@ static struct clk_div_table video_div_table[] = { ...@@ -136,7 +137,7 @@ static struct clk_div_table video_div_table[] = {
{ .val = 1, .div = 2, }, { .val = 1, .div = 2, },
{ .val = 2, .div = 1, }, { .val = 2, .div = 1, },
{ .val = 3, .div = 4, }, { .val = 3, .div = 4, },
{ } { /* sentinel */ }
}; };
static void __init imx6q_clocks_init(struct device_node *ccm_node) static void __init imx6q_clocks_init(struct device_node *ccm_node)
...@@ -298,7 +299,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -298,7 +299,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6); clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
......
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/clk-provider.h> #include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/jiffies.h> #include <linux/jiffies.h>
...@@ -45,33 +46,49 @@ struct clk_pllv3 { ...@@ -45,33 +46,49 @@ struct clk_pllv3 {
#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
{
unsigned long timeout = jiffies + msecs_to_jiffies(10);
u32 val = readl_relaxed(pll->base) & BM_PLL_POWER;
/* No need to wait for lock when pll is not powered up */
if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
return 0;
/* Wait for PLL to lock */
do {
if (readl_relaxed(pll->base) & BM_PLL_LOCK)
break;
if (time_after(jiffies, timeout))
break;
usleep_range(50, 500);
} while (1);
return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
}
static int clk_pllv3_prepare(struct clk_hw *hw) static int clk_pllv3_prepare(struct clk_hw *hw)
{ {
struct clk_pllv3 *pll = to_clk_pllv3(hw); struct clk_pllv3 *pll = to_clk_pllv3(hw);
unsigned long timeout;
u32 val; u32 val;
int ret;
val = readl_relaxed(pll->base); val = readl_relaxed(pll->base);
val &= ~BM_PLL_BYPASS;
if (pll->powerup_set) if (pll->powerup_set)
val |= BM_PLL_POWER; val |= BM_PLL_POWER;
else else
val &= ~BM_PLL_POWER; val &= ~BM_PLL_POWER;
writel_relaxed(val, pll->base); writel_relaxed(val, pll->base);
timeout = jiffies + msecs_to_jiffies(10); ret = clk_pllv3_wait_lock(pll);
/* Wait for PLL to lock */ if (ret)
do { return ret;
if (readl_relaxed(pll->base) & BM_PLL_LOCK)
break; val = readl_relaxed(pll->base);
if (time_after(jiffies, timeout)) val &= ~BM_PLL_BYPASS;
break; writel_relaxed(val, pll->base);
} while (1);
if (readl_relaxed(pll->base) & BM_PLL_LOCK)
return 0; return 0;
else
return -ETIMEDOUT;
} }
static void clk_pllv3_unprepare(struct clk_hw *hw) static void clk_pllv3_unprepare(struct clk_hw *hw)
...@@ -146,7 +163,7 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, ...@@ -146,7 +163,7 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
val |= div; val |= div;
writel_relaxed(val, pll->base); writel_relaxed(val, pll->base);
return 0; return clk_pllv3_wait_lock(pll);
} }
static const struct clk_ops clk_pllv3_ops = { static const struct clk_ops clk_pllv3_ops = {
...@@ -202,7 +219,7 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, ...@@ -202,7 +219,7 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
val |= div; val |= div;
writel_relaxed(val, pll->base); writel_relaxed(val, pll->base);
return 0; return clk_pllv3_wait_lock(pll);
} }
static const struct clk_ops clk_pllv3_sys_ops = { static const struct clk_ops clk_pllv3_sys_ops = {
...@@ -276,7 +293,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, ...@@ -276,7 +293,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
return 0; return clk_pllv3_wait_lock(pll);
} }
static const struct clk_ops clk_pllv3_av_ops = { static const struct clk_ops clk_pllv3_av_ops = {
......
...@@ -127,11 +127,6 @@ static inline void imx_smp_prepare(void) {} ...@@ -127,11 +127,6 @@ static inline void imx_smp_prepare(void) {}
static inline void imx_scu_standby_enable(void) {} static inline void imx_scu_standby_enable(void) {}
#endif #endif
void imx_src_init(void); void imx_src_init(void);
#ifdef CONFIG_HAVE_IMX_SRC
void imx_src_prepare_restart(void);
#else
static inline void imx_src_prepare_restart(void) {}
#endif
void imx_gpc_init(void); void imx_gpc_init(void);
void imx_gpc_pre_suspend(void); void imx_gpc_pre_suspend(void);
void imx_gpc_post_resume(void); void imx_gpc_post_resume(void);
......
...@@ -115,21 +115,6 @@ void imx_set_cpu_arg(int cpu, u32 arg) ...@@ -115,21 +115,6 @@ void imx_set_cpu_arg(int cpu, u32 arg)
writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4); writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
} }
void imx_src_prepare_restart(void)
{
u32 val;
/* clear enable bits of secondary cores */
spin_lock(&scr_lock);
val = readl_relaxed(src_base + SRC_SCR);
val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
writel_relaxed(val, src_base + SRC_SCR);
spin_unlock(&scr_lock);
/* clear persistent entry register of primary core */
writel_relaxed(0, src_base + SRC_GPR1);
}
void __init imx_src_init(void) void __init imx_src_init(void)
{ {
struct device_node *np; struct device_node *np;
......
...@@ -42,9 +42,6 @@ void mxc_restart(enum reboot_mode mode, const char *cmd) ...@@ -42,9 +42,6 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
{ {
unsigned int wcr_enable; unsigned int wcr_enable;
if (cpu_is_imx6q() || cpu_is_imx6dl())
imx_src_prepare_restart();
if (wdog_clk) if (wdog_clk)
clk_enable(wdog_clk); clk_enable(wdog_clk);
...@@ -55,7 +52,14 @@ void mxc_restart(enum reboot_mode mode, const char *cmd) ...@@ -55,7 +52,14 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
/* Assert SRS signal */ /* Assert SRS signal */
__raw_writew(wcr_enable, wdog_base); __raw_writew(wcr_enable, wdog_base);
/* write twice to ensure the request will not get ignored */ /*
* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
* written twice), we add another two writes to ensure there must be at
* least two writes happen in the same one 32kHz clock period. We save
* the target check here, since the writes shouldn't be a huge burden
* for other platforms.
*/
__raw_writew(wcr_enable, wdog_base);
__raw_writew(wcr_enable, wdog_base); __raw_writew(wcr_enable, wdog_base);
/* wait for reset to assert... */ /* wait for reset to assert... */
......
...@@ -198,7 +198,8 @@ static struct mmci_platform_data mmc_data = { ...@@ -198,7 +198,8 @@ static struct mmci_platform_data mmc_data = {
static void cp_clcd_enable(struct clcd_fb *fb) static void cp_clcd_enable(struct clcd_fb *fb)
{ {
struct fb_var_screeninfo *var = &fb->fb.var; struct fb_var_screeninfo *var = &fb->fb.var;
u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2; u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2
| CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1;
if (var->bits_per_pixel <= 8 || if (var->bits_per_pixel <= 8 ||
(var->bits_per_pixel == 16 && var->green.length == 5)) (var->bits_per_pixel == 16 && var->green.length == 5))
......
...@@ -40,7 +40,7 @@ omap-4-5-common = omap4-common.o omap-wakeupgen.o ...@@ -40,7 +40,7 @@ omap-4-5-common = omap4-common.o omap-wakeupgen.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o
obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o
obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common) obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common)
obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) sleep44xx.o
plus_sec := $(call as-instr,.arch_extension sec,+sec) plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
......
...@@ -510,7 +510,7 @@ static int __init beagle_opp_init(void) ...@@ -510,7 +510,7 @@ static int __init beagle_opp_init(void)
mpu_dev = get_cpu_device(0); mpu_dev = get_cpu_device(0);
iva_dev = omap_device_get_by_hwmod_name("iva"); iva_dev = omap_device_get_by_hwmod_name("iva");
if (IS_ERR(mpu_dev) || IS_ERR(iva_dev)) { if (!mpu_dev || IS_ERR(iva_dev)) {
pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n", pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
__func__, mpu_dev, iva_dev); __func__, mpu_dev, iva_dev);
return -ENODEV; return -ENODEV;
......
...@@ -381,6 +381,42 @@ static struct clk_hw_omap dpll4_ck_hw = { ...@@ -381,6 +381,42 @@ static struct clk_hw_omap dpll4_ck_hw = {
DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops); DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
static const struct clk_div_table dpll4_mx_ck_div_table[] = {
{ .div = 1, .val = 1 },
{ .div = 2, .val = 2 },
{ .div = 3, .val = 3 },
{ .div = 4, .val = 4 },
{ .div = 5, .val = 5 },
{ .div = 6, .val = 6 },
{ .div = 7, .val = 7 },
{ .div = 8, .val = 8 },
{ .div = 9, .val = 9 },
{ .div = 10, .val = 10 },
{ .div = 11, .val = 11 },
{ .div = 12, .val = 12 },
{ .div = 13, .val = 13 },
{ .div = 14, .val = 14 },
{ .div = 15, .val = 15 },
{ .div = 16, .val = 16 },
{ .div = 17, .val = 17 },
{ .div = 18, .val = 18 },
{ .div = 19, .val = 19 },
{ .div = 20, .val = 20 },
{ .div = 21, .val = 21 },
{ .div = 22, .val = 22 },
{ .div = 23, .val = 23 },
{ .div = 24, .val = 24 },
{ .div = 25, .val = 25 },
{ .div = 26, .val = 26 },
{ .div = 27, .val = 27 },
{ .div = 28, .val = 28 },
{ .div = 29, .val = 29 },
{ .div = 30, .val = 30 },
{ .div = 31, .val = 31 },
{ .div = 32, .val = 32 },
{ .div = 0 },
};
DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0, DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH, OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
...@@ -524,10 +560,10 @@ static const struct clksel_rate clkout2_src_54m_rates[] = { ...@@ -524,10 +560,10 @@ static const struct clksel_rate clkout2_src_54m_rates[] = {
{ .div = 0 } { .div = 0 }
}; };
DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0, DEFINE_CLK_DIVIDER_TABLE(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH, OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL); 0, dpll4_mx_ck_div_table, NULL);
static struct clk dpll4_m3x2_ck; static struct clk dpll4_m3x2_ck;
...@@ -847,10 +883,10 @@ static struct clk dpll3_m3x2_ck_3630 = { ...@@ -847,10 +883,10 @@ static struct clk dpll3_m3x2_ck_3630 = {
DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1); DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
DEFINE_CLK_DIVIDER(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0, DEFINE_CLK_DIVIDER_TABLE(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH, OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL); 0, dpll4_mx_ck_div_table, NULL);
static struct clk dpll4_m4x2_ck; static struct clk dpll4_m4x2_ck;
...@@ -869,7 +905,8 @@ static struct clk_hw_omap dpll4_m4x2_ck_hw = { ...@@ -869,7 +905,8 @@ static struct clk_hw_omap dpll4_m4x2_ck_hw = {
.clkdm_name = "dpll4_clkdm", .clkdm_name = "dpll4_clkdm",
}; };
DEFINE_STRUCT_CLK(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops); DEFINE_STRUCT_CLK_FLAGS(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names,
dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
static struct clk dpll4_m4x2_ck_3630 = { static struct clk dpll4_m4x2_ck_3630 = {
.name = "dpll4_m4x2_ck", .name = "dpll4_m4x2_ck",
...@@ -877,6 +914,7 @@ static struct clk dpll4_m4x2_ck_3630 = { ...@@ -877,6 +914,7 @@ static struct clk dpll4_m4x2_ck_3630 = {
.parent_names = dpll4_m4x2_ck_parent_names, .parent_names = dpll4_m4x2_ck_parent_names,
.num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names), .num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
.ops = &dpll4_m5x2_ck_3630_ops, .ops = &dpll4_m5x2_ck_3630_ops,
.flags = CLK_SET_RATE_PARENT,
}; };
DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0, DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
...@@ -968,8 +1006,9 @@ static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = { ...@@ -968,8 +1006,9 @@ static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
.clkdm_name = "dss_clkdm", .clkdm_name = "dss_clkdm",
}; };
DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names, DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es1,
aes2_ick_ops); dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
CLK_SET_RATE_PARENT);
static struct clk dss1_alwon_fck_3430es2; static struct clk dss1_alwon_fck_3430es2;
...@@ -983,8 +1022,9 @@ static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = { ...@@ -983,8 +1022,9 @@ static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
.clkdm_name = "dss_clkdm", .clkdm_name = "dss_clkdm",
}; };
DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names, DEFINE_STRUCT_CLK_FLAGS(dss1_alwon_fck_3430es2,
aes2_ick_ops); dss1_alwon_fck_3430es1_parent_names, aes2_ick_ops,
CLK_SET_RATE_PARENT);
static struct clk dss2_alwon_fck; static struct clk dss2_alwon_fck;
......
...@@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0, ...@@ -830,7 +830,8 @@ DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_CM_DSS_DSS_CLKCTRL,
OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL); OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0, DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
CLK_SET_RATE_PARENT,
OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
0x0, NULL); 0x0, NULL);
......
...@@ -83,7 +83,7 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *gpmc_cfg) ...@@ -83,7 +83,7 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *gpmc_cfg)
pdev = platform_device_register_resndata(NULL, "smsc911x", gpmc_cfg->id, pdev = platform_device_register_resndata(NULL, "smsc911x", gpmc_cfg->id,
gpmc_smsc911x_resources, ARRAY_SIZE(gpmc_smsc911x_resources), gpmc_smsc911x_resources, ARRAY_SIZE(gpmc_smsc911x_resources),
&gpmc_smsc911x_config, sizeof(gpmc_smsc911x_config)); &gpmc_smsc911x_config, sizeof(gpmc_smsc911x_config));
if (!pdev) { if (IS_ERR(pdev)) {
pr_err("Unable to register platform device\n"); pr_err("Unable to register platform device\n");
gpio_free(gpmc_cfg->gpio_reset); gpio_free(gpmc_cfg->gpio_reset);
goto free2; goto free2;
......
...@@ -621,6 +621,7 @@ static int _od_suspend_noirq(struct device *dev) ...@@ -621,6 +621,7 @@ static int _od_suspend_noirq(struct device *dev)
if (!ret && !pm_runtime_status_suspended(dev)) { if (!ret && !pm_runtime_status_suspended(dev)) {
if (pm_generic_runtime_suspend(dev) == 0) { if (pm_generic_runtime_suspend(dev) == 0) {
pm_runtime_set_suspended(dev);
omap_device_idle(pdev); omap_device_idle(pdev);
od->flags |= OMAP_DEVICE_SUSPENDED; od->flags |= OMAP_DEVICE_SUSPENDED;
} }
...@@ -634,10 +635,18 @@ static int _od_resume_noirq(struct device *dev) ...@@ -634,10 +635,18 @@ static int _od_resume_noirq(struct device *dev)
struct platform_device *pdev = to_platform_device(dev); struct platform_device *pdev = to_platform_device(dev);
struct omap_device *od = to_omap_device(pdev); struct omap_device *od = to_omap_device(pdev);
if ((od->flags & OMAP_DEVICE_SUSPENDED) && if (od->flags & OMAP_DEVICE_SUSPENDED) {
!pm_runtime_status_suspended(dev)) {
od->flags &= ~OMAP_DEVICE_SUSPENDED; od->flags &= ~OMAP_DEVICE_SUSPENDED;
omap_device_enable(pdev); omap_device_enable(pdev);
/*
* XXX: we run before core runtime pm has resumed itself. At
* this point in time, we just restore the runtime pm state and
* considering symmetric operations in resume, we donot expect
* to fail. If we failed, something changed in core runtime_pm
* framework OR some device driver messed things up, hence, WARN
*/
WARN(pm_runtime_set_active(dev),
"Could not set %s runtime state active\n", dev_name(dev));
pm_generic_runtime_resume(dev); pm_generic_runtime_resume(dev);
} }
......
...@@ -42,7 +42,8 @@ extern u32 omap4_prm_vcvp_read(u8 offset); ...@@ -42,7 +42,8 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
extern void omap4_prm_vcvp_write(u32 val, u8 offset); extern void omap4_prm_vcvp_write(u32 val, u8 offset);
extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX)
void omap44xx_prm_reconfigure_io_chain(void); void omap44xx_prm_reconfigure_io_chain(void);
#else #else
static inline void omap44xx_prm_reconfigure_io_chain(void) static inline void omap44xx_prm_reconfigure_io_chain(void)
......
...@@ -12,7 +12,7 @@ menuconfig ARCH_STI ...@@ -12,7 +12,7 @@ menuconfig ARCH_STI
select HAVE_ARM_SCU if SMP select HAVE_ARM_SCU if SMP
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
select ARM_ERRATA_754322 select ARM_ERRATA_754322
select ARM_ERRATA_764369 select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_775420 select ARM_ERRATA_775420
select PL310_ERRATA_753970 if CACHE_PL310 select PL310_ERRATA_753970 if CACHE_PL310
select PL310_ERRATA_769419 if CACHE_PL310 select PL310_ERRATA_769419 if CACHE_PL310
......
...@@ -90,9 +90,9 @@ static void __init tegra_init_cache(void) ...@@ -90,9 +90,9 @@ static void __init tegra_init_cache(void)
static void __init tegra_init_early(void) static void __init tegra_init_early(void)
{ {
tegra_cpu_reset_handler_init();
tegra_apb_io_init(); tegra_apb_io_init();
tegra_init_fuse(); tegra_init_fuse();
tegra_cpu_reset_handler_init();
tegra_init_cache(); tegra_init_cache();
tegra_powergate_init(); tegra_powergate_init();
tegra_hotplug_init(); tegra_hotplug_init();
......
...@@ -1604,6 +1604,9 @@ static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc, ...@@ -1604,6 +1604,9 @@ static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
pcs->write(mask, pcswi->reg); pcs->write(mask, pcswi->reg);
raw_spin_unlock(&pcs->lock); raw_spin_unlock(&pcs->lock);
} }
if (pcs_soc->rearm)
pcs_soc->rearm();
} }
/** /**
...@@ -1626,8 +1629,6 @@ static void pcs_irq_unmask(struct irq_data *d) ...@@ -1626,8 +1629,6 @@ static void pcs_irq_unmask(struct irq_data *d)
struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d); struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
pcs_irq_set(pcs_soc, d->irq, true); pcs_irq_set(pcs_soc, d->irq, true);
if (pcs_soc->rearm)
pcs_soc->rearm();
} }
/** /**
...@@ -1678,11 +1679,6 @@ static int pcs_irq_handle(struct pcs_soc_data *pcs_soc) ...@@ -1678,11 +1679,6 @@ static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
} }
} }
/*
* For debugging on omaps, you may want to call pcs_soc->rearm()
* here to see wake-up interrupts during runtime also.
*/
return count; return count;
} }
......
...@@ -141,7 +141,6 @@ static int exynos_mipi_dsi_early_blank_mode(struct mipi_dsim_device *dsim, ...@@ -141,7 +141,6 @@ static int exynos_mipi_dsi_early_blank_mode(struct mipi_dsim_device *dsim,
static int exynos_mipi_dsi_blank_mode(struct mipi_dsim_device *dsim, int power) static int exynos_mipi_dsi_blank_mode(struct mipi_dsim_device *dsim, int power)
{ {
struct platform_device *pdev = to_platform_device(dsim->dev);
struct mipi_dsim_lcd_driver *client_drv = dsim->dsim_lcd_drv; struct mipi_dsim_lcd_driver *client_drv = dsim->dsim_lcd_drv;
struct mipi_dsim_lcd_device *client_dev = dsim->dsim_lcd_dev; struct mipi_dsim_lcd_device *client_dev = dsim->dsim_lcd_dev;
......
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