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Commit 71fbc431 authored by Jin Yao's avatar Jin Yao Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Update event list for Icelake Client 

- Update core and uncore events for Icelake client to perf.
- Add ICL metrics.

Based on ICL event list v1.10:

  https://download.01.org/perfmon/ICL/Signed-off-by: default avatarJin Yao <yao.jin@linux.intel.com>
Reviewed-by: default avatarAndi Kleen <ak@linux.intel.com>
Acked-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lore.kernel.org/lkml/c0f27643-bebb-2912-56ed-f7abec7dbde3@linux.intel.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
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tools/perf/pmu-events/arch/x86/icelake/cache.json
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[ [
{ {
"BriefDescription": "L2 code requests",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
"EventCode": "0x24",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x21", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "Counts the total number of L2 code requests.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"BriefDescription": "Demand Data Read miss L2, no rejects" "Speculative": "1",
"UMask": "0xe4"
}, },
{ {
"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
"EventCode": "0x24",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x22", "Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
"PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
"SampleAfterValue": "200003", "SampleAfterValue": "20011",
"BriefDescription": "RFO requests that miss L2 cache" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Demand requests that miss L2 cache",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts L2 cache misses when fetching instructions.",
"EventCode": "0x24",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x24", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Counts demand requests that miss L2 cache.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"BriefDescription": "L2 cache misses when fetching instructions" "Speculative": "1",
"UMask": "0x27"
}, },
{ {
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts demand requests that miss L2 cache.",
"EventCode": "0x24",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x27", "EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS", "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
"SampleAfterValue": "200003", "SampleAfterValue": "100003",
"BriefDescription": "Demand requests that miss L2 cache" "Speculative": "1",
"UMask": "0x4"
}, },
{ {
"BriefDescription": "RFO requests that hit L2 cache",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts Software prefetch requests that miss the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.",
"EventCode": "0x24",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x28", "EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L2_RQSTS.SWPF_MISS", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"BriefDescription": "SW prefetch requests that miss L2 cache." "Speculative": "1",
"UMask": "0xc2"
}, },
{ {
"BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
"EventCode": "0x24",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0xc1", "Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.FB_HIT",
"PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
"SampleAfterValue": "200003", "SampleAfterValue": "100007",
"BriefDescription": "Demand Data Read requests that hit L2 cache" "UMask": "0x40"
}, },
{ {
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
"EventCode": "0x24",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0xc2", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "200003", "SampleAfterValue": "1000003",
"BriefDescription": "RFO requests that hit L2 cache" "Speculative": "1",
"UMask": "0x8"
}, },
{ {
"BriefDescription": "L2 cache lines filling L2",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
"EventCode": "0x24",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0xc4", "EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
"SampleAfterValue": "200003", "SampleAfterValue": "100003",
"BriefDescription": "L2 cache hits when fetching instructions, code reads." "Speculative": "1",
"UMask": "0x1f"
}, },
{ {
"BriefDescription": "Retired load instructions that split across a cacheline boundary.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts Software prefetch requests that hit the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.",
"EventCode": "0x24",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0xc8", "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
"PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L2_RQSTS.SWPF_HIT", "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
"SampleAfterValue": "200003", "SampleAfterValue": "100003",
"BriefDescription": "SW prefetch requests that hit L2 cache." "UMask": "0x41"
}, },
{ {
"BriefDescription": "Retired load instructions with L3 cache hits as data sources",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
"EventCode": "0x24",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0xe1", "Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_HIT",
"PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
"SampleAfterValue": "200003", "SampleAfterValue": "100021",
"BriefDescription": "Demand Data Read requests" "UMask": "0x4"
}, },
{ {
"BriefDescription": "Demand Data Read miss L2, no rejects",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
"EventCode": "0x24",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0xe2", "EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"BriefDescription": "RFO requests to L2 cache" "Speculative": "1",
"UMask": "0x21"
}, },
{ {
"BriefDescription": "L2 cache misses when fetching instructions",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the total number of L2 code requests.",
"EventCode": "0x24",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0xe4", "EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts L2 cache misses when fetching instructions.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"BriefDescription": "L2 code requests" "Speculative": "1",
"UMask": "0x24"
}, },
{ {
"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts demand requests to L2 cache.",
"EventCode": "0x24",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0xe7", "EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "200003", "SampleAfterValue": "1000003",
"BriefDescription": "Demand requests to L2 cache" "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
"EventCode": "0x48",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of L1D misses that are outstanding" "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "All retired load instructions.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
"EventCode": "0x48",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_LOADS",
"PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES", "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions for loads.",
"SampleAfterValue": "2000003", "SampleAfterValue": "1000003",
"BriefDescription": "Cycles with L1D load Misses outstanding.", "UMask": "0x81"
"CounterMask": "1"
}, },
{ {
"BriefDescription": "L2 writebacks that access L2 cache",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"EventCode": "0x48",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L1D_PEND_MISS.FB_FULL", "PublicDescription": "Counts L2 writebacks that access L2 cache.",
"SampleAfterValue": "2000003", "SampleAfterValue": "200003",
"BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability." "Speculative": "1",
"UMask": "0x40"
}, },
{ {
"BriefDescription": "Demand Data Read requests",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"EventCode": "0x48",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
"SampleAfterValue": "2000003", "SampleAfterValue": "200003",
"BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.", "Speculative": "1",
"CounterMask": "1", "UMask": "0xe1"
"EdgeDetect": "1"
}, },
{ {
"BriefDescription": "Demand Data Read transactions pending for off-core. Highly correlated.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"EventCode": "0x48",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L1D_PEND_MISS.L2_STALL", "PublicDescription": "Counts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the core.",
"SampleAfterValue": "2000003", "SampleAfterValue": "1000003",
"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Demand Data Read requests that hit L2 cache",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
"EventCode": "0x51",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
"SampleAfterValue": "2000003", "SampleAfterValue": "200003",
"BriefDescription": "Counts the number of cache lines replaced in L1 data cache." "Speculative": "1",
"UMask": "0xc1"
}, },
{ {
"BriefDescription": "Cycles the superQ cannot take any more entries.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
"EventCode": "0x60",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "EventCode": "0xf4",
"EventName": "SQ_MISC.SQ_FULL",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", "PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take any more entries.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.", "Speculative": "1",
"CounterMask": "1" "UMask": "0x4"
}, },
{ {
"BriefDescription": "Cycles with L1D load Misses outstanding.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
"EventCode": "0x60",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
"SampleAfterValue": "2000003", "SampleAfterValue": "1000003",
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore" "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Demand Data Read requests sent to uncore",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
"EventCode": "0x60",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", "Speculative": "1",
"CounterMask": "1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Retired load instructions with L1 cache hits as data sources",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
"EventCode": "0xB0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
"PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
"SampleAfterValue": "100003", "SampleAfterValue": "1000003",
"BriefDescription": "Demand Data Read requests sent to uncore" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
"EventCode": "0xB0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "100003", "SampleAfterValue": "1000003",
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM" "Speculative": "1",
"UMask": "0x8"
}, },
{ {
"BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
"EventCode": "0xB0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "100003", "SampleAfterValue": "1000003",
"BriefDescription": "Demand and prefetch data reads" "Speculative": "1",
"UMask": "0x4"
}, },
{ {
"BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
"EventCode": "0xB0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x80", "EventCode": "0x48",
"EventName": "L1D_PEND_MISS.L2_STALL",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "100003", "SampleAfterValue": "1000003",
"BriefDescription": "Any memory transaction that reached the SQ." "Speculative": "1",
"UMask": "0x4"
}, },
{ {
"PEBS": "1", "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired load instructions that true miss the STLB.",
"EventCode": "0xD0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x11", "Data_LA": "1",
"EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
"PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
"SampleAfterValue": "100003", "SampleAfterValue": "200003",
"BriefDescription": "Retired load instructions that miss the STLB.", "UMask": "0x2"
"Data_LA": "1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Retired load instructions with locked access.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired store instructions that true miss the STLB.",
"EventCode": "0xD0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x12", "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS",
"PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", "PublicDescription": "Counts retired load instructions with locked access.",
"SampleAfterValue": "100003", "SampleAfterValue": "100007",
"BriefDescription": "Retired store instructions that miss the STLB.", "UMask": "0x21"
},
{
"BriefDescription": "Retired load instructions missed L3 cache as data sources",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"L1_Hit_Indication": "1" "EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L3_MISS",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
"SampleAfterValue": "50021",
"UMask": "0x20"
}, },
{ {
"BriefDescription": "All retired store instructions.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.ALL_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores.",
"SampleAfterValue": "1000003",
"UMask": "0x82"
},
{
"BriefDescription": "Demand requests to L2 cache",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired load instructions with locked access.",
"EventCode": "0xD0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x21", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS", "PublicDescription": "Counts demand requests to L2 cache.",
"SampleAfterValue": "100007", "SampleAfterValue": "200003",
"BriefDescription": "Retired load instructions with locked access.", "Speculative": "1",
"Data_LA": "1" "UMask": "0xe7"
}, },
{ {
"PEBS": "1", "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
"EventCode": "0xD0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x41", "EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS", "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
"SampleAfterValue": "100003", "SampleAfterValue": "200003",
"BriefDescription": "Retired load instructions that split across a cacheline boundary.", "Speculative": "1",
"Data_LA": "1" "UMask": "0xc4"
}, },
{ {
"PEBS": "1", "BriefDescription": "Demand and prefetch data reads",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
"EventCode": "0xD0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x42", "EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES", "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Retired store instructions that split across a cacheline boundary.", "Speculative": "1",
"Data_LA": "1", "UMask": "0x8"
"L1_Hit_Indication": "1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Core-originated cacheable demand requests missed L3",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2e",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "SW prefetch requests that miss L2 cache.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions for loads.",
"EventCode": "0xD0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x81", "EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_MISS",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_INST_RETIRED.ALL_LOADS", "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.",
"SampleAfterValue": "2000003", "SampleAfterValue": "200003",
"BriefDescription": "All retired load instructions.", "Speculative": "1",
"Data_LA": "1" "UMask": "0x28"
}, },
{ {
"PEBS": "1", "BriefDescription": "Retired load instructions missed L1 cache as data sources",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores.",
"EventCode": "0xD0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x82",
"PEBScounters": "0,1,2,3",
"EventName": "MEM_INST_RETIRED.ALL_STORES",
"SampleAfterValue": "2000003",
"BriefDescription": "All retired store instructions.",
"Data_LA": "1", "Data_LA": "1",
"L1_Hit_Indication": "1" "EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L1_MISS",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
"SampleAfterValue": "200003",
"UMask": "0x8"
}, },
{ {
"PEBS": "1", "BriefDescription": "Number of L1D misses that are outstanding",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
"EventCode": "0xD1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_RETIRED.L1_HIT", "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
"SampleAfterValue": "2000003", "SampleAfterValue": "1000003",
"BriefDescription": "Retired load instructions with L1 cache hits as data sources", "Speculative": "1",
"Data_LA": "1" "UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
"EventCode": "0xD1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_RETIRED.L2_HIT", "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
"SampleAfterValue": "100003", "SampleAfterValue": "1000003",
"BriefDescription": "Retired load instructions with L2 cache hits as data sources", "Speculative": "1",
"Data_LA": "1" "UMask": "0x2"
}, },
{ {
"PEBS": "1", "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
"EventCode": "0xD1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
"PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_RETIRED.L3_HIT", "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
"SampleAfterValue": "50021", "SampleAfterValue": "20011",
"BriefDescription": "Retired load instructions with L3 cache hits as data sources", "UMask": "0x4"
"Data_LA": "1"
}, },
{ {
"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
"SampleAfterValue": "20011",
"UMask": "0x2"
},
{
"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
"EventCode": "0xD1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "Data_LA": "1",
"EventCode": "0xd2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
"PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_RETIRED.L1_MISS", "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Retired load instructions missed L1 cache as data sources", "UMask": "0x8"
"Data_LA": "1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Retired store instructions that miss the STLB.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
"EventCode": "0xD1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_RETIRED.L2_MISS", "PublicDescription": "Counts retired store instructions that true miss the STLB.",
"SampleAfterValue": "50021", "SampleAfterValue": "100003",
"BriefDescription": "Retired load instructions missed L2 cache as data sources", "UMask": "0x12"
"Data_LA": "1"
}, },
{ {
"PEBS": "1", "BriefDescription": "RFO requests to L2 cache",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
"EventCode": "0xD1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x20", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_RETIRED.L3_MISS", "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
"SampleAfterValue": "100007", "SampleAfterValue": "200003",
"BriefDescription": "Retired load instructions missed L3 cache as data sources", "Speculative": "1",
"Data_LA": "1" "UMask": "0xe2"
}, },
{ {
"PEBS": "1", "BriefDescription": "Retired load instructions missed L2 cache as data sources",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", "Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd1", "EventCode": "0xd1",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
"PEBS": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
"SampleAfterValue": "100021",
"UMask": "0x10"
},
{
"BriefDescription": "Store Read transactions pending for off-core. Highly correlated.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x40", "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_RETIRED.FB_HIT", "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.",
"SampleAfterValue": "100007", "SampleAfterValue": "1000003",
"BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", "Speculative": "1",
"Data_LA": "1" "UMask": "0x4"
}, },
{ {
"PEBS": "1", "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
"EventCode": "0xd2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "EventCode": "0xF2",
"EventName": "L2_LINES_OUT.SILENT",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
"SampleAfterValue": "20011", "SampleAfterValue": "200003",
"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", "Speculative": "1",
"Data_LA": "1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Retired store instructions that split across a cacheline boundary.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003",
"UMask": "0x42"
},
{
"BriefDescription": "SW prefetch requests that hit L2 cache.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
"EventCode": "0xd2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "EventCode": "0x24",
"EventName": "L2_RQSTS.SWPF_HIT",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.",
"SampleAfterValue": "20011", "SampleAfterValue": "200003",
"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", "Speculative": "1",
"Data_LA": "1" "UMask": "0xc8"
}, },
{ {
"BriefDescription": "Retired load instructions that miss the STLB.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions that true miss the STLB.",
"SampleAfterValue": "100003",
"UMask": "0x11"
},
{
"BriefDescription": "RFO requests that miss L2 cache",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
"EventCode": "0xd2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
"SampleAfterValue": "20011", "SampleAfterValue": "200003",
"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", "Speculative": "1",
"Data_LA": "1" "UMask": "0x22"
}, },
{ {
"PEBS": "1", "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
"EventCode": "0xd2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "EventCode": "0xF2",
"EventName": "L2_LINES_OUT.NON_SILENT",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
"SampleAfterValue": "100003", "SampleAfterValue": "200003",
"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", "Speculative": "1",
"Data_LA": "1" "UMask": "0x2"
}, },
{ {
"BriefDescription": "Any memory transaction that reached the SQ.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
"EventCode": "0xF1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1f", "EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "L2_LINES_IN.ALL", "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "L2 cache lines filling L2" "Speculative": "1",
"UMask": "0x80"
}, },
{ {
"BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take any more entries.",
"EventCode": "0xF4",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "EventCode": "0xf2",
"EventName": "L2_LINES_OUT.USELESS_HWPF",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "SQ_MISC.SQ_FULL", "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache",
"SampleAfterValue": "100003", "SampleAfterValue": "200003",
"BriefDescription": "Cycles the thread is active and superQ cannot take any more entries." "Speculative": "1",
"UMask": "0x4"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/icelake/floating-point.json
View file @ 71fbc431
[ [
{ {
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts all microcode Floating Point assists.",
"EventCode": "0xC1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "ASSISTS.FP",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Counts all microcode FP assists.", "UMask": "0x40"
"CounterMask": "1"
}, },
{ {
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"EventCode": "0xc7",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." "UMask": "0x8"
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"EventCode": "0xc7",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "SampleAfterValue": "100003",
"SampleAfterValue": "2000003", "UMask": "0x80"
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element."
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"EventCode": "0xc7",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x4", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "SampleAfterValue": "100003",
"SampleAfterValue": "2000003", "UMask": "0x1"
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element."
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"EventCode": "0xc7",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x8", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "SampleAfterValue": "100003",
"SampleAfterValue": "2000003", "UMask": "0x4"
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element."
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"EventCode": "0xc7",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x10", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "SampleAfterValue": "100003",
"SampleAfterValue": "2000003", "UMask": "0x20"
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element."
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"EventCode": "0xc7",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x20", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "SampleAfterValue": "100003",
"SampleAfterValue": "2000003", "UMask": "0x2"
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element."
}, },
{ {
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"EventCode": "0xc7",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x40", "EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "SampleAfterValue": "100003",
"SampleAfterValue": "2000003", "UMask": "0x10"
"BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element."
}, },
{ {
"BriefDescription": "Counts all microcode FP assists.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
"EventCode": "0xc7",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x80", "EventCode": "0xc1",
"EventName": "ASSISTS.FP",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PublicDescription": "Counts all microcode Floating Point assists.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." "Speculative": "1",
"UMask": "0x2"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/icelake/frontend.json
View file @ 71fbc431
[ [
{ {
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "IDQ.MITE_UOPS", "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path" "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Retired Instructions who experienced DSB miss.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x79", "EventCode": "0xc6",
"Counter": "0,1,2,3", "EventName": "FRONTEND_RETIRED.DSB_MISS",
"UMask": "0x4", "MSRIndex": "0x3F7",
"PEBScounters": "0,1,2,3", "MSRValue": "0x11",
"EventName": "IDQ.MITE_CYCLES_OK", "PEBS": "1",
"SampleAfterValue": "2000003", "PEBScounters": "0,1,2,3,4,5,6,7",
"BriefDescription": "Cycles MITE is delivering optimal number of Uops", "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
"CounterMask": "5" "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Cycles MITE is delivering optimal number of Uops",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "CounterMask": "5",
"PEBScounters": "0,1,2,3",
"EventName": "IDQ.MITE_CYCLES_ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles MITE is delivering any Uop",
"CounterMask": "1"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"EventCode": "0x79", "EventCode": "0x79",
"Counter": "0,1,2,3", "EventName": "IDQ.MITE_CYCLES_OK",
"UMask": "0x8",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "IDQ.DSB_UOPS", "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path" "Speculative": "1",
"UMask": "0x4"
}, },
{ {
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x79", "EventCode": "0xc6",
"Counter": "0,1,2,3", "EventName": "FRONTEND_RETIRED.ITLB_MISS",
"UMask": "0x8", "MSRIndex": "0x3F7",
"PEBScounters": "0,1,2,3", "MSRValue": "0x14",
"EventName": "IDQ.DSB_CYCLES_OK", "PEBS": "1",
"SampleAfterValue": "2000003", "PEBScounters": "0,1,2,3,4,5,6,7",
"BriefDescription": "Cycles DSB is delivering optimal number of Uops", "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
"CounterMask": "5" "SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x79", "CounterMask": "5",
"Counter": "0,1,2,3", "EventCode": "0x9c",
"UMask": "0x8", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "IDQ.DSB_CYCLES_ANY", "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"SampleAfterValue": "2000003", "SampleAfterValue": "1000003",
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", "Speculative": "1",
"CounterMask": "1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x30", "EventCode": "0x80",
"EventName": "ICACHE_16B.IFDATA_STALL",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "IDQ.MS_SWITCHES", "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
"SampleAfterValue": "2000003", "SampleAfterValue": "500009",
"BriefDescription": "Number of switches from DSB or MITE to the MS", "Speculative": "1",
"CounterMask": "1", "UMask": "0x4"
"EdgeDetect": "1"
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x79", "EventCode": "0xc6",
"Counter": "0,1,2,3", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"UMask": "0x30", "MSRIndex": "0x3F7",
"PEBScounters": "0,1,2,3", "MSRValue": "0x510006",
"EventName": "IDQ.MS_UOPS", "PEBS": "1",
"SampleAfterValue": "2000003", "PEBScounters": "0,1,2,3,4,5,6,7",
"BriefDescription": "Uops delivered to IDQ while MS is busy" "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"EventCode": "0x79",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x30", "CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_ANY",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "IDQ.MS_CYCLES_ANY", "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", "Speculative": "1",
"CounterMask": "1" "UMask": "0x8"
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x80", "EventCode": "0xc6",
"Counter": "0,1,2,3", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"UMask": "0x4", "MSRIndex": "0x3F7",
"PEBScounters": "0,1,2,3", "MSRValue": "0x100206",
"EventName": "ICACHE_16B.IFDATA_STALL", "PEBS": "1",
"SampleAfterValue": "2000003", "PEBScounters": "0,1,2,3,4,5,6,7",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss." "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "DSB-to-MITE switch true penalty cycles.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
"EventCode": "0x83",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "EventCode": "0xab",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "ICACHE_64B.IFTAG_HIT", "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
"SampleAfterValue": "200003", "SampleAfterValue": "100003",
"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity." "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x83", "EventCode": "0xc6",
"Counter": "0,1,2,3", "EventName": "FRONTEND_RETIRED.STLB_MISS",
"UMask": "0x2", "MSRIndex": "0x3F7",
"PEBScounters": "0,1,2,3", "MSRValue": "0x15",
"EventName": "ICACHE_64B.IFTAG_MISS", "PEBS": "1",
"SampleAfterValue": "200003", "PEBScounters": "0,1,2,3,4,5,6,7",
"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity." "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
"EventCode": "0x83",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "ICACHE_64B.IFTAG_STALL", "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "200003",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"EventCode": "0x9C",
"Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled" "Speculative": "1",
"UMask": "0x4"
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"EventCode": "0x9c",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7",
"MSRValue": "0x504006",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100007",
"BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled", "TakenAlone": "1",
"CounterMask": "5" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"EventCode": "0x9C",
"Invert": "1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7",
"MSRValue": "0x502006",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100007",
"BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled", "TakenAlone": "1",
"CounterMask": "1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Cycles MITE is delivering any Uop",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
"EventCode": "0xAB",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES_ANY",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "DSB-to-MITE switch true penalty cycles." "Speculative": "1",
"UMask": "0x4"
}, },
{ {
"PEBS": "1", "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
"EventCode": "0xC6",
"MSRValue": "0x11",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc6",
"PEBScounters": "0,1,2,3,4,5,6,7", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x500206",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"BriefDescription": "Retired Instructions who experienced DSB miss.", "TakenAlone": "1",
"TakenAlone": "1" "UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", "Counter": "0,1,2,3",
"EventCode": "0xC6", "CounterMask": "1",
"MSRValue": "0x12", "EdgeDetect": "1",
"Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xab",
"UMask": "0x1", "EventName": "DSB2MITE_SWITCHES.COUNT",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3",
"EventName": "FRONTEND_RETIRED.L1I_MISS", "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.",
"MSRIndex": "0x3F7", "SampleAfterValue": "100003",
"SampleAfterValue": "100007", "Speculative": "1",
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", "UMask": "0x2"
"TakenAlone": "1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
"EventCode": "0xC6",
"MSRValue": "0x13",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc6",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "FRONTEND_RETIRED.L2_MISS", "EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x13",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", "TakenAlone": "1",
"TakenAlone": "1" "UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_HIT",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
"EventCode": "0xC6",
"MSRValue": "0x14",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc6",
"PEBScounters": "0,1,2,3,4,5,6,7", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x520006",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"BriefDescription": "Retired Instructions who experienced iTLB true miss.", "TakenAlone": "1",
"TakenAlone": "1" "UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
"EventCode": "0xC6",
"MSRValue": "0x15",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"Invert": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "FRONTEND_RETIRED.STLB_MISS", "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"MSRIndex": "0x3F7", "SampleAfterValue": "1000003",
"SampleAfterValue": "100007", "Speculative": "1",
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", "UMask": "0x1"
"TakenAlone": "1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",
"EventCode": "0xC6",
"MSRValue": "0x500206",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc6",
"PEBScounters": "0,1,2,3,4,5,6,7", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x501006",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.", "TakenAlone": "1",
"TakenAlone": "1" "UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
"EventCode": "0xC6",
"MSRValue": "0x500406",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc6",
"PEBScounters": "0,1,2,3,4,5,6,7", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x508006",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", "TakenAlone": "1",
"TakenAlone": "1" "UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
"EventCode": "0xC6",
"MSRValue": "0x500806",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc6",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x500806",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", "TakenAlone": "1",
"TakenAlone": "1" "UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
"EventCode": "0xC6",
"MSRValue": "0x501006",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc6",
"PEBScounters": "0,1,2,3,4,5,6,7", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x500106",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", "TakenAlone": "1",
"TakenAlone": "1" "UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
"EventCode": "0xC6",
"MSRValue": "0x502006",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc6",
"PEBScounters": "0,1,2,3,4,5,6,7", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x500406",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", "TakenAlone": "1",
"TakenAlone": "1" "UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Number of switches from DSB or MITE to the MS",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3",
"EventCode": "0xC6", "CounterMask": "1",
"MSRValue": "0x504006", "EdgeDetect": "1",
"Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x79",
"UMask": "0x1", "EventName": "IDQ.MS_SWITCHES",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"MSRIndex": "0x3F7", "SampleAfterValue": "100003",
"SampleAfterValue": "100007", "Speculative": "1",
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", "UMask": "0x30"
"TakenAlone": "1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0x83",
"MSRValue": "0x508006", "EventName": "ICACHE_64B.IFTAG_STALL",
"Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3",
"UMask": "0x1", "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
"PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "200003",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "Speculative": "1",
"MSRIndex": "0x3F7", "UMask": "0x4"
"SampleAfterValue": "100007",
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
"TakenAlone": "1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Uops delivered to IDQ while MS is busy",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3",
"EventCode": "0xC6", "EventCode": "0x79",
"MSRValue": "0x510006", "EventName": "IDQ.MS_UOPS",
"Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3",
"UMask": "0x1", "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
"PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "Speculative": "1",
"MSRIndex": "0x3F7", "UMask": "0x30"
"SampleAfterValue": "100007",
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
"TakenAlone": "1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_MISS",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES_ANY",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x30"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
"EventCode": "0xC6",
"MSRValue": "0x520006",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc6",
"PEBScounters": "0,1,2,3,4,5,6,7", "EventName": "FRONTEND_RETIRED.L1I_MISS",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7", "MSRIndex": "0x3F7",
"MSRValue": "0x12",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", "TakenAlone": "1",
"TakenAlone": "1" "UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES_OK",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
"EventCode": "0xC6",
"MSRValue": "0x100206",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0x9c",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
"MSRIndex": "0x3F7", "SampleAfterValue": "1000003",
"SampleAfterValue": "100007", "Speculative": "1",
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", "UMask": "0x1"
"TakenAlone": "1"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json 0 → 100644
View file @ 71fbc431
[
{
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
"BriefDescription": "Instructions Per Cycle (per Logical Processor)",
"MetricGroup": "Summary",
"MetricName": "IPC"
},
{
"MetricExpr": "UOPS_RETIRED.SLOTS / INST_RETIRED.ANY",
"BriefDescription": "Uops Per Instruction",
"MetricGroup": "Pipeline;Retire",
"MetricName": "UPI"
},
{
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
"BriefDescription": "Instruction per taken branch",
"MetricGroup": "Branches;FetchBW;PGO",
"MetricName": "IpTB"
},
{
"MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)",
"BriefDescription": "Cycles Per Instruction (per Logical Processor)",
"MetricGroup": "Pipeline",
"MetricName": "CPI"
},
{
"MetricExpr": "CPU_CLK_UNHALTED.THREAD",
"BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
"MetricGroup": "Pipeline",
"MetricName": "CLKS"
},
{
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.DISTRIBUTED",
"BriefDescription": "Instructions Per Cycle (per physical core)",
"MetricGroup": "SMT;TmaL1",
"MetricName": "CoreIPC"
},
{
"MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED",
"BriefDescription": "Floating Point Operations Per Cycle",
"MetricGroup": "Flops",
"MetricName": "FLOPc"
},
{
"MetricExpr": "UOPS_EXECUTED.THREAD / ( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 )",
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",
"MetricGroup": "Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
"MetricGroup": "BrMispredicts",
"MetricName": "IpMispredict"
},
{
"MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED",
"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
"MetricGroup": "SMT",
"MetricName": "CORE_CLKS"
},
{
"MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
"BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
"MetricGroup": "InsType",
"MetricName": "IpLoad"
},
{
"MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
"BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
"MetricGroup": "InsType",
"MetricName": "IpStore"
},
{
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
"BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
"MetricGroup": "Branches;InsType",
"MetricName": "IpBranch"
},
{
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
"BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
"MetricGroup": "Branches",
"MetricName": "IpCall"
},
{
"MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
"BriefDescription": "Branch instructions per taken branch. ",
"MetricGroup": "Branches;PGO",
"MetricName": "BpTkBranch"
},
{
"MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )",
"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
"MetricGroup": "Flops;FpArith;InsType",
"MetricName": "IpFLOP"
},
{
"MetricExpr": "INST_RETIRED.ANY",
"BriefDescription": "Total number of retired Instructions",
"MetricGroup": "Summary;TmaL1",
"MetricName": "Instructions"
},
{
"MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
"BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)",
"MetricGroup": "LSD",
"MetricName": "LSD_Coverage"
},
{
"MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
"MetricGroup": "DSB;FetchBW",
"MetricName": "DSB_Coverage"
},
{
"MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )",
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)",
"MetricGroup": "MemoryBound;MemoryLat",
"MetricName": "Load_Miss_Real_Latency"
},
{
"MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
"MetricGroup": "MemoryBound;MemoryBW",
"MetricName": "MLP"
},
{
"MetricConstraint": "NO_NMI_WATCHDOG",
"MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )",
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricGroup": "MemoryTLB",
"MetricName": "Page_Walks_Utilization"
},
{
"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
"BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
"MetricGroup": "MemoryBW",
"MetricName": "L1D_Cache_Fill_BW"
},
{
"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
"BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
"MetricGroup": "MemoryBW",
"MetricName": "L2_Cache_Fill_BW"
},
{
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricGroup": "MemoryBW",
"MetricName": "L3_Cache_Fill_BW"
},
{
"MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
"BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
"MetricGroup": "MemoryBW;Offcore",
"MetricName": "L3_Cache_Access_BW"
},
{
"MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
"MetricGroup": "CacheMisses",
"MetricName": "L1MPKI"
},
{
"MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
"MetricGroup": "CacheMisses",
"MetricName": "L2MPKI"
},
{
"MetricExpr": "1000 * ( ( OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD ) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS ) / INST_RETIRED.ANY",
"BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)",
"MetricGroup": "CacheMisses;Offcore",
"MetricName": "L2MPKI_All"
},
{
"MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
"MetricGroup": "CacheMisses",
"MetricName": "L3MPKI"
},
{
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
"BriefDescription": "Average CPU Utilization",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time",
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
"MetricGroup": "Summary;Power",
"MetricName": "Average_Frequency"
},
{
"MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / 1000000000 ) / duration_time",
"BriefDescription": "Giga Floating Point Operations Per Second",
"MetricGroup": "Flops;HPC",
"MetricName": "GFLOPs"
},
{
"MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC",
"BriefDescription": "Average Frequency Utilization relative nominal frequency",
"MetricGroup": "Power",
"MetricName": "Turbo_Utilization"
},
{
"MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED",
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
{
"MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD",
"BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
"MetricGroup": "OS",
"MetricName": "Kernel_Utilization"
},
{
"MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000",
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
"MetricGroup": "HPC;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
{
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricGroup": "Branches;OS",
"MetricName": "IpFarBranch"
},
{
"MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
"BriefDescription": "C3 residency percent per core",
"MetricGroup": "Power",
"MetricName": "C3_Core_Residency"
},
{
"MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
"BriefDescription": "C6 residency percent per core",
"MetricGroup": "Power",
"MetricName": "C6_Core_Residency"
},
{
"MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
"BriefDescription": "C7 residency percent per core",
"MetricGroup": "Power",
"MetricName": "C7_Core_Residency"
},
{
"MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
"BriefDescription": "C2 residency percent per package",
"MetricGroup": "Power",
"MetricName": "C2_Pkg_Residency"
},
{
"MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
"BriefDescription": "C3 residency percent per package",
"MetricGroup": "Power",
"MetricName": "C3_Pkg_Residency"
},
{
"MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
"BriefDescription": "C6 residency percent per package",
"MetricGroup": "Power",
"MetricName": "C6_Pkg_Residency"
},
{
"MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
"BriefDescription": "C7 residency percent per package",
"MetricGroup": "Power",
"MetricName": "C7_Pkg_Residency"
}
]
tools/perf/pmu-events/arch/x86/icelake/memory.json
View file @ 71fbc431
[ [
{ {
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
"EventCode": "0x54",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "EventCode": "0x54",
"PEBScounters": "0,1,2,3",
"EventName": "TX_MEM.ABORT_CONFLICT", "EventName": "TX_MEM.ABORT_CONFLICT",
"SampleAfterValue": "2000003", "PEBScounters": "0,1,2,3",
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address" "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Speculatively counts the number Transactional Synchronization Extensions (TSX) Aborts due to a data capacity limitation for transactional writes.", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x54", "EventCode": "0xc8",
"Counter": "0,1,2,3", "EventName": "HLE_RETIRED.ABORTED",
"UMask": "0x2", "PEBScounters": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of times HLE abort was triggered.",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "SampleAfterValue": "100003",
"SampleAfterValue": "2000003", "UMask": "0x4"
"BriefDescription": "Speculatively counts the number TSX Aborts due to a data capacity limitation for transactional writes."
}, },
{ {
"BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
"EventCode": "0x54",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00001",
"Offcore": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer" "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x54", "Data_LA": "1",
"Counter": "0,1,2,3", "EventCode": "0xcd",
"UMask": "0x8", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"PEBScounters": "0,1,2,3", "MSRIndex": "0x3F6",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "MSRValue": "0x10",
"SampleAfterValue": "2000003", "PEBS": "2",
"BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero." "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "20011",
"TakenAlone": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that was not supplied by the L3 cache.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
"EventCode": "0x54",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00010",
"Offcore": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer" "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MEM",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
"EventCode": "0x54",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x20", "EventCode": "0x54",
"PEBScounters": "0,1,2,3",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"SampleAfterValue": "2000003", "PEBScounters": "0,1,2,3",
"BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer." "PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x20"
}, },
{ {
"BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times we could not allocate Lock Buffer.",
"EventCode": "0x54",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x40", "EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero." "Speculative": "1",
"UMask": "0x8"
}, },
{ {
"BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
"EventCode": "0x5d",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "TX_EXEC.MISC2", "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region" "Speculative": "1",
"UMask": "0x4"
}, },
{ {
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
"EventCode": "0x5d",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x4", "EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "TX_EXEC.MISC3", "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded" "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Cycles where data return is pending for a Demand Data Read request who miss L3 cache.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"EventCode": "0xA3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", "PublicDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
"SampleAfterValue": "2000003", "SampleAfterValue": "1000003",
"BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", "Speculative": "1",
"CounterMask": "2" "UMask": "0x10"
}, },
{ {
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"EventCode": "0xA3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x6", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00002",
"Offcore": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", "Speculative": "1",
"CounterMask": "6" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"MSRIndex": "0x3F6",
"MSRValue": "0x200",
"PEBS": "2",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "101",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of times an RTM execution successfully committed",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts the number of times RTM commit succeeded.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Demand Data Read requests who miss L3 cache.",
"EventCode": "0xB0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Demand Data Read requests who miss L3 cache" "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
"EventCode": "0xc3",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_EVENTS",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Number of machine clears due to memory ordering conflicts." "UMask": "0x80"
}, },
{ {
"BriefDescription": "Number of times an HLE execution successfully committed",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.",
"EventCode": "0xC8",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc8",
"EventName": "HLE_RETIRED.COMMIT",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "HLE_RETIRED.START", "PublicDescription": "Counts the number of times HLE commit succeeded.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of times an HLE execution started." "UMask": "0x2"
}, },
{ {
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times HLE commit succeeded.",
"EventCode": "0xC8",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "HLE_RETIRED.COMMIT", "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of times an HLE execution successfully committed", "UMask": "0x40"
"Data_LA": "1"
}, },
{ {
"BriefDescription": "Number of machine clears due to memory ordering conflicts.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times HLE abort was triggered.",
"EventCode": "0xc8",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x4", "EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "HLE_RETIRED.ABORTED", "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one)." "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3",
"EventCode": "0xC8", "EventCode": "0x54",
"Counter": "0,1,2,3,4,5,6,7", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"UMask": "0x8", "PEBScounters": "0,1,2,3",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
"EventName": "HLE_RETIRED.ABORTED_MEM", "SampleAfterValue": "100003",
"SampleAfterValue": "2000003", "Speculative": "1",
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts)." "UMask": "0x10"
}, },
{ {
"BriefDescription": "Counts streaming stores that was not supplied by the L3 cache.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", "Counter": "0,1,2,3",
"EventCode": "0xC8", "EventCode": "0xB7, 0xBB",
"Counter": "0,1,2,3,4,5,6,7", "EventName": "OCR.STREAMING_WR.L3_MISS",
"UMask": "0x20", "MSRIndex": "0x1a6,0x1a7",
"PEBScounters": "0,1,2,3,4,5,6,7", "MSRValue": "0x3FFFC00800",
"EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", "Offcore": "1",
"SampleAfterValue": "2000003", "PEBScounters": "0,1,2,3",
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.)." "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).", "Counter": "0,1,2,3",
"EventCode": "0xC8", "EventCode": "0x54",
"Counter": "0,1,2,3,4,5,6,7", "EventName": "TX_MEM.ABORT_CAPACITY_READ",
"UMask": "0x80", "PEBScounters": "0,1,2,3",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
"EventName": "HLE_RETIRED.ABORTED_EVENTS", "SampleAfterValue": "100003",
"SampleAfterValue": "2000003", "Speculative": "1",
"BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts)." "UMask": "0x80"
}, },
{ {
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", "Counter": "0,1,2,3",
"EventCode": "0xC9", "EventCode": "0xB7, 0xBB",
"Counter": "0,1,2,3,4,5,6,7", "EventName": "OCR.OTHER.L3_MISS",
"UMask": "0x1", "MSRIndex": "0x1a6,0x1a7",
"PEBScounters": "0,1,2,3,4,5,6,7", "MSRValue": "0x3FFFC08000",
"EventName": "RTM_RETIRED.START", "Offcore": "1",
"SampleAfterValue": "2000003", "PEBScounters": "0,1,2,3",
"BriefDescription": "Number of times an RTM execution started." "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times RTM commit succeeded.", "Counter": "0,1,2,3",
"EventCode": "0xC9", "EventCode": "0xB7, 0xBB",
"Counter": "0,1,2,3,4,5,6,7", "EventName": "OCR.HWPF_L2_RFO.L3_MISS",
"UMask": "0x2", "MSRIndex": "0x1a6,0x1a7",
"PEBScounters": "0,1,2,3,4,5,6,7", "MSRValue": "0x3FFFC00020",
"EventName": "RTM_RETIRED.COMMIT", "Offcore": "1",
"SampleAfterValue": "2000003", "PEBScounters": "0,1,2,3",
"BriefDescription": "Number of times an RTM execution successfully committed" "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Demand Data Read requests who miss L3 cache",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times RTM abort was triggered.", "Counter": "0,1,2,3",
"EventCode": "0xc9", "EventCode": "0xb0",
"Counter": "0,1,2,3,4,5,6,7", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
"UMask": "0x4", "PEBScounters": "0,1,2,3",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Demand Data Read requests who miss L3 cache.",
"EventName": "RTM_RETIRED.ABORTED", "SampleAfterValue": "100003",
"SampleAfterValue": "2000003", "Speculative": "1",
"BriefDescription": "Number of times an RTM execution aborted.", "UMask": "0x10"
"Data_LA": "1"
}, },
{ {
"BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", "Counter": "0,1,2,3",
"EventCode": "0xC9", "CounterMask": "2",
"Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xA3",
"UMask": "0x8", "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3",
"EventName": "RTM_RETIRED.ABORTED_MEM", "SampleAfterValue": "1000003",
"SampleAfterValue": "2000003", "Speculative": "1",
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)" "UMask": "0x2"
}, },
{ {
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
"EventCode": "0xC9",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x20", "EventCode": "0xc9",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
"SampleAfterValue": "2000003", "PEBScounters": "0,1,2,3,4,5,6,7",
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions" "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
"SampleAfterValue": "100003",
"UMask": "0x20"
}, },
{ {
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
"EventCode": "0xC9",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x40", "EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_EVENTS",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type" "UMask": "0x80"
}, },
{ {
"BriefDescription": "Number of times an HLE execution started.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
"EventCode": "0xC9",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x80", "EventCode": "0xc8",
"EventName": "HLE_RETIRED.START",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "RTM_RETIRED.ABORTED_EVENTS", "PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)" "UMask": "0x1"
}, },
{ {
"PEBS": "2", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x4",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "Data_LA": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6", "MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", "TakenAlone": "1",
"TakenAlone": "1" "UMask": "0x1"
}, },
{ {
"PEBS": "2", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x8",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "1009",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times we could not allocate Lock Buffer.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x40"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6", "MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "50021", "SampleAfterValue": "50021",
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", "TakenAlone": "1",
"TakenAlone": "1" "UMask": "0x1"
}, },
{ {
"PEBS": "2", "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x10",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "Data_LA": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"MSRIndex": "0x3F6", "MSRIndex": "0x3F6",
"SampleAfterValue": "20011", "MSRValue": "0x100",
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", "PEBS": "2",
"TakenAlone": "1" "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "503",
"TakenAlone": "1",
"UMask": "0x1"
}, },
{ {
"PEBS": "2", "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x6"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x20",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"MSRIndex": "0x3F6",
"MSRValue": "0x40",
"PEBS": "2",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "2003",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"MSRIndex": "0x3F6", "MSRIndex": "0x3F6",
"MSRValue": "0x20",
"PEBS": "2",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", "TakenAlone": "1",
"TakenAlone": "1" "UMask": "0x1"
}, },
{ {
"PEBS": "2", "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x40",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MEM",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
"MSRIndex": "0x3F6", "SampleAfterValue": "100003",
"SampleAfterValue": "2003", "UMask": "0x8"
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
"TakenAlone": "1"
}, },
{ {
"PEBS": "2", "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00400",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FFFC00004",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of times an RTM execution aborted.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x80",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "PublicDescription": "Counts the number of times RTM abort was triggered.",
"MSRIndex": "0x3F6", "SampleAfterValue": "100003",
"SampleAfterValue": "1009", "UMask": "0x4"
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
"TakenAlone": "1"
}, },
{ {
"PEBS": "2", "BriefDescription": "Number of times an RTM execution started.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x100",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
"MSRIndex": "0x3F6", "SampleAfterValue": "100003",
"SampleAfterValue": "503", "UMask": "0x1"
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
"TakenAlone": "1"
}, },
{ {
"PEBS": "2", "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
"EventCode": "0xcd",
"MSRValue": "0x200",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
"MSRIndex": "0x3F6", "SampleAfterValue": "100003",
"SampleAfterValue": "101", "UMask": "0x20"
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", },
"TakenAlone": "1" {
"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x4"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/icelake/other.json
View file @ 71fbc431
[ [
{ {
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the Top-down Microarchitecture Analysis method. This event is counted on a designated fixed counter (Fixed Counter 3) and is an architectural event.", "Counter": "0,1,2,3",
"Counter": "35", "EventCode": "0xB7, 0xBB",
"UMask": "0x4", "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
"PEBScounters": "35", "MSRIndex": "0x1a6,0x1a7",
"EventName": "TOPDOWN.SLOTS", "MSRValue": "0x01003C8000",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184000020",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184008000",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184000010",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of PREFETCHNTA instructions executed.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.NTA",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x02003C0002",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010004",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C0400",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184008000",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010002",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x02003C8000",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01003C0002",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xa4",
"EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
"SampleAfterValue": "10000003", "SampleAfterValue": "10000003",
"BriefDescription": "Counts the number of available slots for an unhalted logical processor." "Speculative": "1",
"UMask": "0x8"
}, },
{ {
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
"EventCode": "0x28",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x7", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01003C0010",
"Offcore": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "CORE_POWER.LVL0_TURBO_LICENSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "200003", "SampleAfterValue": "100003",
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts streaming stores that have any type of response.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010800",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts streaming stores that DRAM supplied the request.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
"EventCode": "0x28",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x18", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184000800",
"Offcore": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010020",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184000010",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1E003C8000",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010010",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C0010",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL1_TURBO_LICENSE", "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule." "Speculative": "1",
"UMask": "0x18"
}, },
{ {
"BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.",
"EventCode": "0x28",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x20", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x02003C0001",
"Offcore": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "200003", "SampleAfterValue": "100003",
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
"EventCode": "0x32",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1E003C0001",
"Offcore": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "SW_PREFETCH_ACCESS.NTA", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of PREFETCHNTA instructions executed." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
"EventCode": "0x32",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0010",
"Offcore": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "SW_PREFETCH_ACCESS.T0", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of PREFETCHT0 instructions executed." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts demand data reads that DRAM supplied the request.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
"EventCode": "0x32",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184000001",
"Offcore": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "SW_PREFETCH_ACCESS.T1_T2", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts streaming stores that DRAM supplied the request.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of PREFETCHW instructions executed.", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184000800",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184000004",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01003C0004",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184000020",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184000004",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0002",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x02003C0400",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1E003C0020",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0010",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0001",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C0020",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01003C0001",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C8000",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
"CollectPEBSRecord": "2",
"Counter": "35",
"EventName": "TOPDOWN.SLOTS",
"PEBScounters": "35",
"PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
"SampleAfterValue": "10000003",
"Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x32", "EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T1_T2",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x4"
},
{
"BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x8", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C0001",
"Offcore": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of PREFETCHW instructions executed." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184000400",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
"EventCode": "0xa4",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xa4",
"EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "TOPDOWN.SLOTS_P", "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
"SampleAfterValue": "10000003", "SampleAfterValue": "10000003",
"BriefDescription": "Counts the number of available slots for an unhalted logical processor." "Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01003C0020",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of PREFETCHT0 instructions executed.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T0",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x2"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010001",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0004",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0020",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000018000",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Number of PREFETCHW instructions executed.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of PREFETCHW instructions executed.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1E003C0010",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184000400",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184000002",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"EventCode": "0xA4",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0xc1",
"EventName": "ASSISTS.ANY",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
"SampleAfterValue": "10000003", "SampleAfterValue": "100003",
"BriefDescription": "Issue slots where no uops were being issued due to lack of back end resources." "Speculative": "1",
"UMask": "0x7"
}, },
{ {
"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x02003C0010",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C0004",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x20"
},
{
"BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.STREAMING_WR.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C0800",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x02003C0020",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184000001",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1E003C0004",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C0002",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L3.L3_HIT.ANY",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FC03C2380",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
"EventCode": "0xc1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x7", "EventCode": "0xa4",
"EventName": "TOPDOWN.SLOTS_P",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "ASSISTS.ANY", "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
"SampleAfterValue": "10000003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x01003C0400",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1E003C0002",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0000010400",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0184000002",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x7"
},
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0020",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x02003C0004",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware." "Speculative": "1",
"UMask": "0x1"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/icelake/pipeline.json
View file @ 71fbc431
[ [
{ {
"BriefDescription": "Mispredicted indirect CALL instructions retired.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", "Counter": "0,1,2,3,4,5,6,7",
"Counter": "32", "EventCode": "0xc5",
"UMask": "0x1", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
"PEBScounters": "32", "PEBS": "1",
"EventName": "INST_RETIRED.ANY", "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003", "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.",
"BriefDescription": "Number of instructions retired. Fixed Counter - architectural event" "SampleAfterValue": "50021",
"UMask": "0x2"
}, },
{ {
"PEBS": "2", "BriefDescription": "Number of uops executed on the core.",
"CollectPEBSRecord": "3", "CollectPEBSRecord": "2",
"PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.", "Counter": "0,1,2,3,4,5,6,7",
"Counter": "32", "EventCode": "0xB1",
"UMask": "0x1", "EventName": "UOPS_EXECUTED.CORE",
"PEBScounters": "32", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "INST_RETIRED.PREC_DIST", "PublicDescription": "Counts the number of uops executed from any thread.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution" "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Number of uops executed on port 4 and 9",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", "Counter": "0,1,2,3,4,5,6,7",
"Counter": "33", "EventCode": "0xa1",
"UMask": "0x2", "EventName": "UOPS_DISPATCHED.PORT_4_9",
"PEBScounters": "33", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Core cycles when the thread is not in halt state" "Speculative": "1",
"UMask": "0x10"
}, },
{ {
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", "Counter": "0,1,2,3,4,5,6,7",
"Counter": "34", "EventCode": "0xb1",
"UMask": "0x3", "EventName": "UOPS_EXECUTED.THREAD",
"PEBScounters": "34", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when the core is not in halt state." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Not taken branch instructions retired.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when: a. preceding store conflicts with the load (incomplete overlap),b. store forwarding is impossible due to u-arch limitations, c. preceding lock RMW operations are not forwarded, d. store has the no-forward bit set (uncacheable/page-split/masked stores), e. all-blocking stores are used (mostly, fences and port I/O), and others. The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide.", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x03", "EventCode": "0xc4",
"Counter": "0,1,2,3", "EventName": "BR_INST_RETIRED.COND_NTAKEN",
"UMask": "0x2", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts not taken branch instructions retired.",
"SampleAfterValue": "100003", "SampleAfterValue": "400009",
"BriefDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded." "UMask": "0x10"
}, },
{ {
"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x03", "EventCode": "0x0e",
"Counter": "0,1,2,3", "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
"UMask": "0x8", "PEBScounters": "0,1,2,3,4,5,6,7",
"PEBScounters": "0,1,2,3", "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
"EventName": "LD_BLOCKS.NO_SR",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use." "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x07", "CounterMask": "1",
"Counter": "0,1,2,3", "EventCode": "0xB1",
"UMask": "0x1", "EventName": "UOPS_EXECUTED.STALL_CYCLES",
"PEBScounters": "0,1,2,3", "Invert": "1",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "All indirect branch instructions retired (excluding RETs. TSX aborts are considered indirect branch).",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.INDIRECT",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts all indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "False dependencies in MOB due to partial compare on address." "UMask": "0x80"
}, },
{ {
"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
"EventCode": "0x0D",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "INT_MISC.RECOVERY_CYCLES", "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread" "Speculative": "1",
"UMask": "0x10"
}, },
{ {
"BriefDescription": "Number of uops executed on port 2 and 3",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
"EventCode": "0x0D",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x3", "EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_2_3",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "INT_MISC.ALL_RECOVERY_CYCLES", "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", "Speculative": "1",
"CounterMask": "1" "UMask": "0x4"
}, },
{ {
"BriefDescription": "Taken branch instructions retired.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
"EventCode": "0x0d",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x80", "EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "PublicDescription": "Counts taken branch instructions retired.",
"SampleAfterValue": "2000003", "SampleAfterValue": "400009",
"BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path." "UMask": "0x20"
}, },
{ {
"BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PREFETCH.SWPF",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of uops executed on port 1",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
"EventCode": "0x0E",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Uops that RAT issues to RS" "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Number of Uops delivered by the LSD.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xa8",
"EventName": "LSD.UOPS",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Number of uops executed on port 5",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
"EventCode": "0x0E",
"Invert": "1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_5",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_ISSUED.STALL_CYCLES", "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread", "Speculative": "1",
"CounterMask": "1" "UMask": "0x20"
}, },
{ {
"BriefDescription": "Number of uops executed on port 6",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
"EventCode": "0x14",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x9", "EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_6",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "ARITH.DIVIDER_ACTIVE", "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", "Speculative": "1",
"CounterMask": "1" "UMask": "0x40"
}, },
{ {
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
"EventCode": "0x3C",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
"SampleAfterValue": "2000003", "SampleAfterValue": "500009",
"BriefDescription": "Thread cycles when thread is not in halt state" "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.",
"EventCode": "0x3C",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "CounterMask": "2",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
"SampleAfterValue": "25003", "SampleAfterValue": "1000003",
"BriefDescription": "Core crystal clock cycles when the thread is unhalted." "Speculative": "1",
"UMask": "0x40"
}, },
{ {
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
"EventCode": "0x3C",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.",
"SampleAfterValue": "25003", "SampleAfterValue": "25003",
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
"EventCode": "0x4c",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "LOAD_HIT_PREFETCH.SWPF", "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
"SampleAfterValue": "100003", "SampleAfterValue": "500009",
"BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "False dependencies in MOB due to partial compare on address.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)", "Counter": "0,1,2,3",
"EventCode": "0x5E", "EventCode": "0x07",
"Counter": "0,1,2,3,4,5,6,7", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"UMask": "0x1", "PEBScounters": "0,1,2,3",
"PEBScounters": "0,1,2,3,4,5,6,7", "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.",
"EventName": "RS_EVENTS.EMPTY_CYCLES", "SampleAfterValue": "100003",
"SampleAfterValue": "2000003", "Speculative": "1",
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
"EventCode": "0x5E",
"Invert": "1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0x5e",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "RS_EVENTS.EMPTY_END", "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)",
"SampleAfterValue": "2000003", "SampleAfterValue": "1000003",
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", "Speculative": "1",
"CounterMask": "1", "UMask": "0x1"
"EdgeDetect": "1"
}, },
{ {
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
"EventCode": "0x87",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "ILD_STALL.LCP", "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Stalls caused by changing prefix length of the instruction." "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Cycles without actually retired uops.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
"EventCode": "0xa1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "CounterMask": "1",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
"Invert": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_DISPATCHED.PORT_0", "PublicDescription": "This event counts cycles without actually retired uops.",
"SampleAfterValue": "2000003", "SampleAfterValue": "1000003",
"BriefDescription": "Number of uops executed on port 0" "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Far branch instructions retired.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
"EventCode": "0xa1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_DISPATCHED.PORT_1", "PublicDescription": "Counts far branch instructions retired.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100007",
"BriefDescription": "Number of uops executed on port 1" "UMask": "0x40"
}, },
{ {
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.",
"EventCode": "0xa1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x4", "CounterMask": "16",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_DISPATCHED.PORT_2_3", "SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x10"
},
{
"BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
"CollectPEBSRecord": "2",
"Counter": "32",
"EventName": "INST_RETIRED.ANY",
"PEBS": "1",
"PEBScounters": "32",
"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of uops executed on port 2 and 3" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.",
"EventCode": "0xa1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x10", "EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.SCOREBOARD",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_DISPATCHED.PORT_4_9", "SampleAfterValue": "100003",
"SampleAfterValue": "2000003", "Speculative": "1",
"BriefDescription": "Number of uops executed on port 4 and 9" "UMask": "0x2"
}, },
{ {
"BriefDescription": "Increments whenever there is an update to the LBR array.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
"EventCode": "0xa1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x20", "EventCode": "0xcc",
"EventName": "MISC_RETIRED.LBR_INSERTS",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_DISPATCHED.PORT_5", "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of uops executed on port 5" "UMask": "0x20"
}, },
{ {
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
"EventCode": "0xa1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x40", "EventCode": "0xc0",
"EventName": "INST_RETIRED.ANY_P",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_DISPATCHED.PORT_6", "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003"
"BriefDescription": "Number of uops executed on port 6"
}, },
{ {
"BriefDescription": "Counts the number of x87 uops dispatched.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.",
"EventCode": "0xa1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x80", "EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.X87",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_DISPATCHED.PORT_7_8", "PublicDescription": "Counts the number of x87 uops executed.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of uops executed on port 7 and 8" "Speculative": "1",
"UMask": "0x10"
}, },
{ {
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"EventCode": "0xa2",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "RESOURCE_STALLS.SCOREBOARD", "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations." "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
"EventCode": "0xA2",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x8", "EventCode": "0xa2",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "RESOURCE_STALLS.SB", "EventName": "RESOURCE_STALLS.SB",
"SampleAfterValue": "2000003", "PEBScounters": "0,1,2,3,4,5,6,7",
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync)." "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x8"
}, },
{ {
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"EventCode": "0xA3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", "Speculative": "1",
"CounterMask": "1" "UMask": "0x8"
}, },
{ {
"BriefDescription": "Number of machine clears (nukes) of any type.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"EventCode": "0xA3",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x4", "CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.COUNT",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "PublicDescription": "Counts the number of machine clears (nukes) of any type.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Total execution stalls.", "Speculative": "1",
"CounterMask": "4" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"EventCode": "0xA3", "Counter": "0,1,2,3,4,5,6,7",
"Counter": "0,1,2,3", "EventCode": "0xc5",
"UMask": "0x5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBScounters": "0,1,2,3", "PEBS": "1",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003", "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", "SampleAfterValue": "50021",
"CounterMask": "5" "UMask": "0x20"
}, },
{ {
"BriefDescription": "Return instructions retired.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"EventCode": "0xA3", "Counter": "0,1,2,3,4,5,6,7",
"Counter": "0,1,2,3", "EventCode": "0xc4",
"UMask": "0x8", "EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBScounters": "0,1,2,3", "PEBS": "1",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003", "PublicDescription": "Counts return instructions retired.",
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", "SampleAfterValue": "100007",
"CounterMask": "8" "UMask": "0x8"
}, },
{ {
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"EventCode": "0xA3", "Counter": "0,1,2,3,4,5,6,7",
"Counter": "0,1,2,3", "CounterMask": "1",
"UMask": "0xc", "EventCode": "0x14",
"PEBScounters": "0,1,2,3", "EventName": "ARITH.DIVIDER_ACTIVE",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003", "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", "SampleAfterValue": "1000003",
"CounterMask": "12" "Speculative": "1",
"UMask": "0x9"
}, },
{ {
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"EventCode": "0xA3",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x10", "EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles while memory subsystem has an outstanding load.", "Speculative": "1",
"CounterMask": "16" "UMask": "0x2"
}, },
{ {
"BriefDescription": "Cycles without actually retired instructions.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"EventCode": "0xA3",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x14", "CounterMask": "1",
"EventCode": "0xc0",
"EventName": "INST_RETIRED.STALL_CYCLES",
"Invert": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", "PublicDescription": "This event counts cycles without actually retired instructions.",
"SampleAfterValue": "2000003", "SampleAfterValue": "1000003",
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", "Speculative": "1",
"CounterMask": "20" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
"EventCode": "0xa6",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND_NTAKEN",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
"SampleAfterValue": "50021",
"UMask": "0x10"
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
"CollectPEBSRecord": "2",
"Counter": "33",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PEBScounters": "33",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty." "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Taken conditional branch instructions retired.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
"EventCode": "0xa6",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x4", "EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_TAKEN",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PublicDescription": "Counts taken conditional branch instructions retired.",
"SampleAfterValue": "2000003", "SampleAfterValue": "400009",
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty." "UMask": "0x1"
}, },
{ {
"BriefDescription": "Direct and indirect near call instructions retired.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
"EventCode": "0xA6",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x40", "EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES", "PublicDescription": "Counts both direct and indirect near call instructions retired.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100007",
"BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", "UMask": "0x2"
"CounterMask": "2"
}, },
{ {
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.",
"EventCode": "0xa6",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x80", "CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load." "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", "Counter": "32",
"EventCode": "0xA8", "EventName": "INST_RETIRED.PREC_DIST",
"Counter": "0,1,2,3", "PEBS": "1",
"UMask": "0x1", "PEBScounters": "32",
"PEBScounters": "0,1,2,3", "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
"EventName": "LSD.UOPS",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of Uops delivered by the LSD." "UMask": "0x1"
}, },
{ {
"BriefDescription": "Total execution stalls.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8", "CounterMask": "4",
"Counter": "0,1,2,3", "EventCode": "0xa3",
"UMask": "0x1", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "LSD.CYCLES_ACTIVE", "SampleAfterValue": "1000003",
"SampleAfterValue": "2000003", "Speculative": "1",
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", "UMask": "0x4"
"CounterMask": "1"
}, },
{ {
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
"EventCode": "0xa8",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "LSD.CYCLES_OK", "SampleAfterValue": "1000003",
"SampleAfterValue": "2000003", "Speculative": "1",
"BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", "UMask": "0xc"
"CounterMask": "5"
}, },
{ {
"BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"EventCode": "0xB1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xcc",
"PEBScounters": "0,1,2,3,4,5,6,7", "EventName": "MISC_RETIRED.PAUSE_INST",
"EventName": "UOPS_EXECUTED.THREAD", "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle." "UMask": "0x40"
}, },
{ {
"BriefDescription": "Self-modifying code (SMC) detected.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
"EventCode": "0xB1",
"Invert": "1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.SMC",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_EXECUTED.STALL_CYCLES", "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", "Speculative": "1",
"CounterMask": "1" "UMask": "0x4"
}, },
{ {
"BriefDescription": "Uops that RAT issues to RS",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
"EventCode": "0xb1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0x0e",
"EventName": "UOPS_ISSUED.ANY",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1", "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles where at least 1 uop was executed per-thread", "Speculative": "1",
"CounterMask": "1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Cycles where at least 2 uops were executed per-thread.", "Counter": "0,1,2,3",
"EventCode": "0xb1", "CounterMask": "5",
"Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa3",
"UMask": "0x1", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2", "SampleAfterValue": "1000003",
"SampleAfterValue": "2000003", "Speculative": "1",
"BriefDescription": "Cycles where at least 2 uops were executed per-thread", "UMask": "0x5"
"CounterMask": "2"
}, },
{ {
"BriefDescription": "Reference cycles when the core is not in halt state.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Cycles where at least 3 uops were executed per-thread.", "Counter": "34",
"EventCode": "0xb1", "EventName": "CPU_CLK_UNHALTED.REF_TSC",
"Counter": "0,1,2,3,4,5,6,7", "PEBScounters": "34",
"UMask": "0x1", "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles where at least 3 uops were executed per-thread", "Speculative": "1",
"CounterMask": "3" "UMask": "0x3"
}, },
{ {
"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
"EventCode": "0xb1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.ALL_RECOVERY_CYCLES",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4", "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles where at least 4 uops were executed per-thread", "Speculative": "1",
"CounterMask": "4" "UMask": "0x3"
}, },
{ {
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of uops executed from any thread.",
"EventCode": "0xB1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of uops executed on the core." "Speculative": "1",
"UMask": "0x4"
}, },
{ {
"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
"EventCode": "0xB1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0xa6",
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", "Speculative": "1",
"CounterMask": "1" "UMask": "0x8"
}, },
{ {
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x8"
},
{
"BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
"EventCode": "0xB1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0x0d",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
"SampleAfterValue": "2000003", "SampleAfterValue": "500009",
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", "Speculative": "1",
"CounterMask": "2" "UMask": "0x80"
}, },
{ {
"BriefDescription": "Cycles with less than 10 actually retired uops.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
"EventCode": "0xB1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "CounterMask": "10",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
"Invert": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "PublicDescription": "Counts the number of cycles using always true condition (uops_ret &amp;lt; 16) applied to non PEBS uops retired event.",
"SampleAfterValue": "2000003", "SampleAfterValue": "1000003",
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", "UMask": "0x2"
"CounterMask": "3"
}, },
{ {
"BriefDescription": "All branch instructions retired.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
"EventCode": "0xB1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "PublicDescription": "Counts all branch instructions retired.",
"SampleAfterValue": "2000003", "SampleAfterValue": "400009"
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
"CounterMask": "4"
}, },
{ {
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of x87 uops executed.",
"EventCode": "0xB1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x10", "CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_END",
"Invert": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_EXECUTED.X87", "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Counts the number of x87 uops dispatched." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"EventCode": "0xC0",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xec",
"EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "INST_RETIRED.ANY_P", "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of instructions retired. General Counter - architectural event" "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of cycles using always true condition (uops_ret &amp;lt; 16) applied to non PEBS uops retired event.",
"EventCode": "0xC2",
"Invert": "1",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES", "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
"SampleAfterValue": "2000003", "SampleAfterValue": "25003",
"BriefDescription": "Cycles with less than 10 actually retired uops.", "Speculative": "1",
"CounterMask": "10" "UMask": "0x2"
}, },
{ {
"BriefDescription": "Thread cycles when thread is not in halt state",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the retirement slots used each cycle.",
"EventCode": "0xc2",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "UOPS_RETIRED.SLOTS", "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Retirement slots used." "Speculative": "1"
}, },
{ {
"BriefDescription": "Mispredicted conditional branch instructions retired.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of machine clears (nukes) of any type.",
"EventCode": "0xC3",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.COND",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MACHINE_CLEARS.COUNT", "PublicDescription": "Counts mispredicted conditional branch instructions retired.",
"SampleAfterValue": "100003", "SampleAfterValue": "50021",
"BriefDescription": "Number of machine clears (nukes) of any type.", "UMask": "0x11"
"CounterMask": "1",
"EdgeDetect": "1"
}, },
{ {
"BriefDescription": "Number of uops executed on port 0",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
"EventCode": "0xC3",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x4", "EventCode": "0xa1",
"EventName": "UOPS_DISPATCHED.PORT_0",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
"SampleAfterValue": "100003", "SampleAfterValue": "2000003",
"BriefDescription": "Self-modifying code (SMC) detected." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Conditional branch instructions retired.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts all branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PublicDescription": "Counts conditional branch instructions retired.",
"SampleAfterValue": "400009", "SampleAfterValue": "400009",
"BriefDescription": "All branch instructions retired." "UMask": "0x11"
}, },
{ {
"PEBS": "1", "BriefDescription": "Retirement slots used.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts taken conditional branch instructions retired.",
"EventCode": "0xc4",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "EventCode": "0xc2",
"EventName": "UOPS_RETIRED.SLOTS",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "BR_INST_RETIRED.COND_TAKEN", "PublicDescription": "Counts the retirement slots used each cycle.",
"SampleAfterValue": "400009", "SampleAfterValue": "2000003",
"BriefDescription": "Taken conditional branch instructions retired." "UMask": "0x2"
}, },
{ {
"PEBS": "1", "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts both direct and indirect near call instructions retired.", "Counter": "0,1,2,3",
"EventCode": "0xC4", "CounterMask": "5",
"Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa8",
"UMask": "0x2", "EventName": "LSD.CYCLES_OK",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3",
"EventName": "BR_INST_RETIRED.NEAR_CALL", "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
"SampleAfterValue": "100007", "SampleAfterValue": "2000003",
"BriefDescription": "Direct and indirect near call instructions retired." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts return instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x8", "EventCode": "0x3c",
"EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "BR_INST_RETIRED.NEAR_RETURN", "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"SampleAfterValue": "100007", "SampleAfterValue": "2000003",
"BriefDescription": "Return instructions retired." "Speculative": "1",
"UMask": "0x8"
}, },
{ {
"PEBS": "1", "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts not taken branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x10", "CounterMask": "3",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "BR_INST_RETIRED.COND_NTAKEN", "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
"SampleAfterValue": "400009", "SampleAfterValue": "2000003",
"BriefDescription": "Not taken branch instructions retired." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts conditional branch instructions retired.",
"EventCode": "0xc4",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x11", "CounterMask": "2",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "BR_INST_RETIRED.COND", "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
"SampleAfterValue": "400009", "SampleAfterValue": "2000003",
"BriefDescription": "Conditional branch instructions retired." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts taken branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x20", "CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
"SampleAfterValue": "400009", "SampleAfterValue": "2000003",
"BriefDescription": "Taken branch instructions retired." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts far branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x40", "CounterMask": "4",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "BR_INST_RETIRED.FAR_BRANCH", "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
"SampleAfterValue": "100007", "SampleAfterValue": "2000003",
"BriefDescription": "Far branch instructions retired." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts all indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", "Counter": "0,1,2,3",
"EventCode": "0xc4", "CounterMask": "1",
"Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xA3",
"UMask": "0x80", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3",
"EventName": "BR_INST_RETIRED.INDIRECT", "SampleAfterValue": "1000003",
"SampleAfterValue": "100003", "Speculative": "1",
"BriefDescription": "All indirect branch instructions retired (excluding RETs. TSX aborts are considered indirect branch)." "UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
"EventCode": "0xC5",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
"Invert": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
"SampleAfterValue": "400009", "SampleAfterValue": "1000003",
"BriefDescription": "All mispredicted branch instructions retired.", "Speculative": "1",
"Data_LA": "1" "UMask": "0x1"
}, },
{ {
"PEBS": "1", "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts taken conditional mispredicted branch instructions retired.",
"EventCode": "0xc5",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x1", "CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "BR_MISP_RETIRED.COND_TAKEN", "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
"SampleAfterValue": "400009", "SampleAfterValue": "2000003",
"BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS", "Speculative": "1",
"Data_LA": "1" "UMask": "0x2"
}, },
{ {
"PEBS": "1", "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts mispredicted conditional branch instructions retired.",
"EventCode": "0xc5",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x11", "CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "BR_MISP_RETIRED.COND", "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
"SampleAfterValue": "400009", "SampleAfterValue": "2000003",
"BriefDescription": "Mispredicted conditional branch instructions retired.", "Speculative": "1",
"Data_LA": "1" "UMask": "0x2"
}, },
{ {
"PEBS": "1", "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
"EventCode": "0xC5",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x20", "EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.INDIRECT",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
"SampleAfterValue": "400009", "SampleAfterValue": "50021",
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", "UMask": "0x80"
"Data_LA": "1"
}, },
{ {
"PEBS": "1", "BriefDescription": "TMA slots where uops got dropped",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
"EventCode": "0xC5",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x80", "EventCode": "0x0d",
"EventName": "INT_MISC.UOP_DROPPING",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "BR_MISP_RETIRED.INDIRECT", "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
"SampleAfterValue": "100003", "SampleAfterValue": "1000003",
"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", "Speculative": "1",
"Data_LA": "1" "UMask": "0x10"
}, },
{ {
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
"EventCode": "0xcc",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x20", "CounterMask": "20",
"EventCode": "0xa3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "MISC_RETIRED.LBR_INSERTS", "SampleAfterValue": "1000003",
"SampleAfterValue": "2000003", "Speculative": "1",
"BriefDescription": "Increments whenever there is an update to the LBR array." "UMask": "0x14"
}, },
{ {
"PublicDescription": "Counts number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted).", "BriefDescription": "Number of uops executed on port 7 and 8",
"EventCode": "0xcc", "CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x40", "EventCode": "0xa1",
"EventName": "MISC_RETIRED.PAUSE_INST", "EventName": "UOPS_DISPATCHED.PORT_7_8",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"BriefDescription": "Number of retired PAUSE instructions." "Speculative": "1",
"UMask": "0x80"
}, },
{ {
"BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", "Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xE6", "EventCode": "0xc5",
"Counter": "0,1,2,3", "EventName": "BR_MISP_RETIRED.COND_TAKEN",
"UMask": "0x1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "BACLEARS.ANY", "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.",
"SampleAfterValue": "100003", "SampleAfterValue": "50021",
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end." "UMask": "0x1"
}, },
{ {
"BriefDescription": "All mispredicted branch instructions retired.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"EventCode": "0xec",
"Counter": "0,1,2,3,4,5,6,7", "Counter": "0,1,2,3,4,5,6,7",
"UMask": "0x2", "EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7", "PEBScounters": "0,1,2,3,4,5,6,7",
"EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
"SampleAfterValue": "2000003", "SampleAfterValue": "50021"
"BriefDescription": "Cycle counts are evenly distributed between active threads in the Core."
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json
View file @ 71fbc431
[ [
{ {
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
"EventCode": "0x08",
"Counter": "0,1,2,3",
"UMask": "0x2",
"PEBScounters": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"SampleAfterValue": "2000003",
"BriefDescription": "Page walks completed due to a demand data load to a 4K page."
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.",
"EventCode": "0x08",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100007",
"BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page." "Speculative": "1",
"UMask": "0x1"
}, },
{ {
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
"EventCode": "0x08",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0xe", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)" "Speculative": "1",
"UMask": "0xe"
}, },
{ {
"BriefDescription": "STLB flush attempts",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
"EventCode": "0x08",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
"SampleAfterValue": "2000003", "SampleAfterValue": "100007",
"BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle." "Speculative": "1",
"UMask": "0x20"
}, },
{ {
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
"EventCode": "0x08",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "CounterMask": "1",
"PEBScounters": "0,1,2,3", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", "Speculative": "1",
"CounterMask": "1" "UMask": "0x10"
}, },
{ {
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
"EventCode": "0x08",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x20", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Loads that miss the DTLB and hit the STLB." "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.",
"EventCode": "0x49",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Page walks completed due to a demand data store to a 4K page." "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.",
"EventCode": "0x49",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page." "Speculative": "1",
"UMask": "0x4"
}, },
{ {
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
"EventCode": "0x49",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0xe", "CounterMask": "1",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)" "Speculative": "1",
"UMask": "0x10"
}, },
{ {
"BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
"EventCode": "0x49",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "2000003", "SampleAfterValue": "100003",
"BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle." "Speculative": "1",
"UMask": "0x4"
}, },
{ {
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
"EventCode": "0x49",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", "Speculative": "1",
"CounterMask": "1" "UMask": "0x20"
}, },
{ {
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
"EventCode": "0x49",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x20", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Stores that miss the DTLB and hit the STLB." "Speculative": "1",
"UMask": "0xe"
}, },
{ {
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
"EventCode": "0x85",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x2", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)" "Speculative": "1",
"UMask": "0xe"
}, },
{ {
"BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts code misses in all ITLB (Instruction TLB) levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
"EventCode": "0x85",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x4", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)" "Speculative": "1",
"UMask": "0x2"
}, },
{ {
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
"EventCode": "0x85",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0xe", "EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)" "Speculative": "1",
"UMask": "0x20"
}, },
{ {
"BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
"EventCode": "0x85",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle." "Speculative": "1",
"UMask": "0x4"
}, },
{ {
"BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
"EventCode": "0x85",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x10", "EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "ITLB_MISSES.WALK_ACTIVE", "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", "Speculative": "1",
"CounterMask": "1" "UMask": "0x10"
}, },
{ {
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
"EventCode": "0x85",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x20", "CounterMask": "1",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "ITLB_MISSES.STLB_HIT", "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB." "Speculative": "1",
"UMask": "0x10"
}, },
{ {
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
"EventCode": "0xAE",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
"SampleAfterValue": "100007", "SampleAfterValue": "100003",
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages." "Speculative": "1",
"UMask": "0x20"
}, },
{ {
"BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
"EventCode": "0xBD",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x1", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100007", "SampleAfterValue": "100003",
"BriefDescription": "DTLB flush attempts of the thread-specific entries" "Speculative": "1",
"UMask": "0x10"
}, },
{ {
"BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
"EventCode": "0xBD",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"UMask": "0x20", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
"SampleAfterValue": "100007", "SampleAfterValue": "100003",
"BriefDescription": "STLB flush attempts" "Speculative": "1",
"UMask": "0x10"
} }
] ]
\ No newline at end of file
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