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Commit 73b4390f authored by Ralf Baechle's avatar Ralf Baechle
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[MIPS] Routerboard 532: Support for base system 

Signed-off-by: default avatarPhil Sutter <n0-1@freewrt.org>
Signed-off-by: default avatarFlorian Fainelli <florian.fainelli@telecomint.eu>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 36a0a3cd
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Showing with 4515 additions and 1 deletion
arch/mips/Kconfig
View file @ 73b4390f
...@@ -558,6 +558,24 @@ config MACH_TX39XX ...@@ -558,6 +558,24 @@ config MACH_TX39XX
config MACH_TX49XX config MACH_TX49XX
bool "Toshiba TX49 series based machines" bool "Toshiba TX49 series based machines"
config MIKROTIK_RB532
bool "Mikrotik RB532 boards"
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select GENERIC_HARDIRQS_NO__DO_IRQ
select HW_HAS_PCI
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SWAP_IO_SPACE
select BOOT_RAW
select GENERIC_GPIO
help
Support the Mikrotik(tm) RouterBoard 532 series,
based on the IDT RC32434 SoC.
config WR_PPMC config WR_PPMC
bool "Wind River PPMC board" bool "Wind River PPMC board"
select CEVT_R4K select CEVT_R4K
...@@ -899,7 +917,7 @@ config BOOT_ELF32 ...@@ -899,7 +917,7 @@ config BOOT_ELF32
config MIPS_L1_CACHE_SHIFT config MIPS_L1_CACHE_SHIFT
int int
default "4" if MACH_DECSTATION default "4" if MACH_DECSTATION || MIKROTIK_RB532
default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
default "4" if PMC_MSP4200_EVAL default "4" if PMC_MSP4200_EVAL
default "5" default "5"
......
arch/mips/Makefile
View file @ 73b4390f
...@@ -559,6 +559,13 @@ load-$(CONFIG_MACH_TX49XX) += 0xffffffff80100000 ...@@ -559,6 +559,13 @@ load-$(CONFIG_MACH_TX49XX) += 0xffffffff80100000
# #
core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/ core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/
#
# Routerboard 532 board
#
core-$(CONFIG_MIKROTIK_RB532) += arch/mips/rb532/
cflags-$(CONFIG_MIKROTIK_RB532) += -Iinclude/asm-mips/mach-rc32434
load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000
# #
# Toshiba RBTX4927 board or # Toshiba RBTX4927 board or
# Toshiba RBTX4937 board # Toshiba RBTX4937 board
......
arch/mips/configs/rb532_defconfig 0 → 100644
View file @ 73b4390f
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25
# Mon Apr 28 12:24:17 2008
#
CONFIG_MIPS=y
#
# Machine selection
#
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_BASLER_EXCITE is not set
# CONFIG_BCM47XX is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_LASAT is not set
# CONFIG_LEMOTE_FULONG is not set
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MARKEINS is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP28 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SWARM is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SNI_RM is not set
# CONFIG_TOSHIBA_JMR3927 is not set
CONFIG_MIKROTIK_RB532=y
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_TOSHIBA_RBTX4938 is not set
# CONFIG_WR_PPMC is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_BOOT_RAW=y
CONFIG_CEVT_R4K=y
CONFIG_CSRC_R4K=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_DMA_NEED_PCI_MAP_STATE=y
# CONFIG_HOTPLUG_CPU is not set
# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_GPIO=y
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
CONFIG_IRQ_CPU=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_MIPS_L1_CACHE_SHIFT=4
#
# CPU selection
#
# CONFIG_CPU_LOONGSON2 is not set
CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPSR1=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
#
# Kernel type
#
CONFIG_32BIT=y
# CONFIG_64BIT is not set
CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_16KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
# CONFIG_HZ_48 is not set
CONFIG_HZ_100=y
# CONFIG_HZ_128 is not set
# CONFIG_HZ_250 is not set
# CONFIG_HZ_256 is not set
# CONFIG_HZ_1000 is not set
# CONFIG_HZ_1024 is not set
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_HZ=100
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
# CONFIG_KEXEC is not set
# CONFIG_SECCOMP is not set
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_GROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
# CONFIG_RT_GROUP_SCHED is not set
CONFIG_USER_SCHED=y
# CONFIG_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_SYSCTL_SYSCALL=y
# CONFIG_KALLSYMS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_HAVE_KPROBES is not set
# CONFIG_HAVE_KRETPROBES is not set
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_KMOD is not set
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
CONFIG_IOSCHED_DEADLINE=y
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_DEFAULT_AS is not set
CONFIG_DEFAULT_DEADLINE=y
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="deadline"
CONFIG_CLASSIC_RCU=y
#
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
CONFIG_HW_HAS_PCI=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_PCI_LEGACY=y
CONFIG_MMU=y
# CONFIG_PCCARD is not set
# CONFIG_HOTPLUG_PCI is not set
#
# Executable file formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_TRAD_SIGNALS=y
#
# Power management options
#
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# CONFIG_PM is not set
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_MMAP=y
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_ASK_IP_FIB_HASH=y
# CONFIG_IP_FIB_TRIE is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
# CONFIG_IP_PNP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_IP_MROUTE is not set
CONFIG_ARPD=y
CONFIG_SYN_COOKIES=y
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=m
CONFIG_INET_TCP_DIAG=m
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=m
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=y
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
# CONFIG_DEFAULT_BIC is not set
# CONFIG_DEFAULT_CUBIC is not set
# CONFIG_DEFAULT_HTCP is not set
CONFIG_DEFAULT_VEGAS=y
# CONFIG_DEFAULT_WESTWOOD is not set
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="vegas"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IP_VS is not set
# CONFIG_IPV6 is not set
# CONFIG_NETWORK_SECMARK is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
CONFIG_NETFILTER_ADVANCED=y
# CONFIG_BRIDGE_NETFILTER is not set
#
# Core Netfilter Configuration
#
# CONFIG_NETFILTER_NETLINK_QUEUE is not set
# CONFIG_NETFILTER_NETLINK_LOG is not set
CONFIG_NF_CONNTRACK=y
CONFIG_NF_CT_ACCT=y
CONFIG_NF_CONNTRACK_MARK=y
# CONFIG_NF_CONNTRACK_EVENTS is not set
# CONFIG_NF_CT_PROTO_DCCP is not set
# CONFIG_NF_CT_PROTO_SCTP is not set
# CONFIG_NF_CT_PROTO_UDPLITE is not set
# CONFIG_NF_CONNTRACK_AMANDA is not set
CONFIG_NF_CONNTRACK_FTP=m
# CONFIG_NF_CONNTRACK_H323 is not set
CONFIG_NF_CONNTRACK_IRC=m
# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
# CONFIG_NF_CONNTRACK_PPTP is not set
# CONFIG_NF_CONNTRACK_SANE is not set
# CONFIG_NF_CONNTRACK_SIP is not set
CONFIG_NF_CONNTRACK_TFTP=m
# CONFIG_NF_CT_NETLINK is not set
CONFIG_NETFILTER_XTABLES=y
# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
# CONFIG_NETFILTER_XT_TARGET_MARK is not set
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
CONFIG_NETFILTER_XT_TARGET_TRACE=m
# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
CONFIG_NETFILTER_XT_MATCH_DCCP=m
# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
# CONFIG_NETFILTER_XT_MATCH_ESP is not set
# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
# CONFIG_NETFILTER_XT_MATCH_MAC is not set
# CONFIG_NETFILTER_XT_MATCH_MARK is not set
# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_STATE=y
# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
# CONFIG_NETFILTER_XT_MATCH_STRING is not set
# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
# CONFIG_NETFILTER_XT_MATCH_TIME is not set
CONFIG_NETFILTER_XT_MATCH_U32=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
#
# IP: Netfilter Configuration
#
CONFIG_NF_CONNTRACK_IPV4=y
CONFIG_NF_CONNTRACK_PROC_COMPAT=y
# CONFIG_IP_NF_QUEUE is not set
CONFIG_IP_NF_IPTABLES=y
# CONFIG_IP_NF_MATCH_RECENT is not set
# CONFIG_IP_NF_MATCH_ECN is not set
# CONFIG_IP_NF_MATCH_AH is not set
# CONFIG_IP_NF_MATCH_TTL is not set
CONFIG_IP_NF_MATCH_ADDRTYPE=m
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
# CONFIG_IP_NF_TARGET_LOG is not set
# CONFIG_IP_NF_TARGET_ULOG is not set
CONFIG_NF_NAT=y
CONFIG_NF_NAT_NEEDED=y
CONFIG_IP_NF_TARGET_MASQUERADE=y
# CONFIG_IP_NF_TARGET_REDIRECT is not set
# CONFIG_IP_NF_TARGET_NETMAP is not set
# CONFIG_NF_NAT_SNMP_BASIC is not set
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_TFTP=m
# CONFIG_NF_NAT_AMANDA is not set
# CONFIG_NF_NAT_PPTP is not set
# CONFIG_NF_NAT_H323 is not set
# CONFIG_NF_NAT_SIP is not set
CONFIG_IP_NF_MANGLE=y
# CONFIG_IP_NF_TARGET_ECN is not set
# CONFIG_IP_NF_TARGET_TTL is not set
# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
CONFIG_IP_NF_RAW=m
# CONFIG_IP_NF_ARPTABLES is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
CONFIG_BRIDGE=y
CONFIG_VLAN_8021Q=y
# CONFIG_DECNET is not set
CONFIG_LLC=y
CONFIG_LLC2=m
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
CONFIG_NET_SCHED=y
#
# Queueing/Scheduling
#
CONFIG_NET_SCH_CBQ=m
# CONFIG_NET_SCH_HTB is not set
# CONFIG_NET_SCH_HFSC is not set
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_RR=m
# CONFIG_NET_SCH_RED is not set
# CONFIG_NET_SCH_SFQ is not set
# CONFIG_NET_SCH_TEQL is not set
# CONFIG_NET_SCH_TBF is not set
# CONFIG_NET_SCH_GRED is not set
# CONFIG_NET_SCH_DSMARK is not set
CONFIG_NET_SCH_NETEM=m
# CONFIG_NET_SCH_INGRESS is not set
#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_ROUTE=y
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_PERF=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_RSVP=m
CONFIG_NET_CLS_RSVP6=m
# CONFIG_NET_CLS_FLOW is not set
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
CONFIG_NET_EMATCH_CMP=m
CONFIG_NET_EMATCH_NBYTE=m
CONFIG_NET_EMATCH_U32=m
CONFIG_NET_EMATCH_META=m
CONFIG_NET_EMATCH_TEXT=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_POLICE=y
CONFIG_NET_ACT_GACT=m
CONFIG_GACT_PROB=y
CONFIG_NET_ACT_MIRRED=m
CONFIG_NET_ACT_IPT=m
# CONFIG_NET_ACT_NAT is not set
CONFIG_NET_ACT_PEDIT=m
# CONFIG_NET_ACT_SIMP is not set
CONFIG_NET_CLS_IND=y
CONFIG_NET_SCH_FIFO=y
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
CONFIG_HAMRADIO=y
#
# Packet Radio protocols
#
# CONFIG_AX25 is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
CONFIG_FIB_RULES=y
#
# Wireless
#
# CONFIG_CFG80211 is not set
CONFIG_WIRELESS_EXT=y
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
# CONFIG_MTD_AR7_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_INTEL_VR_NOR is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_PMC551 is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
CONFIG_MTD_BLOCK2MTD=y
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_VERIFY_WRITE=y
# CONFIG_MTD_NAND_ECC_SMC is not set
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_NAND_CAFE is not set
# CONFIG_MTD_NAND_NANDSIM is not set
CONFIG_MTD_NAND_PLATFORM=y
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_MISC_DEVICES=y
# CONFIG_PHANTOM is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
# CONFIG_ENCLOSURE_SERVICES is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
#
# CONFIG_BLK_DEV_SD is not set
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
# CONFIG_CHR_DEV_SCH is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_FC is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_LPFC is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_NSP32 is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_SRP is not set
CONFIG_ATA=y
# CONFIG_ATA_NONSTANDARD is not set
# CONFIG_SATA_PMP is not set
# CONFIG_SATA_AHCI is not set
# CONFIG_SATA_SIL24 is not set
CONFIG_ATA_SFF=y
# CONFIG_SATA_SVW is not set
# CONFIG_ATA_PIIX is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_NV is not set
# CONFIG_PDC_ADMA is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_PROMISE is not set
# CONFIG_SATA_SX4 is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_ULI is not set
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set
# CONFIG_SATA_INIC162X is not set
# CONFIG_PATA_ALI is not set
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CS5520 is not set
# CONFIG_PATA_CS5530 is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_ATA_GENERIC is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_OPTIDMA is not set
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
CONFIG_PATA_RB532=y
# CONFIG_PATA_RZ1000 is not set
# CONFIG_PATA_SC1200 is not set
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_SIL680 is not set
# CONFIG_PATA_SIS is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set
# CONFIG_PATA_PLATFORM is not set
# CONFIG_MD is not set
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_IEEE1394 is not set
# CONFIG_I2O is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
CONFIG_IFB=m
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_ARCNET is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_AX88796 is not set
CONFIG_KORINA=y
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_CASSINI is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_DM9000 is not set
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
CONFIG_NET_PCI=y
# CONFIG_PCNET32 is not set
# CONFIG_AMD8111_ETH is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_B44 is not set
# CONFIG_FORCEDETH is not set
# CONFIG_TC35815 is not set
# CONFIG_EEPRO100 is not set
# CONFIG_E100 is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
# CONFIG_R6040 is not set
# CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set
# CONFIG_TLAN is not set
CONFIG_VIA_RHINE=y
# CONFIG_VIA_RHINE_MMIO is not set
CONFIG_VIA_RHINE_NAPI=y
# CONFIG_SC92031 is not set
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_TR is not set
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
CONFIG_WLAN_80211=y
# CONFIG_IPW2100 is not set
# CONFIG_IPW2200 is not set
# CONFIG_LIBERTAS is not set
# CONFIG_HERMES is not set
CONFIG_ATMEL=m
# CONFIG_PCI_ATMEL is not set
# CONFIG_PRISM54 is not set
# CONFIG_IWLWIFI_LEDS is not set
# CONFIG_HOSTAP is not set
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
CONFIG_PPP=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_ASYNC=m
# CONFIG_PPP_SYNC_TTY is not set
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_BSDCOMP=m
# CONFIG_PPP_MPPE is not set
CONFIG_PPPOE=m
CONFIG_PPPOL2TP=m
# CONFIG_SLIP is not set
CONFIG_SLHC=m
# CONFIG_NET_FC is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_GPIO is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_NOZOMI is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_NR_UARTS=2
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=y
# CONFIG_RTC is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_DEVPORT=y
# CONFIG_I2C is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set
#
# Multimedia devices
#
CONFIG_VIDEO_DEV=m
CONFIG_VIDEO_V4L2_COMMON=m
CONFIG_VIDEO_ALLOW_V4L1=y
CONFIG_VIDEO_V4L1_COMPAT=y
CONFIG_VIDEO_V4L2=m
CONFIG_VIDEO_V4L1=m
CONFIG_VIDEO_CAPTURE_DRIVERS=y
# CONFIG_VIDEO_ADV_DEBUG is not set
# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
#
# Encoders/decoders and other helper chips
#
#
# Audio decoders
#
#
# Video decoders
#
#
# Video and audio decoders
#
#
# MPEG video encoders
#
# CONFIG_VIDEO_CX2341X is not set
#
# Video encoders
#
#
# Video improvement chips
#
# CONFIG_VIDEO_VIVI is not set
# CONFIG_VIDEO_CPIA is not set
# CONFIG_VIDEO_STRADIS is not set
# CONFIG_SOC_CAMERA is not set
# CONFIG_RADIO_ADAPTERS is not set
# CONFIG_DVB_CORE is not set
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_DRM is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Sound
#
# CONFIG_SOUND is not set
CONFIG_HID_SUPPORT=y
# CONFIG_HID is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y
# CONFIG_USB is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
#
# LED drivers
#
# CONFIG_LEDS_GPIO is not set
#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
# CONFIG_INFINIBAND is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
# CONFIG_UIO is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_CONFIGFS_FS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
CONFIG_JFFS2_SUMMARY=y
# CONFIG_JFFS2_FS_XATTR is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
# CONFIG_NFS_FS is not set
# CONFIG_NFSD is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
CONFIG_MAC_PARTITION=y
CONFIG_MSDOS_PARTITION=y
CONFIG_BSD_DISKLABEL=y
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
# CONFIG_SYSV68_PARTITION is not set
# CONFIG_NLS is not set
# CONFIG_DLM is not set
#
# Kernel hacking
#
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=1024
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SAMPLES is not set
CONFIG_CMDLINE=""
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_CRYPTO=y
#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=m
CONFIG_CRYPTO_AEAD=m
CONFIG_CRYPTO_BLKCIPHER=m
# CONFIG_CRYPTO_MANAGER is not set
# CONFIG_CRYPTO_GF128MUL is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_AUTHENC is not set
CONFIG_CRYPTO_TEST=m
#
# Authenticated Encryption with Associated Data
#
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_SEQIV is not set
#
# Block modes
#
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_XTS is not set
#
# Hash modes
#
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
#
# Digest
#
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_WP512 is not set
#
# Ciphers
#
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_TWOFISH is not set
#
# Compression
#
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_LZO is not set
# CONFIG_CRYPTO_HW is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_GENERIC_FIND_FIRST_BIT is not set
CONFIG_CRC_CCITT=m
CONFIG_CRC16=m
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
CONFIG_LIBCRC32C=m
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
arch/mips/pci/Makefile
View file @ 73b4390f
...@@ -49,3 +49,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o ...@@ -49,3 +49,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
arch/mips/pci/fixup-rc32434.c 0 → 100644
View file @ 73b4390f
/*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* stevel@mvista.com or source@mvista.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/mach-rc32434/rc32434.h>
static int __devinitdata irq_map[2][12] = {
{0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1},
{0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3}
};
int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq = 0;
if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12)
irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
return irq + GROUP4_IRQ_BASE + 4;
}
static void rc32434_pci_early_fixup(struct pci_dev *dev)
{
if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
/* disable prefetched memory range */
pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
}
}
/*
* The fixup applies to both the IDT and VIA devices present on the board
*/
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, rc32434_pci_early_fixup);
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
arch/mips/pci/ops-rc32434.c 0 → 100644
View file @ 73b4390f
/*
* BRIEF MODULE DESCRIPTION
* pci_ops for IDT EB434 board
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
* Copyright 2006 Felix Fietkau <nbd@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/pci.h>
#include <linux/types.h>
#include <asm/cpu.h>
#include <asm/mach-rc32434/rc32434.h>
#include <asm/mach-rc32434/pci.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
#define PCI_CFG_SET(bus, slot, func, off) \
(rc32434_pci->pcicfga = (0x80000000 | \
((bus) << 16) | ((slot)<<11) | \
((func)<<8) | (off)))
static inline int config_access(unsigned char access_type,
struct pci_bus *bus, unsigned int devfn,
unsigned char where, u32 *data)
{
unsigned int slot = PCI_SLOT(devfn);
u8 func = PCI_FUNC(devfn);
/* Setup address */
PCI_CFG_SET(bus->number, slot, func, where);
rc32434_sync();
if (access_type == PCI_ACCESS_WRITE)
rc32434_pci->pcicfgd = *data;
else
*data = rc32434_pci->pcicfgd;
rc32434_sync();
return 0;
}
/*
* We can't address 8 and 16 bit words directly. Instead we have to
* read/write a 32bit word and mask/modify the data we actually want.
*/
static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
int where, u8 *val)
{
u32 data;
int ret;
ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
*val = (data >> ((where & 3) << 3)) & 0xff;
return ret;
}
static int read_config_word(struct pci_bus *bus, unsigned int devfn,
int where, u16 *val)
{
u32 data;
int ret;
ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
*val = (data >> ((where & 3) << 3)) & 0xffff;
return ret;
}
static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
int where, u32 *val)
{
int ret;
int delay = 1;
/*
* Don't scan too far, else there will be errors with plugged in
* daughterboard (rb564).
*/
if (bus->number == 0 && PCI_SLOT(devfn) > 21)
return 0;
retry:
ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
/*
* Certain devices react delayed at device scan time, this
* gives them time to settle
*/
if (where == PCI_VENDOR_ID) {
if (ret == 0xffffffff || ret == 0x00000000 ||
ret == 0x0000ffff || ret == 0xffff0000) {
if (delay > 4)
return 0;
delay *= 2;
msleep(delay);
goto retry;
}
}
return ret;
}
static int
write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
u8 val)
{
u32 data = 0;
if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
return -1;
data = (data & ~(0xff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
return -1;
return PCIBIOS_SUCCESSFUL;
}
static int
write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
u16 val)
{
u32 data = 0;
if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
return -1;
data = (data & ~(0xffff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
return -1;
return PCIBIOS_SUCCESSFUL;
}
static int
write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
u32 val)
{
if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
return -1;
return PCIBIOS_SUCCESSFUL;
}
static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
switch (size) {
case 1:
return read_config_byte(bus, devfn, where, (u8 *) val);
case 2:
return read_config_word(bus, devfn, where, (u16 *) val);
default:
return read_config_dword(bus, devfn, where, val);
}
}
static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
switch (size) {
case 1:
return write_config_byte(bus, devfn, where, (u8) val);
case 2:
return write_config_word(bus, devfn, where, (u16) val);
default:
return write_config_dword(bus, devfn, where, val);
}
}
struct pci_ops rc32434_pci_ops = {
.read = pci_config_read,
.write = pci_config_write,
};
arch/mips/pci/pci-rc32434.c 0 → 100644
View file @ 73b4390f
/*
* BRIEF MODULE DESCRIPTION
* PCI initialization for IDT EB434 board
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/mach-rc32434/rc32434.h>
#include <asm/mach-rc32434/pci.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
/* define an unsigned array for the PCI registers */
static unsigned int korina_cnfg_regs[25] = {
KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
};
static struct resource rc32434_res_pci_mem1;
static struct resource rc32434_res_pci_mem2;
static struct resource rc32434_res_pci_mem1 = {
.name = "PCI MEM1",
.start = 0x50000000,
.end = 0x5FFFFFFF,
.flags = IORESOURCE_MEM,
.parent = &rc32434_res_pci_mem1,
.sibling = NULL,
.child = &rc32434_res_pci_mem2
};
static struct resource rc32434_res_pci_mem2 = {
.name = "PCI Mem2",
.start = 0x60000000,
.end = 0x6FFFFFFF,
.flags = IORESOURCE_MEM,
.parent = &rc32434_res_pci_mem1,
.sibling = NULL,
.child = NULL
};
static struct resource rc32434_res_pci_io1 = {
.name = "PCI I/O1",
.start = 0x18800000,
.end = 0x188FFFFF,
.flags = IORESOURCE_IO,
};
extern struct pci_ops rc32434_pci_ops;
#define PCI_MEM1_START PCI_ADDR_START
#define PCI_MEM1_END (PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1)
#define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN)
#define PCI_MEM2_END (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) - 1)
#define PCI_IO1_START (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN))
#define PCI_IO1_END \
(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1)
#define PCI_IO2_START \
(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN)
#define PCI_IO2_END \
(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1)
struct pci_controller rc32434_controller2;
struct pci_controller rc32434_controller = {
.pci_ops = &rc32434_pci_ops,
.mem_resource = &rc32434_res_pci_mem1,
.io_resource = &rc32434_res_pci_io1,
.mem_offset = 0,
.io_offset = 0,
};
#ifdef __MIPSEB__
#define PCI_ENDIAN_FLAG PCILBAC_sb_m
#else
#define PCI_ENDIAN_FLAG 0
#endif
static int __init rc32434_pcibridge_init(void)
{
unsigned int pcicvalue, pcicdata = 0;
unsigned int dummyread, pcicntlval;
int loopCount;
unsigned int pci_config_addr;
pcicvalue = rc32434_pci->pcic;
pcicvalue = (pcicvalue >> PCIM_SHFT) & PCIM_BIT_LEN;
if (!((pcicvalue == PCIM_H_EA) ||
(pcicvalue == PCIM_H_IA_FIX) ||
(pcicvalue == PCIM_H_IA_RR))) {
pr_err(KERN_ERR "PCI init error!!!\n");
/* Not in Host Mode, return ERROR */
return -1;
}
/* Enables the Idle Grant mode, Arbiter Parking */
pcicdata |= (PCI_CTL_IGM | PCI_CTL_EAP | PCI_CTL_EN);
rc32434_pci->pcic = pcicdata; /* Enable the PCI bus Interface */
/* Zero out the PCI status & PCI Status Mask */
for (;;) {
pcicdata = rc32434_pci->pcis;
if (!(pcicdata & PCI_STAT_RIP))
break;
}
rc32434_pci->pcis = 0;
rc32434_pci->pcism = 0xFFFFFFFF;
/* Zero out the PCI decoupled registers */
rc32434_pci->pcidac = 0; /*
* disable PCI decoupled accesses at
* initialization
*/
rc32434_pci->pcidas = 0; /* clear the status */
rc32434_pci->pcidasm = 0x0000007F; /* Mask all the interrupts */
/* Mask PCI Messaging Interrupts */
rc32434_pci_msg->pciiic = 0;
rc32434_pci_msg->pciiim = 0xFFFFFFFF;
rc32434_pci_msg->pciioic = 0;
rc32434_pci_msg->pciioim = 0;
/* Setup PCILB0 as Memory Window */
rc32434_pci->pcilba[0].address = (unsigned int) (PCI_ADDR_START);
/* setup the PCI map address as same as the local address */
rc32434_pci->pcilba[0].mapping = (unsigned int) (PCI_ADDR_START);
/* Setup PCILBA1 as MEM */
rc32434_pci->pcilba[0].control =
(((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */
rc32434_pci->pcilba[1].address = 0x60000000;
rc32434_pci->pcilba[1].mapping = 0x60000000;
/* setup PCILBA2 as IO Window */
rc32434_pci->pcilba[1].control =
(((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */
rc32434_pci->pcilba[2].address = 0x18C00000;
rc32434_pci->pcilba[2].mapping = 0x18FFFFFF;
/* setup PCILBA2 as IO Window */
rc32434_pci->pcilba[2].control =
(((SIZE_4MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */
/* Setup PCILBA3 as IO Window */
rc32434_pci->pcilba[3].address = 0x18800000;
rc32434_pci->pcilba[3].mapping = 0x18800000;
rc32434_pci->pcilba[3].control =
((((SIZE_1MB & 0x1ff) << PCI_LBAC_SIZE_BIT) | PCI_LBAC_MSI) |
PCI_ENDIAN_FLAG);
dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */
pci_config_addr = (unsigned int) (0x80000004);
for (loopCount = 0; loopCount < 24; loopCount++) {
rc32434_pci->pcicfga = pci_config_addr;
dummyread = rc32434_pci->pcicfga;
rc32434_pci->pcicfgd = korina_cnfg_regs[loopCount];
dummyread = rc32434_pci->pcicfgd;
pci_config_addr += 4;
}
rc32434_pci->pcitc =
(unsigned int) ((PCITC_RTIMER_VAL & 0xff) << PCI_TC_RTIMER_BIT) |
((PCITC_DTIMER_VAL & 0xff) << PCI_TC_DTIMER_BIT);
pcicntlval = rc32434_pci->pcic;
pcicntlval &= ~PCI_CTL_TNR;
rc32434_pci->pcic = pcicntlval;
pcicntlval = rc32434_pci->pcic;
return 0;
}
static int __init rc32434_pci_init(void)
{
pr_info("PCI: Initializing PCI\n");
ioport_resource.start = rc32434_res_pci_io1.start;
ioport_resource.end = rc32434_res_pci_io1.end;
rc32434_pcibridge_init();
register_pci_controller(&rc32434_controller);
rc32434_sync();
return 0;
}
arch_initcall(rc32434_pci_init);
arch/mips/rb532/Makefile 0 → 100644
View file @ 73b4390f
#
# Makefile for the RB532 board specific parts of the kernel
#
obj-y += irq.o time.o setup.o serial.o prom.o gpio.o devices.o
EXTRA_CFLAGS += -Werror
arch/mips/rb532/devices.c 0 → 100644
View file @ 73b4390f
/*
* RouterBoard 500 Platform devices
*
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
* Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <asm/bootinfo.h>
#include <asm/mach-rc32434/rc32434.h>
#include <asm/mach-rc32434/dma.h>
#include <asm/mach-rc32434/dma_v.h>
#include <asm/mach-rc32434/eth.h>
#include <asm/mach-rc32434/rb.h>
#include <asm/mach-rc32434/integ.h>
#include <asm/mach-rc32434/gpio.h>
#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0)
#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1)
#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
/* NAND definitions */
#define GPIO_RDY (1 << 0x08)
#define GPIO_WPX (1 << 0x09)
#define GPIO_ALE (1 << 0x0a)
#define GPIO_CLE (1 << 0x0b)
extern char *board_type;
static struct resource korina_dev0_res[] = {
{
.name = "korina_regs",
.start = ETH0_BASE_ADDR,
.end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
.flags = IORESOURCE_MEM,
}, {
.name = "korina_rx",
.start = ETH0_DMA_RX_IRQ,
.end = ETH0_DMA_RX_IRQ,
.flags = IORESOURCE_IRQ
}, {
.name = "korina_tx",
.start = ETH0_DMA_TX_IRQ,
.end = ETH0_DMA_TX_IRQ,
.flags = IORESOURCE_IRQ
}, {
.name = "korina_ovr",
.start = ETH0_RX_OVR_IRQ,
.end = ETH0_RX_OVR_IRQ,
.flags = IORESOURCE_IRQ
}, {
.name = "korina_und",
.start = ETH0_TX_UND_IRQ,
.end = ETH0_TX_UND_IRQ,
.flags = IORESOURCE_IRQ
}, {
.name = "korina_dma_rx",
.start = ETH0_RX_DMA_ADDR,
.end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "korina_dma_tx",
.start = ETH0_TX_DMA_ADDR,
.end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
.flags = IORESOURCE_MEM,
}
};
static struct korina_device korina_dev0_data = {
.name = "korina0",
.mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
};
static struct platform_device korina_dev0 = {
.id = 0,
.name = "korina",
.dev.platform_data = &korina_dev0_data,
.resource = korina_dev0_res,
.num_resources = ARRAY_SIZE(korina_dev0_res),
};
#define CF_GPIO_NUM 13
static struct resource cf_slot0_res[] = {
{
.name = "cf_membase",
.flags = IORESOURCE_MEM
}, {
.name = "cf_irq",
.start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
.end = (8 + 4 * 32 + CF_GPIO_NUM),
.flags = IORESOURCE_IRQ
}
};
static struct cf_device cf_slot0_data = {
.gpio_pin = 13
};
static struct platform_device cf_slot0 = {
.id = 0,
.name = "pata-rb532-cf",
.dev.platform_data = &cf_slot0_data,
.resource = cf_slot0_res,
.num_resources = ARRAY_SIZE(cf_slot0_res),
};
/* Resources and device for NAND */
static int rb532_dev_ready(struct mtd_info *mtd)
{
return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
}
static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd->priv;
unsigned char orbits, nandbits;
if (ctrl & NAND_CTRL_CHANGE) {
orbits = (ctrl & NAND_CLE) << 1;
orbits |= (ctrl & NAND_ALE) >> 1;
nandbits = (~ctrl & NAND_CLE) << 1;
nandbits |= (~ctrl & NAND_ALE) >> 1;
set_latch_u5(orbits, nandbits);
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, chip->IO_ADDR_W);
}
static struct resource nand_slot0_res[] = {
[0] = {
.name = "nand_membase",
.flags = IORESOURCE_MEM
}
};
static struct platform_nand_data rb532_nand_data = {
.ctrl.dev_ready = rb532_dev_ready,
.ctrl.cmd_ctrl = rb532_cmd_ctrl,
};
static struct platform_device nand_slot0 = {
.name = "gen_nand",
.id = -1,
.resource = nand_slot0_res,
.num_resources = ARRAY_SIZE(nand_slot0_res),
.dev.platform_data = &rb532_nand_data,
};
static struct mtd_partition rb532_partition_info[] = {
{
.name = "Routerboard NAND boot",
.offset = 0,
.size = 4 * 1024 * 1024,
}, {
.name = "rootfs",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL,
}
};
static struct platform_device rb532_led = {
.name = "rb532-led",
.id = 0,
};
static struct gpio_keys_button rb532_gpio_btn[] = {
{
.gpio = 1,
.code = BTN_0,
.desc = "S1",
.active_low = 1,
}
};
static struct gpio_keys_platform_data rb532_gpio_btn_data = {
.buttons = rb532_gpio_btn,
.nbuttons = ARRAY_SIZE(rb532_gpio_btn),
};
static struct platform_device rb532_button = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &rb532_gpio_btn_data,
}
};
static struct resource rb532_wdt_res[] = {
{
.name = "rb532_wdt_res",
.start = INTEG0_BASE_ADDR,
.end = INTEG0_BASE_ADDR + sizeof(struct integ),
.flags = IORESOURCE_MEM,
}
};
static struct platform_device rb532_wdt = {
.name = "rc32434_wdt",
.id = -1,
.resource = rb532_wdt_res,
.num_resources = ARRAY_SIZE(rb532_wdt_res),
};
static struct platform_device *rb532_devs[] = {
&korina_dev0,
&nand_slot0,
&cf_slot0,
&rb532_led,
&rb532_button,
&rb532_wdt
};
static void __init parse_mac_addr(char *macstr)
{
int i, j;
unsigned char result, value;
for (i = 0; i < 6; i++) {
result = 0;
if (i != 5 && *(macstr + 2) != ':')
return;
for (j = 0; j < 2; j++) {
if (isxdigit(*macstr)
&& (value =
isdigit(*macstr) ? *macstr -
'0' : toupper(*macstr) - 'A' + 10) < 16) {
result = result * 16 + value;
macstr++;
} else
return;
}
macstr++;
korina_dev0_data.mac[i] = result;
}
}
/* DEVICE CONTROLLER 1 */
#define CFG_DC_DEV1 ((void *)0xb8010010)
#define CFG_DC_DEV2 ((void *)0xb8010020)
#define CFG_DC_DEVBASE 0x0
#define CFG_DC_DEVMASK 0x4
#define CFG_DC_DEVC 0x8
#define CFG_DC_DEVTC 0xC
/* NAND definitions */
#define NAND_CHIP_DELAY 25
static void __init rb532_nand_setup(void)
{
switch (mips_machtype) {
case MACH_MIKROTIK_RB532A:
set_latch_u5(LO_FOFF | LO_CEX,
LO_ULED | LO_ALE | LO_CLE | LO_WPX);
break;
default:
set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
LO_ULED | LO_ALE | LO_CLE);
break;
}
/* Setup NAND specific settings */
rb532_nand_data.chip.nr_chips = 1;
rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
rb532_nand_data.chip.partitions = rb532_partition_info;
rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
rb532_nand_data.chip.options = NAND_NO_AUTOINCR;
}
static int __init plat_setup_devices(void)
{
/* Look for the CF card reader */
if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
rb532_devs[1] = NULL;
else {
cf_slot0_res[0].start =
readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
}
/* Read the NAND resources from the device controller */
nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE);
nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
/* Initialise the NAND device */
rb532_nand_setup();
return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
}
static int __init setup_kmac(char *s)
{
printk(KERN_INFO "korina mac = %s\n", s);
parse_mac_addr(s);
return 0;
}
__setup("kmac=", setup_kmac);
arch_initcall(plat_setup_devices);
arch/mips/rb532/gpio.c 0 → 100644
View file @ 73b4390f
/*
* Miscellaneous functions for IDT EB434 board
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
* Copyright 2006 Phil Sutter <n0-1@freewrt.org>
* Copyright 2007 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <asm/addrspace.h>
#include <asm/mach-rc32434/rb.h>
struct rb532_gpio_reg __iomem *rb532_gpio_reg0;
EXPORT_SYMBOL(rb532_gpio_reg0);
struct mpmc_device dev3;
static struct resource rb532_gpio_reg0_res[] = {
{
.name = "gpio_reg0",
.start = (u32)(IDT434_REG_BASE + GPIOBASE),
.end = (u32)(IDT434_REG_BASE + GPIOBASE + sizeof(struct rb532_gpio_reg)),
.flags = IORESOURCE_MEM,
}
};
static struct resource rb532_dev3_ctl_res[] = {
{
.name = "dev3_ctl",
.start = (u32)(IDT434_REG_BASE + DEV3BASE),
.end = (u32)(IDT434_REG_BASE + DEV3BASE + sizeof(struct dev_reg)),
.flags = IORESOURCE_MEM,
}
};
void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
{
unsigned flags, data;
unsigned i = 0;
spin_lock_irqsave(&dev3.lock, flags);
data = *(volatile unsigned *) (IDT434_REG_BASE + reg_offs);
for (i = 0; i != len; ++i) {
if (val & (1 << i))
data |= (1 << (i + bit));
else
data &= ~(1 << (i + bit));
}
writel(data, (IDT434_REG_BASE + reg_offs));
spin_unlock_irqrestore(&dev3.lock, flags);
}
EXPORT_SYMBOL(set_434_reg);
unsigned get_434_reg(unsigned reg_offs)
{
return readl(IDT434_REG_BASE + reg_offs);
}
EXPORT_SYMBOL(get_434_reg);
void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
{
unsigned flags;
spin_lock_irqsave(&dev3.lock, flags);
dev3.state = (dev3.state | or_mask) & ~nand_mask;
writel(dev3.state, &dev3.base);
spin_unlock_irqrestore(&dev3.lock, flags);
}
EXPORT_SYMBOL(set_latch_u5);
unsigned char get_latch_u5(void)
{
return dev3.state;
}
EXPORT_SYMBOL(get_latch_u5);
int rb532_gpio_get_value(unsigned gpio)
{
return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio);
}
EXPORT_SYMBOL(rb532_gpio_get_value);
void rb532_gpio_set_value(unsigned gpio, int value)
{
unsigned tmp;
tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio);
if (value)
tmp |= 1 << gpio;
writel(tmp, (void *)&rb532_gpio_reg0->gpiod);
}
EXPORT_SYMBOL(rb532_gpio_set_value);
int rb532_gpio_direction_input(unsigned gpio)
{
writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio),
(void *)&rb532_gpio_reg0->gpiocfg);
return 0;
}
EXPORT_SYMBOL(rb532_gpio_direction_input);
int rb532_gpio_direction_output(unsigned gpio, int value)
{
gpio_set_value(gpio, value);
writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio),
(void *)&rb532_gpio_reg0->gpiocfg);
return 0;
}
EXPORT_SYMBOL(rb532_gpio_direction_output);
void rb532_gpio_set_int_level(unsigned gpio, int value)
{
unsigned tmp;
tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio);
if (value)
tmp |= 1 << gpio;
writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel);
}
EXPORT_SYMBOL(rb532_gpio_set_int_level);
int rb532_gpio_get_int_level(unsigned gpio)
{
return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio);
}
EXPORT_SYMBOL(rb532_gpio_get_int_level);
void rb532_gpio_set_int_status(unsigned gpio, int value)
{
unsigned tmp;
tmp = readl(&rb532_gpio_reg0->gpioistat);
if (value)
tmp |= 1 << gpio;
writel(tmp, (void *)&rb532_gpio_reg0->gpioistat);
}
EXPORT_SYMBOL(rb532_gpio_set_int_status);
int rb532_gpio_get_int_status(unsigned gpio)
{
return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio);
}
EXPORT_SYMBOL(rb532_gpio_get_int_status);
void rb532_gpio_set_func(unsigned gpio, int value)
{
unsigned tmp;
tmp = readl(&rb532_gpio_reg0->gpiofunc);
if (value)
tmp |= 1 << gpio;
writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc);
}
EXPORT_SYMBOL(rb532_gpio_set_func);
int rb532_gpio_get_func(unsigned gpio)
{
return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio);
}
EXPORT_SYMBOL(rb532_gpio_get_func);
int __init rb532_gpio_init(void)
{
rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start,
rb532_gpio_reg0_res[0].end -
rb532_gpio_reg0_res[0].start);
if (!rb532_gpio_reg0) {
printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
return -ENXIO;
}
dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start,
rb532_dev3_ctl_res[0].end -
rb532_dev3_ctl_res[0].start);
if (!dev3.base) {
printk(KERN_ERR "rb532: cannot remap device controller 3\n");
return -ENXIO;
}
return 0;
}
arch_initcall(rb532_gpio_init);
arch/mips/rb532/irq.c 0 → 100644
View file @ 73b4390f
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Copyright 2002 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* stevel@mvista.com or source@mvista.com
*/
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/delay.h>
#include <asm/bootinfo.h>
#include <asm/time.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/mach-rc32434/rc32434.h>
struct intr_group {
u32 mask; /* mask of valid bits in pending/mask registers */
volatile u32 *base_addr;
};
#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
#if (NR_IRQS < RC32434_NR_IRQS)
#error Too little irqs defined. Did you override <asm/irq.h> ?
#endif
static const struct intr_group intr_group[NUM_INTR_GROUPS] = {
{
.mask = 0x0000efff,
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
{
.mask = 0x00001fff,
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
{
.mask = 0x00000007,
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
{
.mask = 0x0003ffff,
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
{
.mask = 0xffffffff,
.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
};
#define READ_PEND(base) (*(base))
#define READ_MASK(base) (*(base + 2))
#define WRITE_MASK(base, val) (*(base + 2) = (val))
static inline int irq_to_group(unsigned int irq_nr)
{
return (irq_nr - GROUP0_IRQ_BASE) >> 5;
}
static inline int group_to_ip(unsigned int group)
{
return group + 2;
}
static inline void enable_local_irq(unsigned int ip)
{
int ipnum = 0x100 << ip;
set_c0_status(ipnum);
}
static inline void disable_local_irq(unsigned int ip)
{
int ipnum = 0x100 << ip;
clear_c0_status(ipnum);
}
static inline void ack_local_irq(unsigned int ip)
{
int ipnum = 0x100 << ip;
clear_c0_cause(ipnum);
}
static void rb532_enable_irq(unsigned int irq_nr)
{
int ip = irq_nr - GROUP0_IRQ_BASE;
unsigned int group, intr_bit;
volatile unsigned int *addr;
if (ip < 0)
enable_local_irq(irq_nr);
else {
group = ip >> 5;
ip &= (1 << 5) - 1;
intr_bit = 1 << ip;
enable_local_irq(group_to_ip(group));
addr = intr_group[group].base_addr;
WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
}
}
static void rb532_disable_irq(unsigned int irq_nr)
{
int ip = irq_nr - GROUP0_IRQ_BASE;
unsigned int group, intr_bit, mask;
volatile unsigned int *addr;
if (ip < 0) {
disable_local_irq(irq_nr);
} else {
group = ip >> 5;
ip &= (1 << 5) - 1;
intr_bit = 1 << ip;
addr = intr_group[group].base_addr;
mask = READ_MASK(addr);
mask |= intr_bit;
WRITE_MASK(addr, mask);
/*
* if there are no more interrupts enabled in this
* group, disable corresponding IP
*/
if (mask == intr_group[group].mask)
disable_local_irq(group_to_ip(group));
}
}
static void rb532_mask_and_ack_irq(unsigned int irq_nr)
{
rb532_disable_irq(irq_nr);
ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
}
static struct irq_chip rc32434_irq_type = {
.name = "RB532",
.ack = rb532_disable_irq,
.mask = rb532_disable_irq,
.mask_ack = rb532_mask_and_ack_irq,
.unmask = rb532_enable_irq,
};
void __init arch_init_irq(void)
{
int i;
pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
for (i = 0; i < RC32434_NR_IRQS; i++)
set_irq_chip_and_handler(i, &rc32434_irq_type,
handle_level_irq);
}
/* Main Interrupt dispatcher */
asmlinkage void plat_irq_dispatch(void)
{
unsigned int ip, pend, group;
volatile unsigned int *addr;
unsigned int cp0_cause = read_c0_cause() & read_c0_status();
if (cp0_cause & CAUSEF_IP7) {
do_IRQ(7);
} else {
ip = (cp0_cause & 0x7c00);
if (ip) {
group = 21 + (fls(ip) - 32);
addr = intr_group[group].base_addr;
pend = READ_PEND(addr);
pend &= ~READ_MASK(addr); /* only unmasked interrupts */
pend = 39 + (fls(pend) - 32);
do_IRQ((group << 5) + pend);
}
}
}
arch/mips/rb532/prom.c 0 → 100644
View file @ 73b4390f
/*
* RouterBoard 500 specific prom routines
*
* Copyright (C) 2003, Peter Sadik <peter.sadik@idt.com>
* Copyright (C) 2005-2006, P.Christeas <p_christ@hol.gr>
* Copyright (C) 2007, Gabor Juhos <juhosg@openwrt.org>
* Felix Fietkau <nbd@openwrt.org>
* Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA.
*
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/console.h>
#include <linux/bootmem.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <asm/bootinfo.h>
#include <asm/mach-rc32434/ddr.h>
#include <asm/mach-rc32434/prom.h>
extern void __init setup_serial_port(void);
unsigned int idt_cpu_freq = 132000000;
EXPORT_SYMBOL(idt_cpu_freq);
unsigned int gpio_bootup_state;
EXPORT_SYMBOL(gpio_bootup_state);
static struct resource ddr_reg[] = {
{
.name = "ddr-reg",
.start = DDR0_PHYS_ADDR,
.end = DDR0_PHYS_ADDR + sizeof(struct ddr_ram),
.flags = IORESOURCE_MEM,
}
};
void __init prom_free_prom_memory(void)
{
/* No prom memory to free */
}
static inline int match_tag(char *arg, const char *tag)
{
return strncmp(arg, tag, strlen(tag)) == 0;
}
static inline unsigned long tag2ul(char *arg, const char *tag)
{
char *num;
num = arg + strlen(tag);
return simple_strtoul(num, 0, 10);
}
void __init prom_setup_cmdline(void)
{
char cmd_line[CL_SIZE];
char *cp, *board;
int prom_argc;
char **prom_argv, **prom_envp;
int i;
prom_argc = fw_arg0;
prom_argv = (char **) fw_arg1;
prom_envp = (char **) fw_arg2;
cp = cmd_line;
/* Note: it is common that parameters start
* at argv[1] and not argv[0],
* however, our elf loader starts at [0] */
for (i = 0; i < prom_argc; i++) {
if (match_tag(prom_argv[i], FREQ_TAG)) {
idt_cpu_freq = tag2ul(prom_argv[i], FREQ_TAG);
continue;
}
#ifdef IGNORE_CMDLINE_MEM
/* parses out the "mem=xx" arg */
if (match_tag(prom_argv[i], MEM_TAG))
continue;
#endif
if (i > 0)
*(cp++) = ' ';
if (match_tag(prom_argv[i], BOARD_TAG)) {
board = prom_argv[i] + strlen(BOARD_TAG);
if (match_tag(board, BOARD_RB532A))
mips_machtype = MACH_MIKROTIK_RB532A;
else
mips_machtype = MACH_MIKROTIK_RB532;
}
if (match_tag(prom_argv[i], GPIO_TAG))
gpio_bootup_state = tag2ul(prom_argv[i], GPIO_TAG);
strcpy(cp, prom_argv[i]);
cp += strlen(prom_argv[i]);
}
*(cp++) = ' ';
i = strlen(arcs_cmdline);
if (i > 0) {
*(cp++) = ' ';
strcpy(cp, arcs_cmdline);
cp += strlen(arcs_cmdline);
}
if (gpio_bootup_state & 0x02)
strcpy(cp, GPIO_INIT_NOBUTTON);
else
strcpy(cp, GPIO_INIT_BUTTON);
cmd_line[CL_SIZE-1] = '\0';
strcpy(arcs_cmdline, cmd_line);
}
void __init prom_init(void)
{
struct ddr_ram __iomem *ddr;
phys_t memsize;
phys_t ddrbase;
ddr = ioremap_nocache(ddr_reg[0].start,
ddr_reg[0].end - ddr_reg[0].start);
if (!ddr) {
printk(KERN_ERR "Unable to remap DDR register\n");
return;
}
ddrbase = (phys_t)&ddr->ddrbase;
memsize = (phys_t)&ddr->ddrmask;
memsize = 0 - memsize;
prom_setup_cmdline();
/* give all RAM to boot allocator,
* except for the first 0x400 and the last 0x200 bytes */
add_memory_region(ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
}
arch/mips/rb532/serial.c 0 → 100644
View file @ 73b4390f
/*
* BRIEF MODULE DESCRIPTION
* Serial port initialisation.
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/tty.h>
#include <linux/serial_core.h>
#include <linux/serial_8250.h>
#include <asm/serial.h>
#include <asm/mach-rc32434/rc32434.h>
extern unsigned int idt_cpu_freq;
static struct uart_port rb532_uart = {
.type = PORT_16550A,
.line = 0,
.irq = RC32434_UART0_IRQ,
.iotype = UPIO_MEM,
.membase = (char *)KSEG1ADDR(RC32434_UART0_BASE),
.regshift = 2
};
int __init setup_serial_port(void)
{
rb532_uart.uartclk = idt_cpu_freq;
return early_serial_setup(&rb532_uart);
}
arch_initcall(setup_serial_port);
arch/mips/rb532/setup.c 0 → 100644
View file @ 73b4390f
/*
* setup.c - boot time setup code
*/
#include <linux/init.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <linux/ioport.h>
#include <asm/mach-rc32434/rc32434.h>
#include <asm/mach-rc32434/pci.h>
struct pci_reg __iomem *pci_reg;
EXPORT_SYMBOL(pci_reg);
static struct resource pci0_res[] = {
{
.name = "pci_reg0",
.start = PCI0_BASE_ADDR,
.end = PCI0_BASE_ADDR + sizeof(struct pci_reg),
.flags = IORESOURCE_MEM,
}
};
static void rb_machine_restart(char *command)
{
/* just jump to the reset vector */
writel(0x80000001, (void *)KSEG1ADDR(RC32434_REG_BASE + RC32434_RST));
((void (*)(void)) KSEG1ADDR(0x1FC00000u))();
}
static void rb_machine_halt(void)
{
for (;;)
continue;
}
void __init plat_mem_setup(void)
{
u32 val;
_machine_restart = rb_machine_restart;
_machine_halt = rb_machine_halt;
pm_power_off = rb_machine_halt;
set_io_port_base(KSEG1);
pci_reg = ioremap_nocache(pci0_res[0].start,
pci0_res[0].end - pci0_res[0].start);
if (!pci_reg) {
printk(KERN_ERR "Could not remap PCI registers\n");
return;
}
val = __raw_readl(&pci_reg->pcic);
val &= 0xFFFFFF7;
__raw_writel(val, (void *)&pci_reg->pcic);
#ifdef CONFIG_PCI
/* Enable PCI interrupts in EPLD Mask register */
*epld_mask = 0x0;
*(epld_mask + 1) = 0x0;
#endif
write_c0_wired(0);
}
const char *get_system_type(void)
{
switch (mips_machtype) {
case MACH_MIKROTIK_RB532A:
return "Mikrotik RB532A";
break;
default:
return "Mikrotik RB532";
break;
}
}
arch/mips/rb532/time.c 0 → 100644
View file @ 73b4390f
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* Setting up the clock on the MIPS boards.
*/
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/ptrace.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/mc146818rtc.h>
#include <linux/irq.h>
#include <linux/timex.h>
#include <asm/mipsregs.h>
#include <asm/debug.h>
#include <asm/time.h>
#include <asm/mach-rc32434/rc32434.h>
extern unsigned int idt_cpu_freq;
/*
* Figure out the r4k offset, the amount to increment the compare
* register for each time tick. There is no RTC available.
*
* The RC32434 counts at half the CPU *core* speed.
*/
static unsigned long __init cal_r4koff(void)
{
mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
return mips_hpt_frequency / HZ;
}
void __init plat_time_init(void)
{
unsigned int est_freq, flags;
unsigned long r4k_offset;
local_irq_save(flags);
printk(KERN_INFO "calculating r4koff... ");
r4k_offset = cal_r4koff();
printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
est_freq = 2 * r4k_offset * HZ;
est_freq += 5000; /* round */
est_freq -= est_freq % 10000;
printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
(est_freq % 1000000) * 100 / 1000000);
local_irq_restore(flags);
}
include/asm-mips/bootinfo.h
View file @ 73b4390f
...@@ -51,6 +51,12 @@ ...@@ -51,6 +51,12 @@
#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */ #define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */ #define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
/*
* Valid machtype for group Mikrotik
*/
#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */
#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */
#define CL_SIZE COMMAND_LINE_SIZE #define CL_SIZE COMMAND_LINE_SIZE
extern char *system_type; extern char *system_type;
......
include/asm-mips/mach-rc32434/cpu-feature-overrides.h 0 → 100644
View file @ 73b4390f
/*
* IDT RC32434 specific CPU feature overrides
*
* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
*
* This file was derived from: include/asm-mips/cpu-features.h
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA.
*/
#ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
/*
* The IDT RC32434 SOC has a built-in MIPS 4Kc core.
*/
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_tx39_cache 0
#define cpu_has_sb1_cache 0
#define cpu_has_fpu 0
#define cpu_has_32fpr 0
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_divec 1
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 1
#define cpu_has_mcheck 1
#define cpu_has_ejtag 1
#define cpu_has_llsc 1
#define cpu_has_mips16 0
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define cpu_has_vtag_icache 0
/* #define cpu_has_dc_aliases ? */
/* #define cpu_has_ic_fills_f_dc ? */
/* #define cpu_has_pindexed_dcache ? */
/* #define cpu_icache_snoops_remote_store ? */
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#define cpu_has_dsp 0
#define cpu_has_mipsmt 0
/* #define cpu_has_nofpuex ? */
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
#define cpu_has_64bit_gp_regs 0
#define cpu_has_64bit_addresses 0
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 16
#define cpu_icache_line_size() 16
#endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */
include/asm-mips/mach-rc32434/ddr.h 0 → 100644
View file @ 73b4390f
/*
* Definitions for the DDR registers
*
* Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
* Copyright 2008 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef _ASM_RC32434_DDR_H_
#define _ASM_RC32434_DDR_H_
#include <asm/mach-rc32434/rb.h>
/* DDR register structure */
struct ddr_ram {
u32 ddrbase;
u32 ddrmask;
u32 res1;
u32 res2;
u32 ddrc;
u32 ddrabase;
u32 ddramask;
u32 ddramap;
u32 ddrcust;
u32 ddrrdc;
u32 ddrspare;
};
#define DDR0_PHYS_ADDR 0x18018000
/* DDR banks masks */
#define DDR_MASK 0xffff0000
#define DDR0_BASE_MSK DDR_MASK
#define DDR1_BASE_MSK DDR_MASK
/* DDR bank0 registers */
#define RC32434_DDR0_ATA_BIT 5
#define RC32434_DDR0_ATA_MSK 0x000000E0
#define RC32434_DDR0_DBW_BIT 8
#define RC32434_DDR0_DBW_MSK 0x00000100
#define RC32434_DDR0_WR_BIT 9
#define RC32434_DDR0_WR_MSK 0x00000600
#define RC32434_DDR0_PS_BIT 11
#define RC32434_DDR0_PS_MSK 0x00001800
#define RC32434_DDR0_DTYPE_BIT 13
#define RC32434_DDR0_DTYPE_MSK 0x0000e000
#define RC32434_DDR0_RFC_BIT 16
#define RC32434_DDR0_RFC_MSK 0x000f0000
#define RC32434_DDR0_RP_BIT 20
#define RC32434_DDR0_RP_MSK 0x00300000
#define RC32434_DDR0_AP_BIT 22
#define RC32434_DDR0_AP_MSK 0x00400000
#define RC32434_DDR0_RCD_BIT 23
#define RC32434_DDR0_RCD_MSK 0x01800000
#define RC32434_DDR0_CL_BIT 25
#define RC32434_DDR0_CL_MSK 0x06000000
#define RC32434_DDR0_DBM_BIT 27
#define RC32434_DDR0_DBM_MSK 0x08000000
#define RC32434_DDR0_SDS_BIT 28
#define RC32434_DDR0_SDS_MSK 0x10000000
#define RC32434_DDR0_ATP_BIT 29
#define RC32434_DDR0_ATP_MSK 0x60000000
#define RC32434_DDR0_RE_BIT 31
#define RC32434_DDR0_RE_MSK 0x80000000
/* DDR bank C registers */
#define RC32434_DDRC_MSK(x) BIT_TO_MASK(x)
#define RC32434_DDRC_CES_BIT 0
#define RC32434_DDRC_ACE_BIT 1
/* Custom DDR bank registers */
#define RC32434_DCST_MSK(x) BIT_TO_MASK(x)
#define RC32434_DCST_CS_BIT 0
#define RC32434_DCST_CS_MSK 0x00000003
#define RC32434_DCST_WE_BIT 2
#define RC32434_DCST_RAS_BIT 3
#define RC32434_DCST_CAS_BIT 4
#define RC32434_DSCT_CKE_BIT 5
#define RC32434_DSCT_BA_BIT 6
#define RC32434_DSCT_BA_MSK 0x000000c0
/* DDR QSC registers */
#define RC32434_QSC_DM_BIT 0
#define RC32434_QSC_DM_MSK 0x00000003
#define RC32434_QSC_DQSBS_BIT 2
#define RC32434_QSC_DQSBS_MSK 0x000000fc
#define RC32434_QSC_DB_BIT 8
#define RC32434_QSC_DB_MSK 0x00000100
#define RC32434_QSC_DBSP_BIT 9
#define RC32434_QSC_DBSP_MSK 0x01fffe00
#define RC32434_QSC_BDP_BIT 25
#define RC32434_QSC_BDP_MSK 0x7e000000
/* DDR LLC registers */
#define RC32434_LLC_EAO_BIT 0
#define RC32434_LLC_EAO_MSK 0x00000001
#define RC32434_LLC_EO_BIT 1
#define RC32434_LLC_EO_MSK 0x0000003e
#define RC32434_LLC_FS_BIT 6
#define RC32434_LLC_FS_MSK 0x000000c0
#define RC32434_LLC_AS_BIT 8
#define RC32434_LLC_AS_MSK 0x00000700
#define RC32434_LLC_SP_BIT 11
#define RC32434_LLC_SP_MSK 0x001ff800
/* DDR LLFC registers */
#define RC32434_LLFC_MSK(x) BIT_TO_MASK(x)
#define RC32434_LLFC_MEN_BIT 0
#define RC32434_LLFC_EAN_BIT 1
#define RC32434_LLFC_FF_BIT 2
/* DDR DLLTA registers */
#define RC32434_DLLTA_ADDR_BIT 2
#define RC32434_DLLTA_ADDR_MSK 0xfffffffc
/* DDR DLLED registers */
#define RC32434_DLLED_MSK(x) BIT_TO_MASK(x)
#define RC32434_DLLED_DBE_BIT 0
#define RC32434_DLLED_DTE_BIT 1
#endif /* _ASM_RC32434_DDR_H_ */
include/asm-mips/mach-rc32434/dma.h 0 → 100644
View file @ 73b4390f
/*
* Copyright 2002 Integrated Device Technology, Inc.
* All rights reserved.
*
* DMA register definition.
*
* Author : ryan.holmQVist@idt.com
* Date : 20011005
*/
#ifndef __ASM_RC32434_DMA_H
#define __ASM_RC32434_DMA_H
#include <asm/mach-rc32434/rb.h>
#define DMA0_BASE_ADDR 0x18040000
/*
* DMA descriptor (in physical memory).
*/
struct dma_desc {
u32 control; /* Control. use DMAD_* */
u32 ca; /* Current Address. */
u32 devcs; /* Device control and status. */
u32 link; /* Next descriptor in chain. */
};
#define DMA_DESC_SIZ sizeof(struct dma_desc)
#define DMA_DESC_COUNT_BIT 0
#define DMA_DESC_COUNT_MSK 0x0003ffff
#define DMA_DESC_DS_BIT 20
#define DMA_DESC_DS_MSK 0x00300000
#define DMA_DESC_DEV_CMD_BIT 22
#define DMA_DESC_DEV_CMD_MSK 0x01c00000
/* DMA command sizes */
#define DMA_DESC_DEV_CMD_BYTE 0
#define DMA_DESC_DEV_CMD_HLF_WD 1
#define DMA_DESC_DEV_CMD_WORD 2
#define DMA_DESC_DEV_CMD_2WORDS 3
#define DMA_DESC_DEV_CMD_4WORDS 4
#define DMA_DESC_DEV_CMD_6WORDS 5
#define DMA_DESC_DEV_CMD_8WORDS 6
#define DMA_DESC_DEV_CMD_16WORDS 7
/* DMA descriptors interrupts */
#define DMA_DESC_COF (1 << 25) /* Chain on finished */
#define DMA_DESC_COD (1 << 26) /* Chain on done */
#define DMA_DESC_IOF (1 << 27) /* Interrupt on finished */
#define DMA_DESC_IOD (1 << 28) /* Interrupt on done */
#define DMA_DESC_TERM (1 << 29) /* Terminated */
#define DMA_DESC_DONE (1 << 30) /* Done */
#define DMA_DESC_FINI (1 << 31) /* Finished */
/*
* DMA register (within Internal Register Map).
*/
struct dma_reg {
u32 dmac; /* Control. */
u32 dmas; /* Status. */
u32 dmasm; /* Mask. */
u32 dmadptr; /* Descriptor pointer. */
u32 dmandptr; /* Next descriptor pointer. */
};
/* DMA channels specific registers */
#define DMA_CHAN_RUN_BIT (1 << 0)
#define DMA_CHAN_DONE_BIT (1 << 1)
#define DMA_CHAN_MODE_BIT (1 << 2)
#define DMA_CHAN_MODE_MSK 0x0000000c
#define DMA_CHAN_MODE_AUTO 0
#define DMA_CHAN_MODE_BURST 1
#define DMA_CHAN_MODE_XFRT 2
#define DMA_CHAN_MODE_RSVD 3
#define DMA_CHAN_ACT_BIT (1 << 4)
/* DMA status registers */
#define DMA_STAT_FINI (1 << 0)
#define DMA_STAT_DONE (1 << 1)
#define DMA_STAT_CHAIN (1 << 2)
#define DMA_STAT_ERR (1 << 3)
#define DMA_STAT_HALT (1 << 4)
/*
* DMA channel definitions
*/
#define DMA_CHAN_ETH_RCV 0
#define DMA_CHAN_ETH_XMT 1
#define DMA_CHAN_MEM_TO_FIFO 2
#define DMA_CHAN_FIFO_TO_MEM 3
#define DMA_CHAN_PCI_TO_MEM 4
#define DMA_CHAN_MEM_TO_PCI 5
#define DMA_CHAN_COUNT 6
struct dma_channel {
struct dma_reg ch[DMA_CHAN_COUNT];
};
#endif /* __ASM_RC32434_DMA_H */
include/asm-mips/mach-rc32434/dma_v.h 0 → 100644
View file @ 73b4390f
/*
* Copyright 2002 Integrated Device Technology, Inc.
* All rights reserved.
*
* DMA register definition.
*
* Author : ryan.holmQVist@idt.com
* Date : 20011005
*/
#ifndef _ASM_RC32434_DMA_V_H_
#define _ASM_RC32434_DMA_V_H_
#include <asm/mach-rc32434/dma.h>
#include <asm/mach-rc32434/rc32434.h>
#define DMA_CHAN_OFFSET 0x14
#define IS_DMA_USED(X) (((X) & \
(DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \
!= 0)
#define DMA_COUNT(count) ((count) & DMA_DESC_COUNT_MSK)
#define DMA_HALT_TIMEOUT 500
static inline int rc32434_halt_dma(struct dma_reg *ch)
{
int timeout = 1;
if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
__raw_writel(0, &ch->dmac);
for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) {
__raw_writel(0, &ch->dmas);
break;
}
}
}
return timeout ? 0 : 1;
}
static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr)
{
__raw_writel(0, &ch->dmandptr);
__raw_writel(dma_addr, &ch->dmadptr);
}
static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr)
{
__raw_writel(dma_addr, &ch->dmandptr);
}
#endif /* _ASM_RC32434_DMA_V_H_ */
include/asm-mips/mach-rc32434/eth.h 0 → 100644
View file @ 73b4390f
/*
* Definitions for the Ethernet registers
*
* Copyright 2002 Allend Stichter <allen.stichter@idt.com>
* Copyright 2008 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __ASM_RC32434_ETH_H
#define __ASM_RC32434_ETH_H
#define ETH0_BASE_ADDR 0x18060000
struct eth_regs {
u32 ethintfc;
u32 ethfifott;
u32 etharc;
u32 ethhash0;
u32 ethhash1;
u32 ethu0[4]; /* Reserved. */
u32 ethpfs;
u32 ethmcp;
u32 eth_u1[10]; /* Reserved. */
u32 ethspare;
u32 eth_u2[42]; /* Reserved. */
u32 ethsal0;
u32 ethsah0;
u32 ethsal1;
u32 ethsah1;
u32 ethsal2;
u32 ethsah2;
u32 ethsal3;
u32 ethsah3;
u32 ethrbc;
u32 ethrpc;
u32 ethrupc;
u32 ethrfc;
u32 ethtbc;
u32 ethgpf;
u32 eth_u9[50]; /* Reserved. */
u32 ethmac1;
u32 ethmac2;
u32 ethipgt;
u32 ethipgr;
u32 ethclrt;
u32 ethmaxf;
u32 eth_u10; /* Reserved. */
u32 ethmtest;
u32 miimcfg;
u32 miimcmd;
u32 miimaddr;
u32 miimwtd;
u32 miimrdd;
u32 miimind;
u32 eth_u11; /* Reserved. */
u32 eth_u12; /* Reserved. */
u32 ethcfsa0;
u32 ethcfsa1;
u32 ethcfsa2;
};
/* Ethernet interrupt registers */
#define ETH_INT_FC_EN (1 << 0)
#define ETH_INT_FC_ITS (1 << 1)
#define ETH_INT_FC_RIP (1 << 2)
#define ETH_INT_FC_JAM (1 << 3)
#define ETH_INT_FC_OVR (1 << 4)
#define ETH_INT_FC_UND (1 << 5)
#define ETH_INT_FC_IOC 0x000000c0
/* Ethernet FIFO registers */
#define ETH_FIFI_TT_TTH_BIT 0
#define ETH_FIFO_TT_TTH 0x0000007f
/* Ethernet ARC/multicast registers */
#define ETH_ARC_PRO (1 << 0)
#define ETH_ARC_AM (1 << 1)
#define ETH_ARC_AFM (1 << 2)
#define ETH_ARC_AB (1 << 3)
/* Ethernet SAL registers */
#define ETH_SAL_BYTE_5 0x000000ff
#define ETH_SAL_BYTE_4 0x0000ff00
#define ETH_SAL_BYTE_3 0x00ff0000
#define ETH_SAL_BYTE_2 0xff000000
/* Ethernet SAH registers */
#define ETH_SAH_BYTE1 0x000000ff
#define ETH_SAH_BYTE0 0x0000ff00
/* Ethernet GPF register */
#define ETH_GPF_PTV 0x0000ffff
/* Ethernet PFG register */
#define ETH_PFS_PFD (1 << 0)
/* Ethernet CFSA[0-3] registers */
#define ETH_CFSA0_CFSA4 0x000000ff
#define ETH_CFSA0_CFSA5 0x0000ff00
#define ETH_CFSA1_CFSA2 0x000000ff
#define ETH_CFSA1_CFSA3 0x0000ff00
#define ETH_CFSA1_CFSA0 0x000000ff
#define ETH_CFSA1_CFSA1 0x0000ff00
/* Ethernet MAC1 registers */
#define ETH_MAC1_RE (1 << 0)
#define ETH_MAC1_PAF (1 << 1)
#define ETH_MAC1_RFC (1 << 2)
#define ETH_MAC1_TFC (1 << 3)
#define ETH_MAC1_LB (1 << 4)
#define ETH_MAC1_MR (1 << 31)
/* Ethernet MAC2 registers */
#define ETH_MAC2_FD (1 << 0)
#define ETH_MAC2_FLC (1 << 1)
#define ETH_MAC2_HFE (1 << 2)
#define ETH_MAC2_DC (1 << 3)
#define ETH_MAC2_CEN (1 << 4)
#define ETH_MAC2_PE (1 << 5)
#define ETH_MAC2_VPE (1 << 6)
#define ETH_MAC2_APE (1 << 7)
#define ETH_MAC2_PPE (1 << 8)
#define ETH_MAC2_LPE (1 << 9)
#define ETH_MAC2_NB (1 << 12)
#define ETH_MAC2_BP (1 << 13)
#define ETH_MAC2_ED (1 << 14)
/* Ethernet IPGT register */
#define ETH_IPGT 0x0000007f
/* Ethernet IPGR registers */
#define ETH_IPGR_IPGR2 0x0000007f
#define ETH_IPGR_IPGR1 0x00007f00
/* Ethernet CLRT registers */
#define ETH_CLRT_MAX_RET 0x0000000f
#define ETH_CLRT_COL_WIN 0x00003f00
/* Ethernet MAXF register */
#define ETH_MAXF 0x0000ffff
/* Ethernet test registers */
#define ETH_TEST_REG (1 << 2)
#define ETH_MCP_DIV 0x000000ff
/* MII registers */
#define ETH_MII_CFG_RSVD 0x0000000c
#define ETH_MII_CMD_RD (1 << 0)
#define ETH_MII_CMD_SCN (1 << 1)
#define ETH_MII_REG_ADDR 0x0000001f
#define ETH_MII_PHY_ADDR 0x00001f00
#define ETH_MII_WTD_DATA 0x0000ffff
#define ETH_MII_RDD_DATA 0x0000ffff
#define ETH_MII_IND_BSY (1 << 0)
#define ETH_MII_IND_SCN (1 << 1)
#define ETH_MII_IND_NV (1 << 2)
/*
* Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
*/
#define ETH_RX_FD (1 << 0)
#define ETH_RX_LD (1 << 1)
#define ETH_RX_ROK (1 << 2)
#define ETH_RX_FM (1 << 3)
#define ETH_RX_MP (1 << 4)
#define ETH_RX_BP (1 << 5)
#define ETH_RX_VLT (1 << 6)
#define ETH_RX_CF (1 << 7)
#define ETH_RX_OVR (1 << 8)
#define ETH_RX_CRC (1 << 9)
#define ETH_RX_CV (1 << 10)
#define ETH_RX_DB (1 << 11)
#define ETH_RX_LE (1 << 12)
#define ETH_RX_LOR (1 << 13)
#define ETH_RX_CES (1 << 14)
#define ETH_RX_LEN_BIT 16
#define ETH_RX_LEN 0xffff0000
#define ETH_TX_FD (1 << 0)
#define ETH_TX_LD (1 << 1)
#define ETH_TX_OEN (1 << 2)
#define ETH_TX_PEN (1 << 3)
#define ETH_TX_CEN (1 << 4)
#define ETH_TX_HEN (1 << 5)
#define ETH_TX_TOK (1 << 6)
#define ETH_TX_MP (1 << 7)
#define ETH_TX_BP (1 << 8)
#define ETH_TX_UND (1 << 9)
#define ETH_TX_OF (1 << 10)
#define ETH_TX_ED (1 << 11)
#define ETH_TX_EC (1 << 12)
#define ETH_TX_LC (1 << 13)
#define ETH_TX_TD (1 << 14)
#define ETH_TX_CRC (1 << 15)
#define ETH_TX_LE (1 << 16)
#define ETH_TX_CC 0x001E0000
#endif /* __ASM_RC32434_ETH_H */
include/asm-mips/mach-rc32434/gpio.h 0 → 100644
View file @ 73b4390f
/*
* Copyright 2002 Integrated Device Technology, Inc.
* All rights reserved.
*
* GPIO register definition.
*
* Author : ryan.holmQVist@idt.com
* Date : 20011005
* Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
*/
#ifndef _RC32434_GPIO_H_
#define _RC32434_GPIO_H_
#include <linux/types.h>
struct rb532_gpio_reg {
u32 gpiofunc; /* GPIO Function Register
* gpiofunc[x]==0 bit = gpio
* func[x]==1 bit = altfunc
*/
u32 gpiocfg; /* GPIO Configuration Register
* gpiocfg[x]==0 bit = input
* gpiocfg[x]==1 bit = output
*/
u32 gpiod; /* GPIO Data Register
* gpiod[x] read/write gpio pinX status
*/
u32 gpioilevel; /* GPIO Interrupt Status Register
* interrupt level (see gpioistat)
*/
u32 gpioistat; /* Gpio Interrupt Status Register
* istat[x] = (gpiod[x] == level[x])
* cleared in ISR (STICKY bits)
*/
u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
};
/* UART GPIO signals */
#define RC32434_UART0_SOUT (1 << 0)
#define RC32434_UART0_SIN (1 << 1)
#define RC32434_UART0_RTS (1 << 2)
#define RC32434_UART0_CTS (1 << 3)
/* M & P bus GPIO signals */
#define RC32434_MP_BIT_22 (1 << 4)
#define RC32434_MP_BIT_23 (1 << 5)
#define RC32434_MP_BIT_24 (1 << 6)
#define RC32434_MP_BIT_25 (1 << 7)
/* CPU GPIO signals */
#define RC32434_CPU_GPIO (1 << 8)
/* Reserved GPIO signals */
#define RC32434_AF_SPARE_6 (1 << 9)
#define RC32434_AF_SPARE_4 (1 << 10)
#define RC32434_AF_SPARE_3 (1 << 11)
#define RC32434_AF_SPARE_2 (1 << 12)
/* PCI messaging unit */
#define RC32434_PCI_MSU_GPIO (1 << 13)
extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
extern unsigned get_434_reg(unsigned reg_offs);
extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
extern unsigned char get_latch_u5(void);
extern int rb532_gpio_get_value(unsigned gpio);
extern void rb532_gpio_set_value(unsigned gpio, int value);
extern int rb532_gpio_direction_input(unsigned gpio);
extern int rb532_gpio_direction_output(unsigned gpio, int value);
extern void rb532_gpio_set_int_level(unsigned gpio, int value);
extern int rb532_gpio_get_int_level(unsigned gpio);
extern void rb532_gpio_set_int_status(unsigned gpio, int value);
extern int rb532_gpio_get_int_status(unsigned gpio);
/* Wrappers for the arch-neutral GPIO API */
static inline int gpio_request(unsigned gpio, const char *label)
{
/* Not yet implemented */
return 0;
}
static inline void gpio_free(unsigned gpio)
{
/* Not yet implemented */
}
static inline int gpio_direction_input(unsigned gpio)
{
return rb532_gpio_direction_input(gpio);
}
static inline int gpio_direction_output(unsigned gpio, int value)
{
return rb532_gpio_direction_output(gpio, value);
}
static inline int gpio_get_value(unsigned gpio)
{
return rb532_gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
rb532_gpio_set_value(gpio, value);
}
static inline int gpio_to_irq(unsigned gpio)
{
return gpio;
}
static inline int irq_to_gpio(unsigned irq)
{
return irq;
}
/* For cansleep */
#include <asm-generic/gpio.h>
#endif /* _RC32434_GPIO_H_ */
include/asm-mips/mach-rc32434/integ.h 0 → 100644
View file @ 73b4390f
/*
* Definitions for the Watchdog registers
*
* Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
* Copyright 2008 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __RC32434_INTEG_H__
#define __RC32434_INTEG_H__
#include <asm/mach-rc32434/rb.h>
#define INTEG0_BASE_ADDR 0x18030030
struct integ {
u32 errcs; /* sticky use ERRCS_ */
u32 wtcount; /* Watchdog timer count reg. */
u32 wtcompare; /* Watchdog timer timeout value. */
u32 wtc; /* Watchdog timer control. use WTC_ */
};
/* Error counters */
#define RC32434_ERR_WTO 0
#define RC32434_ERR_WNE 1
#define RC32434_ERR_UCW 2
#define RC32434_ERR_UCR 3
#define RC32434_ERR_UPW 4
#define RC32434_ERR_UPR 5
#define RC32434_ERR_UDW 6
#define RC32434_ERR_UDR 7
#define RC32434_ERR_SAE 8
#define RC32434_ERR_WRE 9
/* Watchdog control bits */
#define RC32434_WTC_EN 0
#define RC32434_WTC_TO 1
#endif /* __RC32434_INTEG_H__ */
include/asm-mips/mach-rc32434/irq.h 0 → 100644
View file @ 73b4390f
#ifndef __ASM_RC32434_IRQ_H
#define __ASM_RC32434_IRQ_H
#define NR_IRQS 256
#include <asm/mach-generic/irq.h>
#endif /* __ASM_RC32434_IRQ_H */
include/asm-mips/mach-rc32434/pci.h 0 → 100644
View file @ 73b4390f
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Copyright 2004 IDT Inc. (rischelp@idt.com)
*
* Initial Release
*/
#ifndef _ASM_RC32434_PCI_H_
#define _ASM_RC32434_PCI_H_
#define epld_mask ((volatile unsigned char *)0xB900000d)
#define PCI0_BASE_ADDR 0x18080000
#define PCI_LBA_COUNT 4
struct pci_map {
u32 address; /* Address. */
u32 control; /* Control. */
u32 mapping; /* mapping. */
};
struct pci_reg {
u32 pcic;
u32 pcis;
u32 pcism;
u32 pcicfga;
u32 pcicfgd;
volatile struct pci_map pcilba[PCI_LBA_COUNT];
u32 pcidac;
u32 pcidas;
u32 pcidasm;
u32 pcidad;
u32 pcidma8c;
u32 pcidma9c;
u32 pcitc;
};
#define PCI_MSU_COUNT 2
struct pci_msu {
u32 pciim[PCI_MSU_COUNT];
u32 pciom[PCI_MSU_COUNT];
u32 pciid;
u32 pciiic;
u32 pciiim;
u32 pciiod;
u32 pciioic;
u32 pciioim;
};
/*
* PCI Control Register
*/
#define PCI_CTL_EN (1 << 0)
#define PCI_CTL_TNR (1 << 1)
#define PCI_CTL_SCE (1 << 2)
#define PCI_CTL_IEN (1 << 3)
#define PCI_CTL_AAA (1 << 4)
#define PCI_CTL_EAP (1 << 5)
#define PCI_CTL_PCIM_BIT 6
#define PCI_CTL_PCIM 0x000001c0
#define PCI_CTL_PCIM_DIS 0
#define PCI_CTL_PCIM_TNR 1 /* Satellite - target not ready */
#define PCI_CTL_PCIM_SUS 2 /* Satellite - suspended CPU. */
#define PCI_CTL_PCIM_EXT 3 /* Host - external arbiter. */
#define PCI_CTL PCIM_PRIO 4 /* Host - fixed priority arb. */
#define PCI_CTL_PCIM_RR 5 /* Host - round robin priority. */
#define PCI_CTL_PCIM_RSVD6 6
#define PCI_CTL_PCIM_RSVD7 7
#define PCI_CTL_IGM (1 << 9)
/*
* PCI Status Register
*/
#define PCI_STAT_EED (1 << 0)
#define PCI_STAT_WR (1 << 1)
#define PCI_STAT_NMI (1 << 2)
#define PCI_STAT_II (1 << 3)
#define PCI_STAT_CWE (1 << 4)
#define PCI_STAT_CRE (1 << 5)
#define PCI_STAT_MDPE (1 << 6)
#define PCI_STAT_STA (1 << 7)
#define PCI_STAT_RTA (1 << 8)
#define PCI_STAT_RMA (1 << 9)
#define PCI_STAT_SSE (1 << 10)
#define PCI_STAT_OSE (1 << 11)
#define PCI_STAT_PE (1 << 12)
#define PCI_STAT_TAE (1 << 13)
#define PCI_STAT_RLE (1 << 14)
#define PCI_STAT_BME (1 << 15)
#define PCI_STAT_PRD (1 << 16)
#define PCI_STAT_RIP (1 << 17)
/*
* PCI Status Mask Register
*/
#define PCI_STATM_EED PCI_STAT_EED
#define PCI_STATM_WR PCI_STAT_WR
#define PCI_STATM_NMI PCI_STAT_NMI
#define PCI_STATM_II PCI_STAT_II
#define PCI_STATM_CWE PCI_STAT_CWE
#define PCI_STATM_CRE PCI_STAT_CRE
#define PCI_STATM_MDPE PCI_STAT_MDPE
#define PCI_STATM_STA PCI_STAT_STA
#define PCI_STATM_RTA PCI_STAT_RTA
#define PCI_STATM_RMA PCI_STAT_RMA
#define PCI_STATM_SSE PCI_STAT_SSE
#define PCI_STATM_OSE PCI_STAT_OSE
#define PCI_STATM_PE PCI_STAT_PE
#define PCI_STATM_TAE PCI_STAT_TAE
#define PCI_STATM_RLE PCI_STAT_RLE
#define PCI_STATM_BME PCI_STAT_BME
#define PCI_STATM_PRD PCI_STAT_PRD
#define PCI_STATM_RIP PCI_STAT_RIP
/*
* PCI Configuration Address Register
*/
#define PCI_CFGA_REG_BIT 2
#define PCI_CFGA_REG 0x000000fc
#define PCI_CFGA_REG_ID (0x00 >> 2) /* use PCFGID */
#define PCI_CFGA_REG_04 (0x04 >> 2) /* use PCFG04_ */
#define PCI_CFGA_REG_08 (0x08 >> 2) /* use PCFG08_ */
#define PCI_CFGA_REG_0C (0x0C >> 2) /* use PCFG0C_ */
#define PCI_CFGA_REG_PBA0 (0x10 >> 2) /* use PCIPBA_ */
#define PCI_CFGA_REG_PBA1 (0x14 >> 2) /* use PCIPBA_ */
#define PCI_CFGA_REG_PBA2 (0x18 >> 2) /* use PCIPBA_ */
#define PCI_CFGA_REG_PBA3 (0x1c >> 2) /* use PCIPBA_ */
#define PCI_CFGA_REG_SUBSYS (0x2c >> 2) /* use PCFGSS_ */
#define PCI_CFGA_REG_3C (0x3C >> 2) /* use PCFG3C_ */
#define PCI_CFGA_REG_PBBA0C (0x44 >> 2) /* use PCIPBAC_ */
#define PCI_CFGA_REG_PBA0M (0x48 >> 2)
#define PCI_CFGA_REG_PBA1C (0x4c >> 2) /* use PCIPBAC_ */
#define PCI_CFGA_REG_PBA1M (0x50 >> 2)
#define PCI_CFGA_REG_PBA2C (0x54 >> 2) /* use PCIPBAC_ */
#define PCI_CFGA_REG_PBA2M (0x58 >> 2)
#define PCI_CFGA_REG_PBA3C (0x5c >> 2) /* use PCIPBAC_ */
#define PCI_CFGA_REG_PBA3M (0x60 >> 2)
#define PCI_CFGA_REG_PMGT (0x64 >> 2)
#define PCI_CFGA_FUNC_BIT 8
#define PCI_CFGA_FUNC 0x00000700
#define PCI_CFGA_DEV_BIT 11
#define PCI_CFGA_DEV 0x0000f800
#define PCI_CFGA_DEV_INTERN 0
#define PCI_CFGA_BUS_BIT 16
#define PCI CFGA_BUS 0x00ff0000
#define PCI_CFGA_BUS_TYPE0 0
#define PCI_CFGA_EN (1 << 31)
/* PCI CFG04 commands */
#define PCI_CFG04_CMD_IO_ENA (1 << 0)
#define PCI_CFG04_CMD_MEM_ENA (1 << 1)
#define PCI_CFG04_CMD_BM_ENA (1 << 2)
#define PCI_CFG04_CMD_MW_INV (1 << 4)
#define PCI_CFG04_CMD_PAR_ENA (1 << 6)
#define PCI_CFG04_CMD_SER_ENA (1 << 8)
#define PCI_CFG04_CMD_FAST_ENA (1 << 9)
/* PCI CFG04 status fields */
#define PCI_CFG04_STAT_BIT 16
#define PCI_CFG04_STAT 0xffff0000
#define PCI_CFG04_STAT_66_MHZ (1 << 21)
#define PCI_CFG04_STAT_FBB (1 << 23)
#define PCI_CFG04_STAT_MDPE (1 << 24)
#define PCI_CFG04_STAT_DST (1 << 25)
#define PCI_CFG04_STAT_STA (1 << 27)
#define PCI_CFG04_STAT_RTA (1 << 28)
#define PCI_CFG04_STAT_RMA (1 << 29)
#define PCI_CFG04_STAT_SSE (1 << 30)
#define PCI_CFG04_STAT_PE (1 << 31)
#define PCI_PBA_MSI (1 << 0)
#define PCI_PBA_P (1 << 2)
/* PCI PBAC registers */
#define PCI_PBAC_MSI (1 << 0)
#define PCI_PBAC_P (1 << 1)
#define PCI_PBAC_SIZE_BIT 2
#define PCI_PBAC_SIZE 0x0000007c
#define PCI_PBAC_SB (1 << 7)
#define PCI_PBAC_PP (1 << 8)
#define PCI_PBAC_MR_BIT 9
#define PCI_PBAC_MR 0x00000600
#define PCI_PBAC_MR_RD 0
#define PCI_PBAC_MR_RD_LINE 1
#define PCI_PBAC_MR_RD_MULT 2
#define PCI_PBAC_MRL (1 << 11)
#define PCI_PBAC_MRM (1 << 12)
#define PCI_PBAC_TRP (1 << 13)
#define PCI_CFG40_TRDY_TIM 0x000000ff
#define PCI_CFG40_RET_LIM 0x0000ff00
/*
* PCI Local Base Address [0|1|2|3] Register
*/
#define PCI_LBA_BADDR_BIT 0
#define PCI_LBA_BADDR 0xffffff00
/*
* PCI Local Base Address Control Register
*/
#define PCI_LBAC_MSI (1 << 0)
#define PCI_LBAC_MSI_MEM 0
#define PCI_LBAC_MSI_IO 1
#define PCI_LBAC_SIZE_BIT 2
#define PCI_LBAC_SIZE 0x0000007c
#define PCI_LBAC_SB (1 << 7)
#define PCI_LBAC_RT (1 << 8)
#define PCI_LBAC_RT_NO_PREF 0
#define PCI_LBAC_RT_PREF 1
/*
* PCI Local Base Address [0|1|2|3] Mapping Register
*/
#define PCI_LBAM_MADDR_BIT 8
#define PCI_LBAM_MADDR 0xffffff00
/*
* PCI Decoupled Access Control Register
*/
#define PCI_DAC_DEN (1 << 0)
/*
* PCI Decoupled Access Status Register
*/
#define PCI_DAS_D (1 << 0)
#define PCI_DAS_B (1 << 1)
#define PCI_DAS_E (1 << 2)
#define PCI_DAS_OFE (1 << 3)
#define PCI_DAS_OFF (1 << 4)
#define PCI_DAS_IFE (1 << 5)
#define PCI_DAS_IFF (1 << 6)
/*
* PCI DMA Channel 8 Configuration Register
*/
#define PCI_DMA8C_MBS_BIT 0
#define PCI_DMA8C_MBS 0x00000fff /* Maximum Burst Size. */
#define PCI_DMA8C_OUR (1 << 12)
/*
* PCI DMA Channel 9 Configuration Register
*/
#define PCI_DMA9C_MBS_BIT 0 /* Maximum Burst Size. */
#define PCI_DMA9C_MBS 0x00000fff
/*
* PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
*/
#define PCI_DMAD_PT_BIT 22 /* in DEVCMD field (descriptor) */
#define PCI_DMAD_PT 0x00c00000 /* preferred transaction field */
/* These are for reads (DMA channel 8) */
#define PCI_DMAD_DEVCMD_MR 0 /* memory read */
#define PCI_DMAD_DEVCMD_MRL 1 /* memory read line */
#define PCI_DMAD_DEVCMD_MRM 2 /* memory read multiple */
#define PCI_DMAD_DEVCMD_IOR 3 /* I/O read */
/* These are for writes (DMA channel 9) */
#define PCI_DMAD_DEVCMD_MW 0 /* memory write */
#define PCI_DMAD_DEVCMD_MWI 1 /* memory write invalidate */
#define PCI_DMAD_DEVCMD_IOW 3 /* I/O write */
/* Swap byte field applies to both DMA channel 8 and 9 */
#define PCI_DMAD_SB (1 << 24) /* swap byte field */
/*
* PCI Target Control Register
*/
#define PCI_TC_RTIMER_BIT 0
#define PCI_TC_RTIMER 0x000000ff
#define PCI_TC_DTIMER_BIT 8
#define PCI_TC_DTIMER 0x0000ff00
#define PCI_TC_RDR (1 << 18)
#define PCI_TC_DDT (1 << 19)
/*
* PCI messaging unit [applies to both inbound and outbound registers ]
*/
#define PCI_MSU_M0 (1 << 0)
#define PCI_MSU_M1 (1 << 1)
#define PCI_MSU_DB (1 << 2)
#define PCI_MSG_ADDR 0xB8088010
#define PCI0_ADDR 0xB8080000
#define rc32434_pci ((struct pci_reg *) PCI0_ADDR)
#define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR)
#define PCIM_SHFT 0x6
#define PCIM_BIT_LEN 0x7
#define PCIM_H_EA 0x3
#define PCIM_H_IA_FIX 0x4
#define PCIM_H_IA_RR 0x5
#if 0
#define PCI_ADDR_START 0x13000000
#endif
#define PCI_ADDR_START 0x50000000
#define CPUTOPCI_MEM_WIN 0x02000000
#define CPUTOPCI_IO_WIN 0x00100000
#define PCILBA_SIZE_SHFT 2
#define PCILBA_SIZE_MASK 0x1F
#define SIZE_256MB 0x1C
#define SIZE_128MB 0x1B
#define SIZE_64MB 0x1A
#define SIZE_32MB 0x19
#define SIZE_16MB 0x18
#define SIZE_4MB 0x16
#define SIZE_2MB 0x15
#define SIZE_1MB 0x14
#define KORINA_CONFIG0_ADDR 0x80000000
#define KORINA_CONFIG1_ADDR 0x80000004
#define KORINA_CONFIG2_ADDR 0x80000008
#define KORINA_CONFIG3_ADDR 0x8000000C
#define KORINA_CONFIG4_ADDR 0x80000010
#define KORINA_CONFIG5_ADDR 0x80000014
#define KORINA_CONFIG6_ADDR 0x80000018
#define KORINA_CONFIG7_ADDR 0x8000001C
#define KORINA_CONFIG8_ADDR 0x80000020
#define KORINA_CONFIG9_ADDR 0x80000024
#define KORINA_CONFIG10_ADDR 0x80000028
#define KORINA_CONFIG11_ADDR 0x8000002C
#define KORINA_CONFIG12_ADDR 0x80000030
#define KORINA_CONFIG13_ADDR 0x80000034
#define KORINA_CONFIG14_ADDR 0x80000038
#define KORINA_CONFIG15_ADDR 0x8000003C
#define KORINA_CONFIG16_ADDR 0x80000040
#define KORINA_CONFIG17_ADDR 0x80000044
#define KORINA_CONFIG18_ADDR 0x80000048
#define KORINA_CONFIG19_ADDR 0x8000004C
#define KORINA_CONFIG20_ADDR 0x80000050
#define KORINA_CONFIG21_ADDR 0x80000054
#define KORINA_CONFIG22_ADDR 0x80000058
#define KORINA_CONFIG23_ADDR 0x8000005C
#define KORINA_CONFIG24_ADDR 0x80000060
#define KORINA_CONFIG25_ADDR 0x80000064
#define KORINA_CMD (PCI_CFG04_CMD_IO_ENA | \
PCI_CFG04_CMD_MEM_ENA | \
PCI_CFG04_CMD_BM_ENA | \
PCI_CFG04_CMD_MW_INV | \
PCI_CFG04_CMD_PAR_ENA | \
PCI_CFG04_CMD_SER_ENA)
#define KORINA_STAT (PCI_CFG04_STAT_MDPE | \
PCI_CFG04_STAT_STA | \
PCI_CFG04_STAT_RTA | \
PCI_CFG04_STAT_RMA | \
PCI_CFG04_STAT_SSE | \
PCI_CFG04_STAT_PE)
#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
#define KORINA_REVID 0
#define KORINA_CLASS_CODE 0
#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
KORINA_REVID)
#define KORINA_CACHE_LINE_SIZE 4
#define KORINA_MASTER_LAT 0x3c
#define KORINA_HEADER_TYPE 0
#define KORINA_BIST 0
#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
(KORINA_HEADER_TYPE<<16) | \
(KORINA_MASTER_LAT<<8) | \
KORINA_CACHE_LINE_SIZE)
#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
#define KORINA_BAR1 0x18800001 /* 1 MB IO */
#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
internal Registers */
#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
#define KORINA_CNFG4 KORINA_BAR0
#define KORINA_CNFG5 KORINA_BAR1
#define KORINA_CNFG6 KORINA_BAR2
#define KORINA_CNFG7 KORINA_BAR3
#define KORINA_SUBSYS_VENDOR_ID 0x011d
#define KORINA_SUBSYSTEM_ID 0x0214
#define KORINA_CNFG8 0
#define KORINA_CNFG9 0
#define KORINA_CNFG10 0
#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
KORINA_SUBSYSTEM_ID)
#define KORINA_INT_LINE 1
#define KORINA_INT_PIN 1
#define KORINA_MIN_GNT 8
#define KORINA_MAX_LAT 0x38
#define KORINA_CNFG12 0
#define KORINA_CNFG13 0
#define KORINA_CNFG14 0
#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
(KORINA_MIN_GNT<<16) | \
(KORINA_INT_PIN<<8) | \
KORINA_INT_LINE)
#define KORINA_RETRY_LIMIT 0x80
#define KORINA_TRDY_LIMIT 0x80
#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
KORINA_TRDY_LIMIT)
#define PCI_PBAxC_R 0x0
#define PCI_PBAxC_RL 0x1
#define PCI_PBAxC_RM 0x2
#define SIZE_SHFT 2
#if defined(__MIPSEB__)
#define KORINA_PBA0C (PCI_PBAC_MRL | PCI_PBAC_SB | \
((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
PCI_PBAC_PP | \
(SIZE_128MB<<SIZE_SHFT) | \
PCI_PBAC_P)
#else
#define KORINA_PBA0C (PCI_PBAC_MRL | \
((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
PCI_PBAC_PP | \
(SIZE_128MB<<SIZE_SHFT) | \
PCI_PBAC_P)
#endif
#define KORINA_CNFG17 KORINA_PBA0C
#define KORINA_PBA0M 0x0
#define KORINA_CNFG18 KORINA_PBA0M
#if defined(__MIPSEB__)
#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCI_PBAC_SB | \
PCI_PBAC_MSI)
#else
#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
PCI_PBAC_MSI)
#endif
#define KORINA_CNFG19 KORINA_PBA1C
#define KORINA_PBA1M 0x0
#define KORINA_CNFG20 KORINA_PBA1M
#if defined(__MIPSEB__)
#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCI_PBAC_SB | \
PCI_PBAC_MSI)
#else
#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
PCI_PBAC_MSI)
#endif
#define KORINA_CNFG21 KORINA_PBA2C
#define KORINA_PBA2M 0x18000000
#define KORINA_CNFG22 KORINA_PBA2M
#define KORINA_PBA3C 0
#define KORINA_CNFG23 KORINA_PBA3C
#define KORINA_PBA3M 0
#define KORINA_CNFG24 KORINA_PBA3M
#define PCITC_DTIMER_VAL 8
#define PCITC_RTIMER_VAL 0x10
#endif /* __ASM_RC32434_PCI_H */
include/asm-mips/mach-rc32434/prom.h 0 → 100644
View file @ 73b4390f
/*
* Definitions for the PROM
*
* Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
* Copyright 2008 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#define PROM_ENTRY(x) (0xbfc00000 + ((x) * 8))
#define GPIO_INIT_NOBUTTON ""
#define GPIO_INIT_BUTTON " 2"
#define SR_NMI 0x00180000
#define SERIAL_SPEED_ENTRY 0x00000001
#define FREQ_TAG "HZ="
#define GPIO_TAG "gpio="
#define KMAC_TAG "kmac="
#define MEM_TAG "mem="
#define BOARD_TAG "board="
#define BOARD_RB532 "500"
#define BOARD_RB532A "500r5"
include/asm-mips/mach-rc32434/rb.h 0 → 100644
View file @ 73b4390f
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2004 IDT Inc.
* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
*/
#ifndef __ASM_RC32434_RB_H
#define __ASM_RC32434_RB_H
#include <linux/genhd.h>
#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
#define DEV0BASE 0x010000
#define DEV0MASK 0x010004
#define DEV0C 0x010008
#define DEV0T 0x01000C
#define DEV1BASE 0x010010
#define DEV1MASK 0x010014
#define DEV1C 0x010018
#define DEV1TC 0x01001C
#define DEV2BASE 0x010020
#define DEV2MASK 0x010024
#define DEV2C 0x010028
#define DEV2TC 0x01002C
#define DEV3BASE 0x010030
#define DEV3MASK 0x010034
#define DEV3C 0x010038
#define DEV3TC 0x01003C
#define BTCS 0x010040
#define BTCOMPARE 0x010044
#define GPIOBASE 0x050000
#define GPIOCFG 0x050004
#define GPIOD 0x050008
#define GPIOILEVEL 0x05000C
#define GPIOISTAT 0x050010
#define GPIONMIEN 0x050014
#define IMASK6 0x038038
#define LO_WPX (1 << 0)
#define LO_ALE (1 << 1)
#define LO_CLE (1 << 2)
#define LO_CEX (1 << 3)
#define LO_FOFF (1 << 5)
#define LO_SPICS (1 << 6)
#define LO_ULED (1 << 7)
#define BIT_TO_MASK(x) (1 << x)
struct dev_reg {
u32 base;
u32 mask;
u32 ctl;
u32 timing;
};
struct korina_device {
char *name;
unsigned char mac[6];
struct net_device *dev;
};
struct cf_device {
int gpio_pin;
void *dev;
struct gendisk *gd;
};
struct mpmc_device {
unsigned char state;
spinlock_t lock;
void __iomem *base;
};
#endif /* __ASM_RC32434_RB_H */
include/asm-mips/mach-rc32434/rc32434.h 0 → 100644
View file @ 73b4390f
/*
* Definitions for IDT RC323434 CPU.
*/
#ifndef _ASM_RC32434_RC32434_H_
#define _ASM_RC32434_RC32434_H_
#include <linux/delay.h>
#include <linux/io.h>
#define RC32434_REG_BASE 0x18000000
#define RC32434_RST (1 << 15)
#define IDT_CLOCK_MULT 2
#define MIPS_CPU_TIMER_IRQ 7
/* Interrupt Controller */
#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
#define IC_GROUP_OFFSET 0x0C
#define NUM_INTR_GROUPS 5
/* 16550 UARTs */
#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
/* GRP3 IRQ numbers start here */
#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32)
/* GRP4 IRQ numbers start here */
#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32)
/* GRP5 IRQ numbers start here */
#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32)
#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
#ifdef __MIPSEB__
#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
#else
#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
#endif
#define RC32434_UART0_IRQ (GROUP3_IRQ_BASE + 0)
/* cpu pipeline flush */
static inline void rc32434_sync(void)
{
__asm__ volatile ("sync");
}
static inline void rc32434_sync_udelay(int us)
{
__asm__ volatile ("sync");
udelay(us);
}
static inline void rc32434_sync_delay(int ms)
{
__asm__ volatile ("sync");
mdelay(ms);
}
#endif /* _ASM_RC32434_RC32434_H_ */
include/asm-mips/mach-rc32434/timer.h 0 → 100644
View file @ 73b4390f
/*
* Definitions for timer registers
*
* Copyright 2004 Philip Rischel <rischelp@idt.com>
* Copyright 2008 Florian Fainelli <florian@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __ASM_RC32434_TIMER_H
#define __ASM_RC32434_TIMER_H
#include <asm/mach-rc32434/rb.h>
#define TIMER0_BASE_ADDR 0x18028000
#define TIMER_COUNT 3
struct timer_counter {
u32 count;
u32 compare;
u32 ctc; /*use CTC_ */
};
struct timer {
struct timer_counter tim[TIMER_COUNT];
u32 rcount; /* use RCOUNT_ */
u32 rcompare; /* use RCOMPARE_ */
u32 rtc; /* use RTC_ */
};
#define RC32434_CTC_EN_BIT 0
#define RC32434_CTC_TO_BIT 1
/* Real time clock registers */
#define RC32434_RTC_MSK(x) BIT_TO_MASK(x)
#define RC32434_RTC_CE_BIT 0
#define RC32434_RTC_TO_BIT 1
#define RC32434_RTC_RQE_BIT 2
/* Counter registers */
#define RC32434_RCOUNT_BIT 0
#define RC32434_RCOUNT_MSK 0x0000ffff
#define RC32434_RCOMP_BIT 0
#define RC32434_RCOMP_MSK 0x0000ffff
#endif /* __ASM_RC32434_TIMER_H */
include/asm-mips/mach-rc32434/war.h 0 → 100644
View file @ 73b4390f
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
#define __ASM_MIPS_MACH_MIPS_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 1
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define RM9000_CDEX_SMP_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
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