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Commit 751e29bb authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
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ARM: dts: r8a7779: Use SYSC "always-on" PM Domain 

Hook up all devices that are part of the CPG/MSTP Clock Domain to the
SYSC "always-on" PM Domain, for a more consistent device-power-area
description in DT.
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 0761ff2a
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Showing with 22 additions and 22 deletions
arch/arm/boot/dts/r8a7779.dtsi
View file @ 751e29bb
...@@ -177,7 +177,7 @@ i2c0: i2c@ffc70000 { ...@@ -177,7 +177,7 @@ i2c0: i2c@ffc70000 {
reg = <0xffc70000 0x1000>; reg = <0xffc70000 0x1000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C0>; clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -188,7 +188,7 @@ i2c1: i2c@ffc71000 { ...@@ -188,7 +188,7 @@ i2c1: i2c@ffc71000 {
reg = <0xffc71000 0x1000>; reg = <0xffc71000 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C1>; clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -199,7 +199,7 @@ i2c2: i2c@ffc72000 { ...@@ -199,7 +199,7 @@ i2c2: i2c@ffc72000 {
reg = <0xffc72000 0x1000>; reg = <0xffc72000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C2>; clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -210,7 +210,7 @@ i2c3: i2c@ffc73000 { ...@@ -210,7 +210,7 @@ i2c3: i2c@ffc73000 {
reg = <0xffc73000 0x1000>; reg = <0xffc73000 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C3>; clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -222,7 +222,7 @@ scif0: serial@ffe40000 { ...@@ -222,7 +222,7 @@ scif0: serial@ffe40000 {
clocks = <&mstp0_clks R8A7779_CLK_SCIF0>, clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -234,7 +234,7 @@ scif1: serial@ffe41000 { ...@@ -234,7 +234,7 @@ scif1: serial@ffe41000 {
clocks = <&mstp0_clks R8A7779_CLK_SCIF1>, clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -246,7 +246,7 @@ scif2: serial@ffe42000 { ...@@ -246,7 +246,7 @@ scif2: serial@ffe42000 {
clocks = <&mstp0_clks R8A7779_CLK_SCIF2>, clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -258,7 +258,7 @@ scif3: serial@ffe43000 { ...@@ -258,7 +258,7 @@ scif3: serial@ffe43000 {
clocks = <&mstp0_clks R8A7779_CLK_SCIF3>, clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -270,7 +270,7 @@ scif4: serial@ffe44000 { ...@@ -270,7 +270,7 @@ scif4: serial@ffe44000 {
clocks = <&mstp0_clks R8A7779_CLK_SCIF4>, clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -282,7 +282,7 @@ scif5: serial@ffe45000 { ...@@ -282,7 +282,7 @@ scif5: serial@ffe45000 {
clocks = <&mstp0_clks R8A7779_CLK_SCIF5>, clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -304,7 +304,7 @@ tmu0: timer@ffd80000 { ...@@ -304,7 +304,7 @@ tmu0: timer@ffd80000 {
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU0>; clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#renesas,channels = <3>; #renesas,channels = <3>;
...@@ -319,7 +319,7 @@ tmu1: timer@ffd81000 { ...@@ -319,7 +319,7 @@ tmu1: timer@ffd81000 {
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU1>; clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#renesas,channels = <3>; #renesas,channels = <3>;
...@@ -334,7 +334,7 @@ tmu2: timer@ffd82000 { ...@@ -334,7 +334,7 @@ tmu2: timer@ffd82000 {
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU2>; clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
#renesas,channels = <3>; #renesas,channels = <3>;
...@@ -346,7 +346,7 @@ sata: sata@fc600000 { ...@@ -346,7 +346,7 @@ sata: sata@fc600000 {
reg = <0xfc600000 0x2000>; reg = <0xfc600000 0x2000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_SATA>; clocks = <&mstp1_clks R8A7779_CLK_SATA>;
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
}; };
sdhi0: sd@ffe4c000 { sdhi0: sd@ffe4c000 {
...@@ -354,7 +354,7 @@ sdhi0: sd@ffe4c000 { ...@@ -354,7 +354,7 @@ sdhi0: sd@ffe4c000 {
reg = <0xffe4c000 0x100>; reg = <0xffe4c000 0x100>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -363,7 +363,7 @@ sdhi1: sd@ffe4d000 { ...@@ -363,7 +363,7 @@ sdhi1: sd@ffe4d000 {
reg = <0xffe4d000 0x100>; reg = <0xffe4d000 0x100>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -372,7 +372,7 @@ sdhi2: sd@ffe4e000 { ...@@ -372,7 +372,7 @@ sdhi2: sd@ffe4e000 {
reg = <0xffe4e000 0x100>; reg = <0xffe4e000 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -381,7 +381,7 @@ sdhi3: sd@ffe4f000 { ...@@ -381,7 +381,7 @@ sdhi3: sd@ffe4f000 {
reg = <0xffe4f000 0x100>; reg = <0xffe4f000 0x100>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -392,7 +392,7 @@ hspi0: spi@fffc7000 { ...@@ -392,7 +392,7 @@ hspi0: spi@fffc7000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -403,7 +403,7 @@ hspi1: spi@fffc8000 { ...@@ -403,7 +403,7 @@ hspi1: spi@fffc8000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -414,7 +414,7 @@ hspi2: spi@fffc6000 { ...@@ -414,7 +414,7 @@ hspi2: spi@fffc6000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
}; };
...@@ -423,7 +423,7 @@ du: display@fff80000 { ...@@ -423,7 +423,7 @@ du: display@fff80000 {
reg = <0 0xfff80000 0 0x40000>; reg = <0 0xfff80000 0 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_DU>; clocks = <&mstp1_clks R8A7779_CLK_DU>;
power-domains = <&cpg_clocks>; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled"; status = "disabled";
ports { ports {
......
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