Commit 768db0b9 authored by Stephen Warren's avatar Stephen Warren

ASoC: tegra: call pm_runtime APIs around register accesses

Call pm_runtime_get_sync() before all register accesses; the HW requires
clocks to be running when accessing registers.

This hasn't been needed to date, since all register IO was performed
while playback was active, and hence the ASoC core had already called
pm_runtime_get(). However, an imminent future commit will allocate and
set up the FIFOs and routing during probe(), when that "protection"
won't be in place.
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
Acked-by: default avatarMark Brown <broonie@linaro.org>
parent 5185e0ac
...@@ -114,6 +114,8 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, ...@@ -114,6 +114,8 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
(channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE); (channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE);
*reqsel = ahub->dma_sel + channel; *reqsel = ahub->dma_sel + channel;
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_CHANNEL_CTRL + reg = TEGRA30_AHUB_CHANNEL_CTRL +
(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
val = tegra30_apbif_read(reg); val = tegra30_apbif_read(reg);
...@@ -140,6 +142,8 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, ...@@ -140,6 +142,8 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
(channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE); (channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE);
ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);
pm_runtime_put(ahub->dev);
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo); EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo);
...@@ -149,12 +153,16 @@ int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif) ...@@ -149,12 +153,16 @@ int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
int reg, val; int reg, val;
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_CHANNEL_CTRL + reg = TEGRA30_AHUB_CHANNEL_CTRL +
(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
val = tegra30_apbif_read(reg); val = tegra30_apbif_read(reg);
val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN; val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
tegra30_apbif_write(reg, val); tegra30_apbif_write(reg, val);
pm_runtime_put(ahub->dev);
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo); EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo);
...@@ -164,12 +172,16 @@ int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif) ...@@ -164,12 +172,16 @@ int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
int reg, val; int reg, val;
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_CHANNEL_CTRL + reg = TEGRA30_AHUB_CHANNEL_CTRL +
(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
val = tegra30_apbif_read(reg); val = tegra30_apbif_read(reg);
val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN; val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
tegra30_apbif_write(reg, val); tegra30_apbif_write(reg, val);
pm_runtime_put(ahub->dev);
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo); EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo);
...@@ -204,6 +216,8 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, ...@@ -204,6 +216,8 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
(channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE); (channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE);
*reqsel = ahub->dma_sel + channel; *reqsel = ahub->dma_sel + channel;
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_CHANNEL_CTRL + reg = TEGRA30_AHUB_CHANNEL_CTRL +
(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
val = tegra30_apbif_read(reg); val = tegra30_apbif_read(reg);
...@@ -230,6 +244,8 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, ...@@ -230,6 +244,8 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
(channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE); (channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE);
ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);
pm_runtime_put(ahub->dev);
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo); EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo);
...@@ -239,12 +255,16 @@ int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif) ...@@ -239,12 +255,16 @@ int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif)
int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
int reg, val; int reg, val;
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_CHANNEL_CTRL + reg = TEGRA30_AHUB_CHANNEL_CTRL +
(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
val = tegra30_apbif_read(reg); val = tegra30_apbif_read(reg);
val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN; val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
tegra30_apbif_write(reg, val); tegra30_apbif_write(reg, val);
pm_runtime_put(ahub->dev);
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo); EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo);
...@@ -254,12 +274,16 @@ int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif) ...@@ -254,12 +274,16 @@ int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif)
int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
int reg, val; int reg, val;
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_CHANNEL_CTRL + reg = TEGRA30_AHUB_CHANNEL_CTRL +
(channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
val = tegra30_apbif_read(reg); val = tegra30_apbif_read(reg);
val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN; val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
tegra30_apbif_write(reg, val); tegra30_apbif_write(reg, val);
pm_runtime_put(ahub->dev);
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo); EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo);
...@@ -280,10 +304,14 @@ int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif, ...@@ -280,10 +304,14 @@ int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
int reg; int reg;
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_AUDIO_RX + reg = TEGRA30_AHUB_AUDIO_RX +
(channel * TEGRA30_AHUB_AUDIO_RX_STRIDE); (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
tegra30_audio_write(reg, 1 << txcif); tegra30_audio_write(reg, 1 << txcif);
pm_runtime_put(ahub->dev);
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source); EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source);
...@@ -293,10 +321,14 @@ int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif) ...@@ -293,10 +321,14 @@ int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif)
int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
int reg; int reg;
pm_runtime_get_sync(ahub->dev);
reg = TEGRA30_AHUB_AUDIO_RX + reg = TEGRA30_AHUB_AUDIO_RX +
(channel * TEGRA30_AHUB_AUDIO_RX_STRIDE); (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
tegra30_audio_write(reg, 0); tegra30_audio_write(reg, 0);
pm_runtime_put(ahub->dev);
return 0; return 0;
} }
EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source); EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source);
......
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