Commit 76e7b902 authored by Neil Brown's avatar Neil Brown Committed by Linus Torvalds

[PATCH] Micro Memory battery backed RAM card driver

New driver for Micro Memory NVRAM module

This driver handles up to 16 PCI based NVRAM cards
from MicroMemory.
Each card appears like a block device, and can be partitioned
using any standard partitioning tool.  Upto 15 partitions are
supported.

This driver needs its own major device number and so allocates
one using register_blkdev.
parent 096cbcc6
......@@ -90,6 +90,24 @@ CONFIG_BLK_DEV_LOOP
Most users will answer N here.
Micro Memory MM5415 Battery Backed RAM support (EXPERIMENTAL)
CONFIG_BLK_DEV_UMEM
Saying Y here will include support for the MM5415 family of
battery backed (Non-volatile) RAM cards.
http://www.umem.com/
The cards appear as block devices that can be partitioned into
as many as 15 partitions.
If you want to compile this driver as a module ( = code which can be
inserted in and removed from the running kernel whenever you want),
say M here and read Documentation/modules.txt. The module will be
called umem.o.
The umem driver has not yet been allocated a MAJOR number, so
one is chosen dynamically. Use "devfs" or look in /proc/devices
for the device number
CONFIG_BLK_DEV_NBD
Saying Y here will allow your computer to be a client for network
block devices, i.e. it will be able to use block devices exported by
......
......@@ -37,6 +37,7 @@ dep_tristate 'Compaq SMART2 support' CONFIG_BLK_CPQ_DA $CONFIG_PCI
dep_tristate 'Compaq Smart Array 5xxx support' CONFIG_BLK_CPQ_CISS_DA $CONFIG_PCI
dep_mbool ' SCSI tape drive support for Smart Array 5xxx' CONFIG_CISS_SCSI_TAPE $CONFIG_BLK_CPQ_CISS_DA $CONFIG_SCSI
dep_tristate 'Mylex DAC960/DAC1100 PCI RAID Controller support' CONFIG_BLK_DEV_DAC960 $CONFIG_PCI
dep_tristate 'Micro Memory MM5415 Battery Backed RAM support' CONFIG_BLK_DEV_UMEM $CONFIG_PCI $CONFIG_EXPERIMENTAL
tristate 'Loopback device support' CONFIG_BLK_DEV_LOOP
dep_tristate 'Network block device support' CONFIG_BLK_DEV_NBD $CONFIG_NET
......
......@@ -30,6 +30,7 @@ obj-$(CONFIG_BLK_CPQ_DA) += cpqarray.o
obj-$(CONFIG_BLK_CPQ_CISS_DA) += cciss.o
obj-$(CONFIG_BLK_DEV_DAC960) += DAC960.o
obj-$(CONFIG_BLK_DEV_UMEM) += umem.o
obj-$(CONFIG_BLK_DEV_NBD) += nbd.o
subdir-$(CONFIG_PARIDE) += paride
......
This diff is collapsed.
/*
* This file contains defines for the
* Micro Memory MM5415
* family PCI Memory Module with Battery Backup.
*
* Copyright Micro Memory INC 2001. All rights reserved.
* Release under the terms of the GNU GENERAL PUBLIC LICENSE version 2.
* See the file COPYING.
*/
#ifndef _DRIVERS_BLOCK_MM_H
#define _DRIVERS_BLOCK_MM_H
#define IRQ_TIMEOUT (1 * HZ)
/* CSR register definition */
#define MEMCTRLSTATUS_MAGIC 0x00
#define MM_MAGIC_VALUE (unsigned char)0x59
#define MEMCTRLSTATUS_BATTERY 0x04
#define BATTERY_1_DISABLED 0x01
#define BATTERY_1_FAILURE 0x02
#define BATTERY_2_DISABLED 0x04
#define BATTERY_2_FAILURE 0x08
#define MEMCTRLSTATUS_MEMORY 0x07
#define MEM_128_MB 0xfe
#define MEM_256_MB 0xfc
#define MEM_512_MB 0xf8
#define MEM_1_GB 0xf0
#define MEM_2_GB 0xe0
#define MEMCTRLCMD_LEDCTRL 0x08
#define LED_REMOVE 2
#define LED_FAULT 4
#define LED_POWER 6
#define LED_FLIP 255
#define LED_OFF 0x00
#define LED_ON 0x01
#define LED_FLASH_3_5 0x02
#define LED_FLASH_7_0 0x03
#define LED_POWER_ON 0x00
#define LED_POWER_OFF 0x01
#define USER_BIT1 0x01
#define USER_BIT2 0x02
#define MEMORY_INITIALIZED USER_BIT1
#define MEMCTRLCMD_ERRCTRL 0x0C
#define EDC_NONE_DEFAULT 0x00
#define EDC_NONE 0x01
#define EDC_STORE_READ 0x02
#define EDC_STORE_CORRECT 0x03
#define MEMCTRLCMD_ERRCNT 0x0D
#define MEMCTRLCMD_ERRSTATUS 0x0E
#define ERROR_DATA_LOG 0x20
#define ERROR_ADDR_LOG 0x28
#define ERROR_COUNT 0x3D
#define ERROR_SYNDROME 0x3E
#define ERROR_CHECK 0x3F
#define DMA_PCI_ADDR 0x40
#define DMA_LOCAL_ADDR 0x48
#define DMA_TRANSFER_SIZE 0x50
#define DMA_DESCRIPTOR_ADDR 0x58
#define DMA_SEMAPHORE_ADDR 0x60
#define DMA_STATUS_CTRL 0x68
#define DMASCR_GO 0x00001
#define DMASCR_TRANSFER_READ 0x00002
#define DMASCR_CHAIN_EN 0x00004
#define DMASCR_SEM_EN 0x00010
#define DMASCR_DMA_COMP_EN 0x00020
#define DMASCR_CHAIN_COMP_EN 0x00040
#define DMASCR_ERR_INT_EN 0x00080
#define DMASCR_PARITY_INT_EN 0x00100
#define DMASCR_ANY_ERR 0x00800
#define DMASCR_MBE_ERR 0x01000
#define DMASCR_PARITY_ERR_REP 0x02000
#define DMASCR_PARITY_ERR_DET 0x04000
#define DMASCR_SYSTEM_ERR_SIG 0x08000
#define DMASCR_TARGET_ABT 0x10000
#define DMASCR_MASTER_ABT 0x20000
#define DMASCR_DMA_COMPLETE 0x40000
#define DMASCR_CHAIN_COMPLETE 0x80000
/*
3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE
READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA
TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE
TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS
(31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6,
AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING
DMA READ OPERATIONS.
*/
#define DMASCR_READ 0x60000000
#define DMASCR_READLINE 0xE0000000
#define DMASCR_READMULTI 0xC0000000
#define DMASCR_ERROR_MASK (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR | DMASCR_ANY_ERR)
#define DMASCR_HARD_ERROR (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR)
#define WINDOWMAP_WINNUM 0x7B
#define DMA_READ_FROM_HOST 0
#define DMA_WRITE_TO_HOST 1
struct mm_dma_desc {
u64 pci_addr;
u64 local_addr;
u32 transfer_size;
u32 zero1;
u64 next_desc_addr;
u64 sem_addr;
u32 control_bits;
u32 zero2;
dma_addr_t data_dma_handle;
/* Copy of the bits */
u64 sem_control_bits;
} __attribute__((aligned(8)));
#define PCI_VENDOR_ID_MICRO_MEMORY 0x1332
#define PCI_DEVICE_ID_MICRO_MEMORY_5415CN 0x5415
#endif
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