Commit 76f0f1f3 authored by David Mosberger's avatar David Mosberger

Merge tiger.hpl.hp.com:/data1/bk/vanilla/linux-2.5

into tiger.hpl.hp.com:/data1/bk/lia64/to-linus-2.5
parents e6d19c6a 86d6792a
...@@ -400,7 +400,7 @@ CONFIG_ITANIUM ...@@ -400,7 +400,7 @@ CONFIG_ITANIUM
Select your IA64 processor type. The default is Intel Itanium. Select your IA64 processor type. The default is Intel Itanium.
CONFIG_MCKINLEY CONFIG_MCKINLEY
Select this to configure for a McKinley processor. Select this to configure for an Itanium 2 (McKinley) processor.
CONFIG_IA64_GENERIC CONFIG_IA64_GENERIC
This selects the system type of your hardware. A "generic" kernel This selects the system type of your hardware. A "generic" kernel
......
...@@ -69,13 +69,6 @@ ifdef CONFIG_IA64_SGI_SN ...@@ -69,13 +69,6 @@ ifdef CONFIG_IA64_SGI_SN
$(CORE_FILES) $(CORE_FILES)
endif endif
ifdef CONFIG_IA64_SOFTSDV
SUBDIRS := arch/$(ARCH)/dig \
$(SUBDIRS)
CORE_FILES := arch/$(ARCH)/dig/dig.a \
$(CORE_FILES)
endif
ifdef CONFIG_IA64_DIG ifdef CONFIG_IA64_DIG
SUBDIRS := arch/$(ARCH)/dig \ SUBDIRS := arch/$(ARCH)/dig \
$(SUBDIRS) $(SUBDIRS)
......
...@@ -16,7 +16,7 @@ define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n ...@@ -16,7 +16,7 @@ define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
choice 'IA-64 processor type' \ choice 'IA-64 processor type' \
"Itanium CONFIG_ITANIUM \ "Itanium CONFIG_ITANIUM \
McKinley CONFIG_MCKINLEY" Itanium Itanium-2 CONFIG_MCKINLEY" Itanium
choice 'IA-64 system type' \ choice 'IA-64 system type' \
"generic CONFIG_IA64_GENERIC \ "generic CONFIG_IA64_GENERIC \
...@@ -26,11 +26,18 @@ choice 'IA-64 system type' \ ...@@ -26,11 +26,18 @@ choice 'IA-64 system type' \
SGI-SN1 CONFIG_IA64_SGI_SN1 \ SGI-SN1 CONFIG_IA64_SGI_SN1 \
SGI-SN2 CONFIG_IA64_SGI_SN2" generic SGI-SN2 CONFIG_IA64_SGI_SN2" generic
choice 'Kernel page size' \ if [ "$CONFIG_ITANIUM" = "y" ]; then
choice 'Kernel page size' \
"4KB CONFIG_IA64_PAGE_SIZE_4KB \
8KB CONFIG_IA64_PAGE_SIZE_8KB \
16KB CONFIG_IA64_PAGE_SIZE_16KB" 16KB
else
choice 'Kernel page size' \
"4KB CONFIG_IA64_PAGE_SIZE_4KB \ "4KB CONFIG_IA64_PAGE_SIZE_4KB \
8KB CONFIG_IA64_PAGE_SIZE_8KB \ 8KB CONFIG_IA64_PAGE_SIZE_8KB \
16KB CONFIG_IA64_PAGE_SIZE_16KB \ 16KB CONFIG_IA64_PAGE_SIZE_16KB \
64KB CONFIG_IA64_PAGE_SIZE_64KB" 16KB 64KB CONFIG_IA64_PAGE_SIZE_64KB" 16KB
endif
if [ "$CONFIG_IA64_HP_SIM" = "n" ]; then if [ "$CONFIG_IA64_HP_SIM" = "n" ]; then
define_bool CONFIG_ACPI y define_bool CONFIG_ACPI y
......
...@@ -12,17 +12,3 @@ export-objs := sba_iommu.o ...@@ -12,17 +12,3 @@ export-objs := sba_iommu.o
obj-y := sba_iommu.o obj-y := sba_iommu.o
include $(TOPDIR)/Rules.make include $(TOPDIR)/Rules.make
#
# ia64/platform/hp/common/Makefile
#
# Copyright (C) 2002 Hewlett Packard
# Copyright (C) Alex Williamson (alex_williamson@hp.com)
#
O_TARGET := common.o
export-objs := sba_iommu.o
obj-y := sba_iommu.o
include $(TOPDIR)/Rules.make
...@@ -1389,6 +1389,12 @@ sba_dma_address (struct scatterlist *sg) ...@@ -1389,6 +1389,12 @@ sba_dma_address (struct scatterlist *sg)
return ((unsigned long)sba_sg_iova(sg)); return ((unsigned long)sba_sg_iova(sg));
} }
int
sba_dma_supported (struct pci_dev *dev, u64 mask)
{
return 1;
}
/************************************************************** /**************************************************************
* *
* Initialization and claim * Initialization and claim
...@@ -1858,5 +1864,6 @@ EXPORT_SYMBOL(sba_unmap_single); ...@@ -1858,5 +1864,6 @@ EXPORT_SYMBOL(sba_unmap_single);
EXPORT_SYMBOL(sba_map_sg); EXPORT_SYMBOL(sba_map_sg);
EXPORT_SYMBOL(sba_unmap_sg); EXPORT_SYMBOL(sba_unmap_sg);
EXPORT_SYMBOL(sba_dma_address); EXPORT_SYMBOL(sba_dma_address);
EXPORT_SYMBOL(sba_dma_supported);
EXPORT_SYMBOL(sba_alloc_consistent); EXPORT_SYMBOL(sba_alloc_consistent);
EXPORT_SYMBOL(sba_free_consistent); EXPORT_SYMBOL(sba_free_consistent);
...@@ -7,9 +7,9 @@ ...@@ -7,9 +7,9 @@
* case means sys_sim.c console (goes via the simulator). The code hereafter * case means sys_sim.c console (goes via the simulator). The code hereafter
* is completely leveraged from the serial.c driver. * is completely leveraged from the serial.c driver.
* *
* Copyright (C) 1999-2000 Hewlett-Packard Co * Copyright (C) 1999-2000, 2002 Hewlett-Packard Co
* Copyright (C) 1999 Stephane Eranian <eranian@hpl.hp.com> * Stephane Eranian <eranian@hpl.hp.com>
* Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com> * David Mosberger-Tang <davidm@hpl.hp.com>
* *
* 02/04/00 D. Mosberger Merged in serial.c bug fixes in rs_close(). * 02/04/00 D. Mosberger Merged in serial.c bug fixes in rs_close().
* 02/25/00 D. Mosberger Synced up with 2.3.99pre-5 version of serial.c. * 02/25/00 D. Mosberger Synced up with 2.3.99pre-5 version of serial.c.
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#include <linux/major.h> #include <linux/major.h>
#include <linux/fcntl.h> #include <linux/fcntl.h>
#include <linux/mm.h> #include <linux/mm.h>
#include <linux/malloc.h> #include <linux/slab.h>
#include <linux/console.h> #include <linux/console.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/serial.h> #include <linux/serial.h>
......
...@@ -11,16 +11,3 @@ obj-y := hpzx1_misc.o ...@@ -11,16 +11,3 @@ obj-y := hpzx1_misc.o
obj-$(CONFIG_IA64_GENERIC) += hpzx1_machvec.o obj-$(CONFIG_IA64_GENERIC) += hpzx1_machvec.o
include $(TOPDIR)/Rules.make include $(TOPDIR)/Rules.make
#
# ia64/platform/hp/zx1/Makefile
#
# Copyright (C) 2002 Hewlett Packard
# Copyright (C) Alex Williamson (alex_williamson@hp.com)
#
O_TARGET := zx1.o
obj-y := hpzx1_misc.o
obj-$(CONFIG_IA64_GENERIC) += hpzx1_machvec.o
include $(TOPDIR)/Rules.make
This diff is collapsed.
...@@ -660,10 +660,10 @@ acpi_get_prt (struct pci_vector_struct **vectors, int *count) ...@@ -660,10 +660,10 @@ acpi_get_prt (struct pci_vector_struct **vectors, int *count)
list_for_each(node, &acpi_prts.entries) { list_for_each(node, &acpi_prts.entries) {
entry = (struct acpi_prt_entry *)node; entry = (struct acpi_prt_entry *)node;
vector[i].bus = (u16) entry->id.bus; vector[i].bus = entry->id.bus;
vector[i].pci_id = (u32) entry->id.dev << 16 | 0xffff; vector[i].pci_id = ((u32) entry->id.dev) << 16 | 0xffff;
vector[i].pin = (u8) entry->id.pin; vector[i].pin = entry->id.pin;
vector[i].irq = (u8) entry->source.index; vector[i].irq = entry->source.index;
i++; i++;
} }
*count = acpi_prts.count; *count = acpi_prts.count;
......
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
* *
* Copyright (C) 1999 VA Linux Systems * Copyright (C) 1999 VA Linux Systems
* Copyright (C) 1999 Walt Drummond <drummond@valinux.com> * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
* Copyright (C) 1999-2001 Hewlett-Packard Co. * Copyright (C) 1999-2002 Hewlett-Packard Co.
* David Mosberger-Tang <davidm@hpl.hp.com> * David Mosberger-Tang <davidm@hpl.hp.com>
* Stephane Eranian <eranian@hpl.hp.com> * Stephane Eranian <eranian@hpl.hp.com>
* *
...@@ -212,8 +212,8 @@ efi_map_pal_code (void) ...@@ -212,8 +212,8 @@ efi_map_pal_code (void)
void *efi_map_start, *efi_map_end, *p; void *efi_map_start, *efi_map_end, *p;
efi_memory_desc_t *md; efi_memory_desc_t *md;
u64 efi_desc_size; u64 efi_desc_size;
int pal_code_count=0; int pal_code_count = 0;
u64 mask, flags; u64 mask, psr;
u64 vaddr; u64 vaddr;
efi_map_start = __va(ia64_boot_param->efi_memmap); efi_map_start = __va(ia64_boot_param->efi_memmap);
...@@ -266,10 +266,10 @@ efi_map_pal_code (void) ...@@ -266,10 +266,10 @@ efi_map_pal_code (void)
/* /*
* Cannot write to CRx with PSR.ic=1 * Cannot write to CRx with PSR.ic=1
*/ */
ia64_clear_ic(flags); psr = ia64_clear_ic();
ia64_itr(0x1, IA64_TR_PALCODE, vaddr & mask, ia64_itr(0x1, IA64_TR_PALCODE, vaddr & mask,
pte_val(pfn_pte(md->phys_addr >> PAGE_SHIFT, PAGE_KERNEL)), IA64_GRANULE_SHIFT); pte_val(pfn_pte(md->phys_addr >> PAGE_SHIFT, PAGE_KERNEL)), IA64_GRANULE_SHIFT);
local_irq_restore(flags); ia64_set_psr(psr);
ia64_srlz_i(); ia64_srlz_i();
} }
} }
...@@ -485,7 +485,7 @@ efi_get_iobase (void) ...@@ -485,7 +485,7 @@ efi_get_iobase (void)
} }
u32 u32
efi_mem_type (u64 phys_addr) efi_mem_type (unsigned long phys_addr)
{ {
void *efi_map_start, *efi_map_end, *p; void *efi_map_start, *efi_map_end, *p;
efi_memory_desc_t *md; efi_memory_desc_t *md;
...@@ -506,7 +506,7 @@ efi_mem_type (u64 phys_addr) ...@@ -506,7 +506,7 @@ efi_mem_type (u64 phys_addr)
} }
u64 u64
efi_mem_attributes (u64 phys_addr) efi_mem_attributes (unsigned long phys_addr)
{ {
void *efi_map_start, *efi_map_end, *p; void *efi_map_start, *efi_map_end, *p;
efi_memory_desc_t *md; efi_memory_desc_t *md;
......
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
#include <asm/unistd.h> #include <asm/unistd.h>
#include <asm/page.h> #include <asm/page.h>
.section .text.gate,"ax" .section .text.gate, "ax"
# define ARG0_OFF (16 + IA64_SIGFRAME_ARG0_OFFSET) # define ARG0_OFF (16 + IA64_SIGFRAME_ARG0_OFFSET)
# define ARG1_OFF (16 + IA64_SIGFRAME_ARG1_OFFSET) # define ARG1_OFF (16 + IA64_SIGFRAME_ARG1_OFFSET)
...@@ -108,7 +108,7 @@ back_from_setup_rbs: ...@@ -108,7 +108,7 @@ back_from_setup_rbs:
dep r8=0,r8,38,26 // clear EC0, CPL0 and reserved bits dep r8=0,r8,38,26 // clear EC0, CPL0 and reserved bits
adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp
;; ;;
.spillsp ar.pfs, CFM_OFF .spillsp ar.pfs, CFM_OFF+SIGCONTEXT_OFF
st8 [base0]=r8 // save CFM0 st8 [base0]=r8 // save CFM0
adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp
;; ;;
......
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
* /proc/irq/#/smp_affinity * /proc/irq/#/smp_affinity
* 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing. * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
* 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
* 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to IOSAPIC mapping error
*/ */
/* /*
* Here is what the interrupt logic between a PCI device and the CPU looks like: * Here is what the interrupt logic between a PCI device and the CPU looks like:
...@@ -112,7 +113,7 @@ find_iosapic (unsigned int irq) ...@@ -112,7 +113,7 @@ find_iosapic (unsigned int irq)
int i; int i;
for (i = 0; i < num_iosapic; i++) { for (i = 0; i < num_iosapic; i++) {
if ((irq - iosapic_lists[i].base_irq) < iosapic_lists[i].max_pin) if ((unsigned) (irq - iosapic_lists[i].base_irq) <= iosapic_lists[i].max_pin)
return i; return i;
} }
...@@ -138,7 +139,7 @@ iosapic_irq_to_vector (int irq) ...@@ -138,7 +139,7 @@ iosapic_irq_to_vector (int irq)
* Map PCI pin to the corresponding IA-64 interrupt vector. If no such mapping exists, * Map PCI pin to the corresponding IA-64 interrupt vector. If no such mapping exists,
* return -1. * return -1.
*/ */
static int int
pci_pin_to_vector (int bus, int slot, int pci_pin) pci_pin_to_vector (int bus, int slot, int pci_pin)
{ {
struct pci_vector_struct *r; struct pci_vector_struct *r;
......
...@@ -1197,7 +1197,7 @@ static void register_irq_proc (unsigned int irq) ...@@ -1197,7 +1197,7 @@ static void register_irq_proc (unsigned int irq)
{ {
char name [MAX_NAMELEN]; char name [MAX_NAMELEN];
if (!root_irq_dir || (irq_desc(irq)->handler == &no_irq_type)) if (!root_irq_dir || (irq_desc(irq)->handler == &no_irq_type) || irq_dir[irq])
return; return;
memset(name, 0, MAX_NAMELEN); memset(name, 0, MAX_NAMELEN);
......
...@@ -199,8 +199,10 @@ ia64_save_extra (struct task_struct *task) ...@@ -199,8 +199,10 @@ ia64_save_extra (struct task_struct *task)
# endif # endif
#endif #endif
#ifdef CONFIG_IA32_SUPPORT
if (IS_IA32_PROCESS(ia64_task_regs(task))) if (IS_IA32_PROCESS(ia64_task_regs(task)))
ia32_save_state(task); ia32_save_state(task);
#endif
} }
void void
...@@ -218,8 +220,10 @@ ia64_load_extra (struct task_struct *task) ...@@ -218,8 +220,10 @@ ia64_load_extra (struct task_struct *task)
# endif # endif
#endif #endif
#ifdef CONFIG_IA32_SUPPORT
if (IS_IA32_PROCESS(ia64_task_regs(task))) if (IS_IA32_PROCESS(ia64_task_regs(task)))
ia32_load_state(task); ia32_load_state(task);
#endif
} }
/* /*
......
...@@ -559,6 +559,24 @@ cpu_init (void) ...@@ -559,6 +559,24 @@ cpu_init (void)
*/ */
identify_cpu(my_cpu_info); identify_cpu(my_cpu_info);
#ifdef CONFIG_MCKINLEY
{
#define FEATURE_SET 16
struct ia64_pal_retval iprv;
if (my_cpu_data->family == 0x1f) {
PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80)) {
PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
(iprv.v1 | 0x80), FEATURE_SET, 0);
}
}
}
#endif
/* Clear the stack memory reserved for pt_regs: */ /* Clear the stack memory reserved for pt_regs: */
memset(ia64_task_regs(current), 0, sizeof(struct pt_regs)); memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));
...@@ -570,7 +588,7 @@ cpu_init (void) ...@@ -570,7 +588,7 @@ cpu_init (void)
* shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
* be fine). * be fine).
*/ */
ia64_set_dcr( IA64_DCR_DM | IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR ia64_set_dcr( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
| IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC); | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC);
#ifndef CONFIG_SMP #ifndef CONFIG_SMP
ia64_set_fpu_owner(0); ia64_set_fpu_owner(0);
......
...@@ -143,9 +143,10 @@ copy_siginfo_to_user (siginfo_t *to, siginfo_t *from) ...@@ -143,9 +143,10 @@ copy_siginfo_to_user (siginfo_t *to, siginfo_t *from)
{ {
if (!access_ok(VERIFY_WRITE, to, sizeof(siginfo_t))) if (!access_ok(VERIFY_WRITE, to, sizeof(siginfo_t)))
return -EFAULT; return -EFAULT;
if (from->si_code < 0) if (from->si_code < 0) {
return __copy_to_user(to, from, sizeof(siginfo_t)); if (__copy_to_user(to, from, sizeof(siginfo_t)))
else { return -EFAULT;
} else {
int err; int err;
/* /*
......
...@@ -478,6 +478,17 @@ swiotlb_dma_address (struct scatterlist *sg) ...@@ -478,6 +478,17 @@ swiotlb_dma_address (struct scatterlist *sg)
return SG_ENT_PHYS_ADDRESS(sg); return SG_ENT_PHYS_ADDRESS(sg);
} }
/*
* Return whether the given PCI device DMA address mask can be supported properly. For
* example, if your device can only drive the low 24-bits during PCI bus mastering, then
* you would pass 0x00ffffff as the mask to this function.
*/
int
swiotlb_pci_dma_supported (struct pci_dev *hwdev, u64 mask)
{
return 1;
}
EXPORT_SYMBOL(swiotlb_init); EXPORT_SYMBOL(swiotlb_init);
EXPORT_SYMBOL(swiotlb_map_single); EXPORT_SYMBOL(swiotlb_map_single);
EXPORT_SYMBOL(swiotlb_unmap_single); EXPORT_SYMBOL(swiotlb_unmap_single);
...@@ -488,3 +499,4 @@ EXPORT_SYMBOL(swiotlb_sync_sg); ...@@ -488,3 +499,4 @@ EXPORT_SYMBOL(swiotlb_sync_sg);
EXPORT_SYMBOL(swiotlb_dma_address); EXPORT_SYMBOL(swiotlb_dma_address);
EXPORT_SYMBOL(swiotlb_alloc_consistent); EXPORT_SYMBOL(swiotlb_alloc_consistent);
EXPORT_SYMBOL(swiotlb_free_consistent); EXPORT_SYMBOL(swiotlb_free_consistent);
EXPORT_SYMBOL(swiotlb_pci_dma_supported);
...@@ -252,7 +252,7 @@ put_gate_page (struct page *page, unsigned long address) ...@@ -252,7 +252,7 @@ put_gate_page (struct page *page, unsigned long address)
void __init void __init
ia64_mmu_init (void *my_cpu_data) ia64_mmu_init (void *my_cpu_data)
{ {
unsigned long flags, rid, pta, impl_va_bits; unsigned long psr, rid, pta, impl_va_bits;
extern void __init tlb_init (void); extern void __init tlb_init (void);
#ifdef CONFIG_DISABLE_VHPT #ifdef CONFIG_DISABLE_VHPT
# define VHPT_ENABLE_BIT 0 # define VHPT_ENABLE_BIT 0
...@@ -264,7 +264,7 @@ ia64_mmu_init (void *my_cpu_data) ...@@ -264,7 +264,7 @@ ia64_mmu_init (void *my_cpu_data)
* Set up the kernel identity mapping for regions 6 and 5. The mapping for region * Set up the kernel identity mapping for regions 6 and 5. The mapping for region
* 7 is setup up in _start(). * 7 is setup up in _start().
*/ */
ia64_clear_ic(flags); psr = ia64_clear_ic();
rid = ia64_rid(IA64_REGION_ID_KERNEL, __IA64_UNCACHED_OFFSET); rid = ia64_rid(IA64_REGION_ID_KERNEL, __IA64_UNCACHED_OFFSET);
ia64_set_rr(__IA64_UNCACHED_OFFSET, (rid << 8) | (IA64_GRANULE_SHIFT << 2)); ia64_set_rr(__IA64_UNCACHED_OFFSET, (rid << 8) | (IA64_GRANULE_SHIFT << 2));
...@@ -278,7 +278,7 @@ ia64_mmu_init (void *my_cpu_data) ...@@ -278,7 +278,7 @@ ia64_mmu_init (void *my_cpu_data)
ia64_itr(0x2, IA64_TR_PERCPU_DATA, PERCPU_ADDR, ia64_itr(0x2, IA64_TR_PERCPU_DATA, PERCPU_ADDR,
pte_val(pfn_pte(__pa(my_cpu_data) >> PAGE_SHIFT, PAGE_KERNEL)), PAGE_SHIFT); pte_val(pfn_pte(__pa(my_cpu_data) >> PAGE_SHIFT, PAGE_KERNEL)), PAGE_SHIFT);
__restore_flags(flags); ia64_set_psr(psr);
ia64_srlz_i(); ia64_srlz_i();
/* /*
......
...@@ -18,7 +18,7 @@ EXTRA_CFLAGS := -DLITTLE_ENDIAN ...@@ -18,7 +18,7 @@ EXTRA_CFLAGS := -DLITTLE_ENDIAN
O_TARGET := sgiio.o O_TARGET := sgiio.o
ifeq ($(CONFIG_MODULES),y) ifeq ($(CONFIG_MODULES),y)
export-objs = pciio.o hcl.o export-objs = pciio.o hcl.o pci_dma.o
endif endif
obj-y := stubs.o sgi_if.o pciio.o xtalk.o xbow.o xswitch.o klgraph_hack.o \ obj-y := stubs.o sgi_if.o pciio.o xtalk.o xbow.o xswitch.o klgraph_hack.o \
......
...@@ -4,6 +4,9 @@ ...@@ -4,6 +4,9 @@
* for more details. * for more details.
* *
* Copyright (C) 2000,2002 Silicon Graphics, Inc. All rights reserved. * Copyright (C) 2000,2002 Silicon Graphics, Inc. All rights reserved.
*
* Routines for PCI DMA mapping. See Documentation/DMA-mapping.txt for
* a description of how these routines should be used.
*/ */
#include <linux/types.h> #include <linux/types.h>
...@@ -12,6 +15,7 @@ ...@@ -12,6 +15,7 @@
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/devfs_fs_kernel.h> #include <linux/devfs_fs_kernel.h>
#include <linux/module.h>
#include <asm/delay.h> #include <asm/delay.h>
#include <asm/io.h> #include <asm/io.h>
...@@ -46,7 +50,7 @@ get_free_pciio_dmamap(devfs_handle_t pci_bus) ...@@ -46,7 +50,7 @@ get_free_pciio_dmamap(devfs_handle_t pci_bus)
/* /*
* Darn, we need to get the maps allocated for this bus. * Darn, we need to get the maps allocated for this bus.
*/ */
for (i=0; i<MAX_PCI_XWIDGET; i++) { for (i = 0; i < MAX_PCI_XWIDGET; i++) {
if (busnum_to_pcibr_vhdl[i] == pci_bus) { if (busnum_to_pcibr_vhdl[i] == pci_bus) {
sn1_dma_map = busnum_to_atedmamaps[i]; sn1_dma_map = busnum_to_atedmamaps[i];
} }
...@@ -314,22 +318,18 @@ sn1_pci_map_sg (struct pci_dev *hwdev, ...@@ -314,22 +318,18 @@ sn1_pci_map_sg (struct pci_dev *hwdev,
} }
/* /*
* It is a 32bit card and we cannot do Direct mapping. * It is a 32 bit card and we cannot do direct mapping,
* Let's 32Bit Page map the request. * so we use an ATE.
*/ */
dma_map = NULL; dma_map = 0;
#ifdef CONFIG_IA64_SGI_SN1
dma_map = pciio_dmamap_alloc(vhdl, NULL, sg->length, dma_map = pciio_dmamap_alloc(vhdl, NULL, sg->length,
PCIIO_BYTE_STREAM | PCIIO_DMA_DATA); DMA_DATA_FLAGS);
#else
dma_map = pciio_dmamap_alloc(vhdl, NULL, sg->length, PCIIO_DMA_DATA);
#endif
if (!dma_map) { if (!dma_map) {
printk("pci_map_sg: Unable to allocate anymore 32Bits Page Map entries.\n"); printk(KERN_ERR "sn_pci_map_sg: Unable to allocate "
"anymore 32 bit page map entries.\n");
BUG(); BUG();
} }
dma_addr = (dma_addr_t)pciio_dmamap_addr(dma_map, temp_ptr, sg->length); dma_addr = pciio_dmamap_addr(dma_map, phys_addr, sg->length);
/* printk("pci_map_sg: dma_map 0x%p Phys Addr 0x%p dma_addr 0x%p\n", dma_map, temp_ptr, dma_addr); */
sg->address = (char *)dma_addr; sg->address = (char *)dma_addr;
sg->page = (char *)dma_map; sg->page = (char *)dma_map;
...@@ -372,7 +372,17 @@ sn1_pci_unmap_sg (struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int ...@@ -372,7 +372,17 @@ sn1_pci_unmap_sg (struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int
} }
/* /**
* sn_pci_map_single - map a single region for DMA
* @hwdev: device to map for
* @ptr: kernel virtual address of the region to map
* @size: size of the region
* @direction: DMA direction
*
* Map the region pointed to by @ptr for DMA and return the
* DMA address. Also known as platform_pci_map_single() by
* the IA64 machvec code.
*
* We map this to the one step pciio_dmamap_trans interface rather than * We map this to the one step pciio_dmamap_trans interface rather than
* the two step pciio_dmamap_alloc/pciio_dmamap_addr because we have * the two step pciio_dmamap_alloc/pciio_dmamap_addr because we have
* no way of saving the dmamap handle from the alloc to later free * no way of saving the dmamap handle from the alloc to later free
......
...@@ -75,7 +75,7 @@ sgi_mcatest(void) ...@@ -75,7 +75,7 @@ sgi_mcatest(void)
if (mcatest == 5) { if (mcatest == 5) {
int zzzspec(long); int zzzspec(long);
int i; int i;
long flags, dcr, res, val, addr=0xff00000000UL; long psr, dcr, res, val, addr=0xff00000000UL;
dcr = ia64_get_dcr(); dcr = ia64_get_dcr();
for (i=0; i<5; i++) { for (i=0; i<5; i++) {
...@@ -87,11 +87,11 @@ sgi_mcatest(void) ...@@ -87,11 +87,11 @@ sgi_mcatest(void)
ia64_set_dcr(dcr); ia64_set_dcr(dcr);
res = ia64_sn_probe_io_slot(0xff00000000UL, 8, &val); res = ia64_sn_probe_io_slot(0xff00000000UL, 8, &val);
printk("zzzspec: probe %ld, 0x%lx\n", res, val); printk("zzzspec: probe %ld, 0x%lx\n", res, val);
ia64_clear_ic(flags); psr = ia64_clear_ic();
ia64_itc(0x2, 0xe00000ff00000000UL, ia64_itc(0x2, 0xe00000ff00000000UL,
pte_val(pfn_pte(0xff00000000UL >> PAGE_SHIFT, pte_val(pfn_pte(0xff00000000UL >> PAGE_SHIFT,
__pgprot(__DIRTY_BITS|_PAGE_PL_0|_PAGE_AR_RW))), _PAGE_SIZE_256M); __pgprot(__DIRTY_BITS|_PAGE_PL_0|_PAGE_AR_RW))), _PAGE_SIZE_256M);
local_irq_restore(flags); ia64_set_psr(psr);
ia64_srlz_i (); ia64_srlz_i ();
} }
......
...@@ -41,7 +41,8 @@ SECTIONS ...@@ -41,7 +41,8 @@ SECTIONS
/* Read-only data */ /* Read-only data */
__gp = ALIGN(16) + 0x200000; /* gp must be 16-byte aligned for exc. table */ . = ALIGN(16);
__gp = . + 0x200000; /* gp must be 16-byte aligned for exc. table */
/* Global data */ /* Global data */
_data = .; _data = .;
......
...@@ -7,9 +7,9 @@ ...@@ -7,9 +7,9 @@
* *
* Copyright (C) 1999 VA Linux Systems * Copyright (C) 1999 VA Linux Systems
* Copyright (C) 1999 Walt Drummond <drummond@valinux.com> * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
* Copyright (C) 1999 Hewlett-Packard Co. * Copyright (C) 1999, 2002 Hewlett-Packard Co.
* Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com> * David Mosberger-Tang <davidm@hpl.hp.com>
* Copyright (C) 1999 Stephane Eranian <eranian@hpl.hp.com> * Stephane Eranian <eranian@hpl.hp.com>
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/string.h> #include <linux/string.h>
...@@ -259,7 +259,8 @@ extern void efi_memmap_walk (efi_freemem_callback_t callback, void *arg); ...@@ -259,7 +259,8 @@ extern void efi_memmap_walk (efi_freemem_callback_t callback, void *arg);
extern void efi_gettimeofday (struct timeval *tv); extern void efi_gettimeofday (struct timeval *tv);
extern void efi_enter_virtual_mode (void); /* switch EFI to virtual mode, if possible */ extern void efi_enter_virtual_mode (void); /* switch EFI to virtual mode, if possible */
extern u64 efi_get_iobase (void); extern u64 efi_get_iobase (void);
extern u32 efi_mem_type (u64 phys_addr); extern u32 efi_mem_type (unsigned long phys_addr);
extern u64 efi_mem_attributes (unsigned long phys_addr);
/* /*
* Variable Attributes * Variable Attributes
......
...@@ -38,7 +38,7 @@ ...@@ -38,7 +38,7 @@
* the way of the program that it will "exec", and that there is * the way of the program that it will "exec", and that there is
* sufficient room for the brk. * sufficient room for the brk.
*/ */
#define ELF_ET_DYN_BASE (TASK_UNMAPPED_BASE + 0x1000000) #define ELF_ET_DYN_BASE (TASK_UNMAPPED_BASE + 0x800000000)
/* /*
......
...@@ -2,8 +2,8 @@ ...@@ -2,8 +2,8 @@
#define _ASM_IA64_KREGS_H #define _ASM_IA64_KREGS_H
/* /*
* Copyright (C) 2001 Hewlett-Packard Co * Copyright (C) 2001-2002 Hewlett-Packard Co
* Copyright (C) 2001 David Mosberger-Tang <davidm@hpl.hp.com> * David Mosberger-Tang <davidm@hpl.hp.com>
*/ */
/* /*
* This file defines the kernel register usage convention used by Linux/ia64. * This file defines the kernel register usage convention used by Linux/ia64.
...@@ -31,4 +31,121 @@ ...@@ -31,4 +31,121 @@
#define IA64_TR_PERCPU_DATA 1 /* dtr1: percpu data */ #define IA64_TR_PERCPU_DATA 1 /* dtr1: percpu data */
#define IA64_TR_CURRENT_STACK 2 /* dtr2: maps kernel's memory- & register-stacks */ #define IA64_TR_CURRENT_STACK 2 /* dtr2: maps kernel's memory- & register-stacks */
/* Processor status register bits: */
#define IA64_PSR_BE_BIT 1
#define IA64_PSR_UP_BIT 2
#define IA64_PSR_AC_BIT 3
#define IA64_PSR_MFL_BIT 4
#define IA64_PSR_MFH_BIT 5
#define IA64_PSR_IC_BIT 13
#define IA64_PSR_I_BIT 14
#define IA64_PSR_PK_BIT 15
#define IA64_PSR_DT_BIT 17
#define IA64_PSR_DFL_BIT 18
#define IA64_PSR_DFH_BIT 19
#define IA64_PSR_SP_BIT 20
#define IA64_PSR_PP_BIT 21
#define IA64_PSR_DI_BIT 22
#define IA64_PSR_SI_BIT 23
#define IA64_PSR_DB_BIT 24
#define IA64_PSR_LP_BIT 25
#define IA64_PSR_TB_BIT 26
#define IA64_PSR_RT_BIT 27
/* The following are not affected by save_flags()/restore_flags(): */
#define IA64_PSR_CPL0_BIT 32
#define IA64_PSR_CPL1_BIT 33
#define IA64_PSR_IS_BIT 34
#define IA64_PSR_MC_BIT 35
#define IA64_PSR_IT_BIT 36
#define IA64_PSR_ID_BIT 37
#define IA64_PSR_DA_BIT 38
#define IA64_PSR_DD_BIT 39
#define IA64_PSR_SS_BIT 40
#define IA64_PSR_RI_BIT 41
#define IA64_PSR_ED_BIT 43
#define IA64_PSR_BN_BIT 44
#define IA64_PSR_BE (__IA64_UL(1) << IA64_PSR_BE_BIT)
#define IA64_PSR_UP (__IA64_UL(1) << IA64_PSR_UP_BIT)
#define IA64_PSR_AC (__IA64_UL(1) << IA64_PSR_AC_BIT)
#define IA64_PSR_MFL (__IA64_UL(1) << IA64_PSR_MFL_BIT)
#define IA64_PSR_MFH (__IA64_UL(1) << IA64_PSR_MFH_BIT)
#define IA64_PSR_IC (__IA64_UL(1) << IA64_PSR_IC_BIT)
#define IA64_PSR_I (__IA64_UL(1) << IA64_PSR_I_BIT)
#define IA64_PSR_PK (__IA64_UL(1) << IA64_PSR_PK_BIT)
#define IA64_PSR_DT (__IA64_UL(1) << IA64_PSR_DT_BIT)
#define IA64_PSR_DFL (__IA64_UL(1) << IA64_PSR_DFL_BIT)
#define IA64_PSR_DFH (__IA64_UL(1) << IA64_PSR_DFH_BIT)
#define IA64_PSR_SP (__IA64_UL(1) << IA64_PSR_SP_BIT)
#define IA64_PSR_PP (__IA64_UL(1) << IA64_PSR_PP_BIT)
#define IA64_PSR_DI (__IA64_UL(1) << IA64_PSR_DI_BIT)
#define IA64_PSR_SI (__IA64_UL(1) << IA64_PSR_SI_BIT)
#define IA64_PSR_DB (__IA64_UL(1) << IA64_PSR_DB_BIT)
#define IA64_PSR_LP (__IA64_UL(1) << IA64_PSR_LP_BIT)
#define IA64_PSR_TB (__IA64_UL(1) << IA64_PSR_TB_BIT)
#define IA64_PSR_RT (__IA64_UL(1) << IA64_PSR_RT_BIT)
/* The following are not affected by save_flags()/restore_flags(): */
#define IA64_PSR_IS (__IA64_UL(1) << IA64_PSR_IS_BIT)
#define IA64_PSR_MC (__IA64_UL(1) << IA64_PSR_MC_BIT)
#define IA64_PSR_IT (__IA64_UL(1) << IA64_PSR_IT_BIT)
#define IA64_PSR_ID (__IA64_UL(1) << IA64_PSR_ID_BIT)
#define IA64_PSR_DA (__IA64_UL(1) << IA64_PSR_DA_BIT)
#define IA64_PSR_DD (__IA64_UL(1) << IA64_PSR_DD_BIT)
#define IA64_PSR_SS (__IA64_UL(1) << IA64_PSR_SS_BIT)
#define IA64_PSR_RI (__IA64_UL(3) << IA64_PSR_RI_BIT)
#define IA64_PSR_ED (__IA64_UL(1) << IA64_PSR_ED_BIT)
#define IA64_PSR_BN (__IA64_UL(1) << IA64_PSR_BN_BIT)
/* User mask bits: */
#define IA64_PSR_UM (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL | IA64_PSR_MFH)
/* Default Control Register */
#define IA64_DCR_PP_BIT 0 /* privileged performance monitor default */
#define IA64_DCR_BE_BIT 1 /* big-endian default */
#define IA64_DCR_LC_BIT 2 /* ia32 lock-check enable */
#define IA64_DCR_DM_BIT 8 /* defer TLB miss faults */
#define IA64_DCR_DP_BIT 9 /* defer page-not-present faults */
#define IA64_DCR_DK_BIT 10 /* defer key miss faults */
#define IA64_DCR_DX_BIT 11 /* defer key permission faults */
#define IA64_DCR_DR_BIT 12 /* defer access right faults */
#define IA64_DCR_DA_BIT 13 /* defer access bit faults */
#define IA64_DCR_DD_BIT 14 /* defer debug faults */
#define IA64_DCR_PP (__IA64_UL(1) << IA64_DCR_PP_BIT)
#define IA64_DCR_BE (__IA64_UL(1) << IA64_DCR_BE_BIT)
#define IA64_DCR_LC (__IA64_UL(1) << IA64_DCR_LC_BIT)
#define IA64_DCR_DM (__IA64_UL(1) << IA64_DCR_DM_BIT)
#define IA64_DCR_DP (__IA64_UL(1) << IA64_DCR_DP_BIT)
#define IA64_DCR_DK (__IA64_UL(1) << IA64_DCR_DK_BIT)
#define IA64_DCR_DX (__IA64_UL(1) << IA64_DCR_DX_BIT)
#define IA64_DCR_DR (__IA64_UL(1) << IA64_DCR_DR_BIT)
#define IA64_DCR_DA (__IA64_UL(1) << IA64_DCR_DA_BIT)
#define IA64_DCR_DD (__IA64_UL(1) << IA64_DCR_DD_BIT)
/* Interrupt Status Register */
#define IA64_ISR_X_BIT 32 /* execute access */
#define IA64_ISR_W_BIT 33 /* write access */
#define IA64_ISR_R_BIT 34 /* read access */
#define IA64_ISR_NA_BIT 35 /* non-access */
#define IA64_ISR_SP_BIT 36 /* speculative load exception */
#define IA64_ISR_RS_BIT 37 /* mandatory register-stack exception */
#define IA64_ISR_IR_BIT 38 /* invalid register frame exception */
#define IA64_ISR_CODE_MASK 0xf
#define IA64_ISR_X (__IA64_UL(1) << IA64_ISR_X_BIT)
#define IA64_ISR_W (__IA64_UL(1) << IA64_ISR_W_BIT)
#define IA64_ISR_R (__IA64_UL(1) << IA64_ISR_R_BIT)
#define IA64_ISR_NA (__IA64_UL(1) << IA64_ISR_NA_BIT)
#define IA64_ISR_SP (__IA64_UL(1) << IA64_ISR_SP_BIT)
#define IA64_ISR_RS (__IA64_UL(1) << IA64_ISR_RS_BIT)
#define IA64_ISR_IR (__IA64_UL(1) << IA64_ISR_IR_BIT)
/* ISR code field for non-access instructions */
#define IA64_ISR_CODE_TPA 0
#define IA64_ISR_CODE_FC 1
#define IA64_ISR_CODE_PROBE 2
#define IA64_ISR_CODE_TAK 3
#define IA64_ISR_CODE_LFETCH 4
#define IA64_ISR_CODE_PROBEF 5
#endif /* _ASM_IA64_kREGS_H */ #endif /* _ASM_IA64_kREGS_H */
...@@ -18,6 +18,7 @@ struct pci_dev; ...@@ -18,6 +18,7 @@ struct pci_dev;
struct pt_regs; struct pt_regs;
struct scatterlist; struct scatterlist;
struct irq_desc; struct irq_desc;
struct page;
typedef void ia64_mv_setup_t (char **); typedef void ia64_mv_setup_t (char **);
typedef void ia64_mv_cpu_init_t(void); typedef void ia64_mv_cpu_init_t(void);
...@@ -45,6 +46,8 @@ typedef void ia64_mv_pci_unmap_sg (struct pci_dev *, struct scatterlist *, int, ...@@ -45,6 +46,8 @@ typedef void ia64_mv_pci_unmap_sg (struct pci_dev *, struct scatterlist *, int,
typedef void ia64_mv_pci_dma_sync_single (struct pci_dev *, dma_addr_t, size_t, int); typedef void ia64_mv_pci_dma_sync_single (struct pci_dev *, dma_addr_t, size_t, int);
typedef void ia64_mv_pci_dma_sync_sg (struct pci_dev *, struct scatterlist *, int, int); typedef void ia64_mv_pci_dma_sync_sg (struct pci_dev *, struct scatterlist *, int, int);
typedef unsigned long ia64_mv_pci_dma_address (struct scatterlist *); typedef unsigned long ia64_mv_pci_dma_address (struct scatterlist *);
typedef int ia64_mv_pci_dma_supported (struct pci_dev *, u64);
/* /*
* WARNING: The legacy I/O space is _architected_. Platforms are * WARNING: The legacy I/O space is _architected_. Platforms are
* expected to follow this architected model (see Section 10.7 in the * expected to follow this architected model (see Section 10.7 in the
...@@ -101,6 +104,7 @@ extern void machvec_noop (void); ...@@ -101,6 +104,7 @@ extern void machvec_noop (void);
# define platform_pci_dma_sync_single ia64_mv.sync_single # define platform_pci_dma_sync_single ia64_mv.sync_single
# define platform_pci_dma_sync_sg ia64_mv.sync_sg # define platform_pci_dma_sync_sg ia64_mv.sync_sg
# define platform_pci_dma_address ia64_mv.dma_address # define platform_pci_dma_address ia64_mv.dma_address
# define platform_pci_dma_supported ia64_mv.dma_supported
# define platform_irq_desc ia64_mv.irq_desc # define platform_irq_desc ia64_mv.irq_desc
# define platform_irq_to_vector ia64_mv.irq_to_vector # define platform_irq_to_vector ia64_mv.irq_to_vector
# define platform_local_vector_to_irq ia64_mv.local_vector_to_irq # define platform_local_vector_to_irq ia64_mv.local_vector_to_irq
...@@ -136,6 +140,7 @@ struct ia64_machine_vector { ...@@ -136,6 +140,7 @@ struct ia64_machine_vector {
ia64_mv_pci_dma_sync_single *sync_single; ia64_mv_pci_dma_sync_single *sync_single;
ia64_mv_pci_dma_sync_sg *sync_sg; ia64_mv_pci_dma_sync_sg *sync_sg;
ia64_mv_pci_dma_address *dma_address; ia64_mv_pci_dma_address *dma_address;
ia64_mv_pci_dma_supported *dma_supported;
ia64_mv_irq_desc *irq_desc; ia64_mv_irq_desc *irq_desc;
ia64_mv_irq_to_vector *irq_to_vector; ia64_mv_irq_to_vector *irq_to_vector;
ia64_mv_local_vector_to_irq *local_vector_to_irq; ia64_mv_local_vector_to_irq *local_vector_to_irq;
...@@ -172,6 +177,7 @@ struct ia64_machine_vector { ...@@ -172,6 +177,7 @@ struct ia64_machine_vector {
platform_pci_dma_sync_single, \ platform_pci_dma_sync_single, \
platform_pci_dma_sync_sg, \ platform_pci_dma_sync_sg, \
platform_pci_dma_address, \ platform_pci_dma_address, \
platform_pci_dma_supported, \
platform_irq_desc, \ platform_irq_desc, \
platform_irq_to_vector, \ platform_irq_to_vector, \
platform_local_vector_to_irq, \ platform_local_vector_to_irq, \
...@@ -269,6 +275,9 @@ extern ia64_mv_pci_dma_address swiotlb_dma_address; ...@@ -269,6 +275,9 @@ extern ia64_mv_pci_dma_address swiotlb_dma_address;
#ifndef platform_pci_dma_address #ifndef platform_pci_dma_address
# define platform_pci_dma_address swiotlb_dma_address # define platform_pci_dma_address swiotlb_dma_address
#endif #endif
#ifndef platform_pci_dma_supported
# define platform_pci_dma_supported swiotlb_pci_dma_supported
#endif
#ifndef platform_irq_desc #ifndef platform_irq_desc
# define platform_irq_desc __ia64_irq_desc # define platform_irq_desc __ia64_irq_desc
#endif #endif
......
...@@ -11,6 +11,7 @@ extern ia64_mv_pci_unmap_single sba_unmap_single; ...@@ -11,6 +11,7 @@ extern ia64_mv_pci_unmap_single sba_unmap_single;
extern ia64_mv_pci_map_sg sba_map_sg; extern ia64_mv_pci_map_sg sba_map_sg;
extern ia64_mv_pci_unmap_sg sba_unmap_sg; extern ia64_mv_pci_unmap_sg sba_unmap_sg;
extern ia64_mv_pci_dma_address sba_dma_address; extern ia64_mv_pci_dma_address sba_dma_address;
extern ia64_mv_pci_dma_supported sba_dma_supported;
/* /*
* This stuff has dual use! * This stuff has dual use!
...@@ -33,42 +34,6 @@ extern ia64_mv_pci_dma_address sba_dma_address; ...@@ -33,42 +34,6 @@ extern ia64_mv_pci_dma_address sba_dma_address;
#define platform_pci_dma_sync_single ((ia64_mv_pci_dma_sync_single *) machvec_noop) #define platform_pci_dma_sync_single ((ia64_mv_pci_dma_sync_single *) machvec_noop)
#define platform_pci_dma_sync_sg ((ia64_mv_pci_dma_sync_sg *) machvec_noop) #define platform_pci_dma_sync_sg ((ia64_mv_pci_dma_sync_sg *) machvec_noop)
#define platform_pci_dma_address sba_dma_address #define platform_pci_dma_address sba_dma_address
#define platform_pci_dma_supported sba_dma_supported
#endif /* _ASM_IA64_MACHVEC_HPZX1_h */
#ifndef _ASM_IA64_MACHVEC_HPZX1_h
#define _ASM_IA64_MACHVEC_HPZX1_h
extern ia64_mv_setup_t dig_setup;
extern ia64_mv_pci_fixup_t hpzx1_pci_fixup;
extern ia64_mv_map_nr_t map_nr_dense;
extern ia64_mv_pci_alloc_consistent sba_alloc_consistent;
extern ia64_mv_pci_free_consistent sba_free_consistent;
extern ia64_mv_pci_map_single sba_map_single;
extern ia64_mv_pci_unmap_single sba_unmap_single;
extern ia64_mv_pci_map_sg sba_map_sg;
extern ia64_mv_pci_unmap_sg sba_unmap_sg;
extern ia64_mv_pci_dma_address sba_dma_address;
/*
* This stuff has dual use!
*
* For a generic kernel, the macros are used to initialize the
* platform's machvec structure. When compiling a non-generic kernel,
* the macros are used directly.
*/
#define platform_name "hpzx1"
#define platform_setup dig_setup
#define platform_pci_fixup hpzx1_pci_fixup
#define platform_map_nr map_nr_dense
#define platform_pci_dma_init ((ia64_mv_pci_dma_init *) machvec_noop)
#define platform_pci_alloc_consistent sba_alloc_consistent
#define platform_pci_free_consistent sba_free_consistent
#define platform_pci_map_single sba_map_single
#define platform_pci_unmap_single sba_unmap_single
#define platform_pci_map_sg sba_map_sg
#define platform_pci_unmap_sg sba_unmap_sg
#define platform_pci_dma_sync_single ((ia64_mv_pci_dma_sync_single *) machvec_noop)
#define platform_pci_dma_sync_sg ((ia64_mv_pci_dma_sync_sg *) machvec_noop)
#define platform_pci_dma_address sba_dma_address
#endif /* _ASM_IA64_MACHVEC_HPZX1_h */ #endif /* _ASM_IA64_MACHVEC_HPZX1_h */
...@@ -106,6 +106,7 @@ ...@@ -106,6 +106,7 @@
#define IA64_SWITCH_STACK_AR_RNAT_OFFSET 536 /* 0x218 */ #define IA64_SWITCH_STACK_AR_RNAT_OFFSET 536 /* 0x218 */
#define IA64_SWITCH_STACK_AR_BSPSTORE_OFFSET 544 /* 0x220 */ #define IA64_SWITCH_STACK_AR_BSPSTORE_OFFSET 544 /* 0x220 */
#define IA64_SWITCH_STACK_PR_OFFSET 552 /* 0x228 */ #define IA64_SWITCH_STACK_PR_OFFSET 552 /* 0x228 */
#define IA64_SIGCONTEXT_IP_OFFSET 40 /* 0x28 */
#define IA64_SIGCONTEXT_AR_BSP_OFFSET 72 /* 0x48 */ #define IA64_SIGCONTEXT_AR_BSP_OFFSET 72 /* 0x48 */
#define IA64_SIGCONTEXT_AR_FPSR_OFFSET 104 /* 0x68 */ #define IA64_SIGCONTEXT_AR_FPSR_OFFSET 104 /* 0x68 */
#define IA64_SIGCONTEXT_AR_RNAT_OFFSET 80 /* 0x50 */ #define IA64_SIGCONTEXT_AR_RNAT_OFFSET 80 /* 0x50 */
......
...@@ -58,6 +58,7 @@ pcibios_penalize_isa_irq (int irq) ...@@ -58,6 +58,7 @@ pcibios_penalize_isa_irq (int irq)
#define pci_dma_sync_single platform_pci_dma_sync_single #define pci_dma_sync_single platform_pci_dma_sync_single
#define pci_dma_sync_sg platform_pci_dma_sync_sg #define pci_dma_sync_sg platform_pci_dma_sync_sg
#define sg_dma_address platform_pci_dma_address #define sg_dma_address platform_pci_dma_address
#define pci_dma_supported platform_pci_dma_supported
/* pci_unmap_{single,page} is not a nop, thus... */ /* pci_unmap_{single,page} is not a nop, thus... */
#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
...@@ -73,17 +74,6 @@ pcibios_penalize_isa_irq (int irq) ...@@ -73,17 +74,6 @@ pcibios_penalize_isa_irq (int irq)
#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
(((PTR)->LEN_NAME) = (VAL)) (((PTR)->LEN_NAME) = (VAL))
/*
* Return whether the given PCI device DMA address mask can be supported properly. For
* example, if your device can only drive the low 24-bits during PCI bus mastering, then
* you would pass 0x00ffffff as the mask to this function.
*/
static inline int
pci_dma_supported (struct pci_dev *hwdev, u64 mask)
{
return 1;
}
#define pci_map_page(dev,pg,off,size,dir) \ #define pci_map_page(dev,pg,off,size,dir) \
pci_map_single((dev), page_address(pg) + (off), (size), (dir)) pci_map_single((dev), page_address(pg) + (off), (size), (dir))
#define pci_unmap_page(dev,dma_addr,size,dir) \ #define pci_unmap_page(dev,dma_addr,size,dir) \
......
...@@ -55,123 +55,6 @@ ...@@ -55,123 +55,6 @@
#define MCA_bus 0 #define MCA_bus 0
#define MCA_bus__is_a_macro /* for versions in ksyms.c */ #define MCA_bus__is_a_macro /* for versions in ksyms.c */
/* Processor status register bits: */
#define IA64_PSR_BE_BIT 1
#define IA64_PSR_UP_BIT 2
#define IA64_PSR_AC_BIT 3
#define IA64_PSR_MFL_BIT 4
#define IA64_PSR_MFH_BIT 5
#define IA64_PSR_IC_BIT 13
#define IA64_PSR_I_BIT 14
#define IA64_PSR_PK_BIT 15
#define IA64_PSR_DT_BIT 17
#define IA64_PSR_DFL_BIT 18
#define IA64_PSR_DFH_BIT 19
#define IA64_PSR_SP_BIT 20
#define IA64_PSR_PP_BIT 21
#define IA64_PSR_DI_BIT 22
#define IA64_PSR_SI_BIT 23
#define IA64_PSR_DB_BIT 24
#define IA64_PSR_LP_BIT 25
#define IA64_PSR_TB_BIT 26
#define IA64_PSR_RT_BIT 27
/* The following are not affected by save_flags()/restore_flags(): */
#define IA64_PSR_CPL0_BIT 32
#define IA64_PSR_CPL1_BIT 33
#define IA64_PSR_IS_BIT 34
#define IA64_PSR_MC_BIT 35
#define IA64_PSR_IT_BIT 36
#define IA64_PSR_ID_BIT 37
#define IA64_PSR_DA_BIT 38
#define IA64_PSR_DD_BIT 39
#define IA64_PSR_SS_BIT 40
#define IA64_PSR_RI_BIT 41
#define IA64_PSR_ED_BIT 43
#define IA64_PSR_BN_BIT 44
#define IA64_PSR_BE (__IA64_UL(1) << IA64_PSR_BE_BIT)
#define IA64_PSR_UP (__IA64_UL(1) << IA64_PSR_UP_BIT)
#define IA64_PSR_AC (__IA64_UL(1) << IA64_PSR_AC_BIT)
#define IA64_PSR_MFL (__IA64_UL(1) << IA64_PSR_MFL_BIT)
#define IA64_PSR_MFH (__IA64_UL(1) << IA64_PSR_MFH_BIT)
#define IA64_PSR_IC (__IA64_UL(1) << IA64_PSR_IC_BIT)
#define IA64_PSR_I (__IA64_UL(1) << IA64_PSR_I_BIT)
#define IA64_PSR_PK (__IA64_UL(1) << IA64_PSR_PK_BIT)
#define IA64_PSR_DT (__IA64_UL(1) << IA64_PSR_DT_BIT)
#define IA64_PSR_DFL (__IA64_UL(1) << IA64_PSR_DFL_BIT)
#define IA64_PSR_DFH (__IA64_UL(1) << IA64_PSR_DFH_BIT)
#define IA64_PSR_SP (__IA64_UL(1) << IA64_PSR_SP_BIT)
#define IA64_PSR_PP (__IA64_UL(1) << IA64_PSR_PP_BIT)
#define IA64_PSR_DI (__IA64_UL(1) << IA64_PSR_DI_BIT)
#define IA64_PSR_SI (__IA64_UL(1) << IA64_PSR_SI_BIT)
#define IA64_PSR_DB (__IA64_UL(1) << IA64_PSR_DB_BIT)
#define IA64_PSR_LP (__IA64_UL(1) << IA64_PSR_LP_BIT)
#define IA64_PSR_TB (__IA64_UL(1) << IA64_PSR_TB_BIT)
#define IA64_PSR_RT (__IA64_UL(1) << IA64_PSR_RT_BIT)
/* The following are not affected by save_flags()/restore_flags(): */
#define IA64_PSR_IS (__IA64_UL(1) << IA64_PSR_IS_BIT)
#define IA64_PSR_MC (__IA64_UL(1) << IA64_PSR_MC_BIT)
#define IA64_PSR_IT (__IA64_UL(1) << IA64_PSR_IT_BIT)
#define IA64_PSR_ID (__IA64_UL(1) << IA64_PSR_ID_BIT)
#define IA64_PSR_DA (__IA64_UL(1) << IA64_PSR_DA_BIT)
#define IA64_PSR_DD (__IA64_UL(1) << IA64_PSR_DD_BIT)
#define IA64_PSR_SS (__IA64_UL(1) << IA64_PSR_SS_BIT)
#define IA64_PSR_RI (__IA64_UL(3) << IA64_PSR_RI_BIT)
#define IA64_PSR_ED (__IA64_UL(1) << IA64_PSR_ED_BIT)
#define IA64_PSR_BN (__IA64_UL(1) << IA64_PSR_BN_BIT)
/* User mask bits: */
#define IA64_PSR_UM (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL | IA64_PSR_MFH)
/* Default Control Register */
#define IA64_DCR_PP_BIT 0 /* privileged performance monitor default */
#define IA64_DCR_BE_BIT 1 /* big-endian default */
#define IA64_DCR_LC_BIT 2 /* ia32 lock-check enable */
#define IA64_DCR_DM_BIT 8 /* defer TLB miss faults */
#define IA64_DCR_DP_BIT 9 /* defer page-not-present faults */
#define IA64_DCR_DK_BIT 10 /* defer key miss faults */
#define IA64_DCR_DX_BIT 11 /* defer key permission faults */
#define IA64_DCR_DR_BIT 12 /* defer access right faults */
#define IA64_DCR_DA_BIT 13 /* defer access bit faults */
#define IA64_DCR_DD_BIT 14 /* defer debug faults */
#define IA64_DCR_PP (__IA64_UL(1) << IA64_DCR_PP_BIT)
#define IA64_DCR_BE (__IA64_UL(1) << IA64_DCR_BE_BIT)
#define IA64_DCR_LC (__IA64_UL(1) << IA64_DCR_LC_BIT)
#define IA64_DCR_DM (__IA64_UL(1) << IA64_DCR_DM_BIT)
#define IA64_DCR_DP (__IA64_UL(1) << IA64_DCR_DP_BIT)
#define IA64_DCR_DK (__IA64_UL(1) << IA64_DCR_DK_BIT)
#define IA64_DCR_DX (__IA64_UL(1) << IA64_DCR_DX_BIT)
#define IA64_DCR_DR (__IA64_UL(1) << IA64_DCR_DR_BIT)
#define IA64_DCR_DA (__IA64_UL(1) << IA64_DCR_DA_BIT)
#define IA64_DCR_DD (__IA64_UL(1) << IA64_DCR_DD_BIT)
/* Interrupt Status Register */
#define IA64_ISR_X_BIT 32 /* execute access */
#define IA64_ISR_W_BIT 33 /* write access */
#define IA64_ISR_R_BIT 34 /* read access */
#define IA64_ISR_NA_BIT 35 /* non-access */
#define IA64_ISR_SP_BIT 36 /* speculative load exception */
#define IA64_ISR_RS_BIT 37 /* mandatory register-stack exception */
#define IA64_ISR_IR_BIT 38 /* invalid register frame exception */
#define IA64_ISR_CODE_MASK 0xf
#define IA64_ISR_X (__IA64_UL(1) << IA64_ISR_X_BIT)
#define IA64_ISR_W (__IA64_UL(1) << IA64_ISR_W_BIT)
#define IA64_ISR_R (__IA64_UL(1) << IA64_ISR_R_BIT)
#define IA64_ISR_NA (__IA64_UL(1) << IA64_ISR_NA_BIT)
#define IA64_ISR_SP (__IA64_UL(1) << IA64_ISR_SP_BIT)
#define IA64_ISR_RS (__IA64_UL(1) << IA64_ISR_RS_BIT)
#define IA64_ISR_IR (__IA64_UL(1) << IA64_ISR_IR_BIT)
/* ISR code field for non-access instructions */
#define IA64_ISR_CODE_TPA 0
#define IA64_ISR_CODE_FC 1
#define IA64_ISR_CODE_PROBE 2
#define IA64_ISR_CODE_TAK 3
#define IA64_ISR_CODE_LFETCH 4
#define IA64_ISR_CODE_PROBEF 5
#define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */ #define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */
#define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */ #define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */
#define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */ #define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */
...@@ -632,14 +515,22 @@ ia64_invala (void) ...@@ -632,14 +515,22 @@ ia64_invala (void)
asm volatile ("invala" ::: "memory"); asm volatile ("invala" ::: "memory");
} }
static inline __u64
ia64_clear_ic (void)
{
__u64 psr;
asm volatile ("mov %0=psr;; rsm psr.i | psr.ic;; srlz.i;;" : "=r"(psr) :: "memory");
return psr;
}
/* /*
* Save the processor status flags in FLAGS and then clear the interrupt collection and * Restore the psr.
* interrupt enable bits. Don't trigger any mandatory RSE references while this bit is
* off!
*/ */
#define ia64_clear_ic(flags) \ static inline void
asm volatile ("mov %0=psr;; rsm psr.i | psr.ic;; srlz.i;;" \ ia64_set_psr (__u64 psr)
: "=r"(flags) :: "memory"); {
asm volatile (";; mov psr.l=%0;; srlz.d" :: "r" (psr) : "memory");
}
/* /*
* Insert a translation into an instruction and/or data translation * Insert a translation into an instruction and/or data translation
......
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
*/ */
#include <linux/config.h> #include <linux/config.h>
#include <asm/kregs.h>
#include <asm/page.h> #include <asm/page.h>
#define KERNEL_START (PAGE_OFFSET + 68*1024*1024) #define KERNEL_START (PAGE_OFFSET + 68*1024*1024)
...@@ -30,7 +31,7 @@ struct pci_vector_struct { ...@@ -30,7 +31,7 @@ struct pci_vector_struct {
__u16 bus; /* PCI Bus number */ __u16 bus; /* PCI Bus number */
__u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */ __u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
__u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */ __u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
__u8 irq; /* IRQ assigned */ __u32 irq; /* IRQ assigned */
}; };
extern struct ia64_boot_param { extern struct ia64_boot_param {
...@@ -139,9 +140,14 @@ do { \ ...@@ -139,9 +140,14 @@ do { \
do { \ do { \
unsigned long ip, old_psr, psr = (x); \ unsigned long ip, old_psr, psr = (x); \
\ \
__asm__ __volatile__ (";;mov %0=psr; mov psr.l=%1;; srlz.d" \ __asm__ __volatile__ ("mov %0=psr;" \
: "=&r" (old_psr) : "r" (psr) : "memory"); \ "cmp.ne p6,p7=%1,r0;;" \
if ((old_psr & (1UL << 14)) && !(psr & (1UL << 14))) { \ "(p6) ssm psr.i;" \
"(p7) rsm psr.i;;" \
"srlz.d" \
: "=&r" (old_psr) : "r"((psr) & IA64_PSR_I) \
: "p6", "p7", "memory"); \
if ((old_psr & IA64_PSR_I) && !(psr & IA64_PSR_I)) { \
__asm__ ("mov %0=ip" : "=r"(ip)); \ __asm__ ("mov %0=ip" : "=r"(ip)); \
last_cli_ip = ip; \ last_cli_ip = ip; \
} \ } \
...@@ -153,8 +159,12 @@ do { \ ...@@ -153,8 +159,12 @@ do { \
: "=r" (x) :: "memory") : "=r" (x) :: "memory")
# define local_irq_disable() __asm__ __volatile__ (";; rsm psr.i;;" ::: "memory") # define local_irq_disable() __asm__ __volatile__ (";; rsm psr.i;;" ::: "memory")
/* (potentially) setting psr.i requires data serialization: */ /* (potentially) setting psr.i requires data serialization: */
# define local_irq_restore(x) __asm__ __volatile__ (";; mov psr.l=%0;; srlz.d" \ # define local_irq_restore(x) __asm__ __volatile__ ("cmp.ne p6,p7=%0,r0;;" \
:: "r" (x) : "memory") "(p6) ssm psr.i;" \
"(p7) rsm psr.i;;" \
"srlz.d" \
:: "r"((x) & IA64_PSR_I) \
: "p6", "p7", "memory")
#endif /* !CONFIG_IA64_DEBUG_IRQ */ #endif /* !CONFIG_IA64_DEBUG_IRQ */
#define local_irq_enable() __asm__ __volatile__ (";; ssm psr.i;; srlz.d" ::: "memory") #define local_irq_enable() __asm__ __volatile__ (";; ssm psr.i;; srlz.d" ::: "memory")
......
...@@ -222,6 +222,7 @@ ...@@ -222,6 +222,7 @@
#define __NR_futex 1230 #define __NR_futex 1230
#define __NR_sched_setaffinity 1231 #define __NR_sched_setaffinity 1231
#define __NR_sched_getaffinity 1232 #define __NR_sched_getaffinity 1232
#define __NR_security 1233
#if !defined(__ASSEMBLY__) && !defined(ASSEMBLER) #if !defined(__ASSEMBLY__) && !defined(ASSEMBLER)
......
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