Commit 77e0f282 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by Linus Torvalds

[PATCH] rework radeonfb blanking

This patch cleans up some old cruft in the manipulation of the LVDS
interface registers and fixes the blanking code to work with various DVI
flat panels.

Since this is all very sensitive stuff, I'm posting the patch here for
testing before submitting it upstream, though Andrew is welcome to put it
in -mm.

It also fix some problems with getting the right PLL setup on recent Mac
laptops, replacing the old hard coded list of values with cleaner code that
"probes" the PLL setup done by the firmware.
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 8f6e4a50
This diff is collapsed.
...@@ -633,43 +633,25 @@ void __devinit radeon_probe_screens(struct radeonfb_info *rinfo, ...@@ -633,43 +633,25 @@ void __devinit radeon_probe_screens(struct radeonfb_info *rinfo,
*/ */
static void radeon_fixup_panel_info(struct radeonfb_info *rinfo) static void radeon_fixup_panel_info(struct radeonfb_info *rinfo)
{ {
#ifdef CONFIG_PPC_OF
/* /*
* A few iBook laptop panels seem to need a fixed PLL setting * LCD Flat panels should use fixed dividers, we enfore that on
* * PowerMac only for now...
* We should probably do this differently based on the panel
* type/model or eventually some other device-tree informations,
* but these tweaks below work enough for now. --BenH
*/ */
#ifdef CONFIG_PPC_OF if (!rinfo->panel_info.use_bios_dividers && rinfo->mon1_type == MT_LCD
/* iBook2's */ && rinfo->is_mobility) {
if (machine_is_compatible("PowerBook4,3")) { int ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
rinfo->panel_info.ref_divider = rinfo->pll.ref_div; u32 ppll_divn = INPLL(PPLL_DIV_0 + ppll_div_sel);
rinfo->panel_info.post_divider = 0x6;
rinfo->panel_info.fbk_divider = 0xad;
rinfo->panel_info.use_bios_dividers = 1;
}
/* Aluminium PowerBook 15" */
if (machine_is_compatible("PowerBook5,4")) {
rinfo->panel_info.ref_divider = rinfo->pll.ref_div; rinfo->panel_info.ref_divider = rinfo->pll.ref_div;
rinfo->panel_info.post_divider = 0x2; rinfo->panel_info.fbk_divider = ppll_divn & 0x7ff;
rinfo->panel_info.fbk_divider = 0x8e; rinfo->panel_info.post_divider = (ppll_divn >> 16) & 0x7;
rinfo->panel_info.use_bios_dividers = 1;
}
/* Aluminium PowerBook 17" */
if (machine_is_compatible("PowerBook5,3") ||
machine_is_compatible("PowerBook5,5")) {
rinfo->panel_info.ref_divider = rinfo->pll.ref_div;
rinfo->panel_info.post_divider = 0x4;
rinfo->panel_info.fbk_divider = 0x80;
rinfo->panel_info.use_bios_dividers = 1;
}
/* iBook G4 */
if (machine_is_compatible("PowerBook6,3") ||
machine_is_compatible("PowerBook6,5")) {
rinfo->panel_info.ref_divider = rinfo->pll.ref_div;
rinfo->panel_info.post_divider = 0x6;
rinfo->panel_info.fbk_divider = 0xad;
rinfo->panel_info.use_bios_dividers = 1; rinfo->panel_info.use_bios_dividers = 1;
printk(KERN_DEBUG "radeonfb: Using Firmware dividers 0x%08x "
"from PPLL %d\n",
rinfo->panel_info.fbk_divider |
(rinfo->panel_info.post_divider << 16),
ppll_div_sel);
} }
#endif /* CONFIG_PPC_OF */ #endif /* CONFIG_PPC_OF */
} }
......
...@@ -465,7 +465,9 @@ static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo) ...@@ -465,7 +465,9 @@ static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl); OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);
/* Switch off LVDS interface */
OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) &
~(LVDS_BLON | LVDS_EN | LVDS_ON | LVDS_DIGON));
/* Enable System power management */ /* Enable System power management */
pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL); pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL);
......
...@@ -619,8 +619,7 @@ ...@@ -619,8 +619,7 @@
#define LVDS_BLON (1 << 19) #define LVDS_BLON (1 << 19)
#define LVDS_SEL_CRTC2 (1 << 23) #define LVDS_SEL_CRTC2 (1 << 23)
#define LVDS_STATE_MASK \ #define LVDS_STATE_MASK \
(LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | \ (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)
LVDS_EN | LVDS_DIGON | LVDS_BLON)
/* LVDS_PLL_CNTL bit constatns */ /* LVDS_PLL_CNTL bit constatns */
#define HSYNC_DELAY_SHIFT 0x1c #define HSYNC_DELAY_SHIFT 0x1c
......
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