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Commit 78501eac authored by Chris Wilson's avatar Chris Wilson
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drm/i915/ringbuffer: Drop the redundant dev from the vfunc interface 

The ringbuffer keeps a pointer to the parent device, so we can use that
instead of passing around the pointer on the stack.
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent dd2b379f
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Showing with 247 additions and 298 deletions
drivers/gpu/drm/i915/i915_debugfs.c
View file @ 78501eac
...@@ -296,7 +296,7 @@ static int i915_gem_seqno_info(struct seq_file *m, void *data) ...@@ -296,7 +296,7 @@ static int i915_gem_seqno_info(struct seq_file *m, void *data)
if (dev_priv->render_ring.status_page.page_addr != NULL) { if (dev_priv->render_ring.status_page.page_addr != NULL) {
seq_printf(m, "Current sequence: %d\n", seq_printf(m, "Current sequence: %d\n",
dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring)); dev_priv->render_ring.get_seqno(&dev_priv->render_ring));
} else { } else {
seq_printf(m, "Current sequence: hws uninitialized\n"); seq_printf(m, "Current sequence: hws uninitialized\n");
} }
...@@ -356,7 +356,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) ...@@ -356,7 +356,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
atomic_read(&dev_priv->irq_received)); atomic_read(&dev_priv->irq_received));
if (dev_priv->render_ring.status_page.page_addr != NULL) { if (dev_priv->render_ring.status_page.page_addr != NULL) {
seq_printf(m, "Current sequence: %d\n", seq_printf(m, "Current sequence: %d\n",
dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring)); dev_priv->render_ring.get_seqno(&dev_priv->render_ring));
} else { } else {
seq_printf(m, "Current sequence: hws uninitialized\n"); seq_printf(m, "Current sequence: hws uninitialized\n");
} }
......
drivers/gpu/drm/i915/i915_dma.c
View file @ 78501eac
...@@ -131,9 +131,9 @@ static int i915_dma_cleanup(struct drm_device * dev) ...@@ -131,9 +131,9 @@ static int i915_dma_cleanup(struct drm_device * dev)
drm_irq_uninstall(dev); drm_irq_uninstall(dev);
mutex_lock(&dev->struct_mutex); mutex_lock(&dev->struct_mutex);
intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); intel_cleanup_ring_buffer(&dev_priv->render_ring);
intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); intel_cleanup_ring_buffer(&dev_priv->bsd_ring);
intel_cleanup_ring_buffer(dev, &dev_priv->blt_ring); intel_cleanup_ring_buffer(&dev_priv->blt_ring);
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
/* Clear the HWS virtual address at teardown */ /* Clear the HWS virtual address at teardown */
...@@ -221,7 +221,7 @@ static int i915_dma_resume(struct drm_device * dev) ...@@ -221,7 +221,7 @@ static int i915_dma_resume(struct drm_device * dev)
DRM_DEBUG_DRIVER("hw status page @ %p\n", DRM_DEBUG_DRIVER("hw status page @ %p\n",
ring->status_page.page_addr); ring->status_page.page_addr);
if (ring->status_page.gfx_addr != 0) if (ring->status_page.gfx_addr != 0)
intel_ring_setup_status_page(dev, ring); intel_ring_setup_status_page(ring);
else else
I915_WRITE(HWS_PGA, dev_priv->dma_status_page); I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
...@@ -567,7 +567,7 @@ static int i915_quiescent(struct drm_device * dev) ...@@ -567,7 +567,7 @@ static int i915_quiescent(struct drm_device * dev)
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
i915_kernel_lost_context(dev); i915_kernel_lost_context(dev);
return intel_wait_ring_buffer(dev, &dev_priv->render_ring, return intel_wait_ring_buffer(&dev_priv->render_ring,
dev_priv->render_ring.size - 8); dev_priv->render_ring.size - 8);
} }
......
drivers/gpu/drm/i915/i915_drv.c
View file @ 78501eac
...@@ -473,7 +473,7 @@ int i915_reset(struct drm_device *dev, u8 flags) ...@@ -473,7 +473,7 @@ int i915_reset(struct drm_device *dev, u8 flags)
!dev_priv->mm.suspended) { !dev_priv->mm.suspended) {
struct intel_ring_buffer *ring = &dev_priv->render_ring; struct intel_ring_buffer *ring = &dev_priv->render_ring;
dev_priv->mm.suspended = 0; dev_priv->mm.suspended = 0;
ring->init(dev, ring); ring->init(ring);
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
drm_irq_uninstall(dev); drm_irq_uninstall(dev);
drm_irq_install(dev); drm_irq_install(dev);
......
drivers/gpu/drm/i915/i915_drv.h
View file @ 78501eac
...@@ -1222,7 +1222,7 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, ...@@ -1222,7 +1222,7 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg,
drm_i915_private_t *dev_priv__ = dev->dev_private; \ drm_i915_private_t *dev_priv__ = dev->dev_private; \
if (I915_VERBOSE) \ if (I915_VERBOSE) \
DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \ DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \
intel_ring_begin(dev, &dev_priv__->render_ring, (n)); \ intel_ring_begin(&dev_priv__->render_ring, (n)); \
} while (0) } while (0)
...@@ -1230,7 +1230,7 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, ...@@ -1230,7 +1230,7 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg,
drm_i915_private_t *dev_priv__ = dev->dev_private; \ drm_i915_private_t *dev_priv__ = dev->dev_private; \
if (I915_VERBOSE) \ if (I915_VERBOSE) \
DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \ DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \
intel_ring_emit(dev, &dev_priv__->render_ring, x); \ intel_ring_emit(&dev_priv__->render_ring, x); \
} while (0) } while (0)
#define ADVANCE_LP_RING() do { \ #define ADVANCE_LP_RING() do { \
...@@ -1238,7 +1238,7 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg, ...@@ -1238,7 +1238,7 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg,
if (I915_VERBOSE) \ if (I915_VERBOSE) \
DRM_DEBUG("ADVANCE_LP_RING %x\n", \ DRM_DEBUG("ADVANCE_LP_RING %x\n", \
dev_priv__->render_ring.tail); \ dev_priv__->render_ring.tail); \
intel_ring_advance(dev, &dev_priv__->render_ring); \ intel_ring_advance(&dev_priv__->render_ring); \
} while(0) } while(0)
/** /**
......
drivers/gpu/drm/i915/i915_gem.c
View file @ 78501eac
...@@ -1703,7 +1703,7 @@ i915_add_request(struct drm_device *dev, ...@@ -1703,7 +1703,7 @@ i915_add_request(struct drm_device *dev,
return 0; return 0;
} }
seqno = ring->add_request(dev, ring, 0); seqno = ring->add_request(ring, 0);
ring->outstanding_lazy_request = false; ring->outstanding_lazy_request = false;
request->seqno = seqno; request->seqno = seqno;
...@@ -1745,8 +1745,7 @@ i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) ...@@ -1745,8 +1745,7 @@ i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
if (INTEL_INFO(dev)->gen >= 4) if (INTEL_INFO(dev)->gen >= 4)
flush_domains |= I915_GEM_DOMAIN_SAMPLER; flush_domains |= I915_GEM_DOMAIN_SAMPLER;
ring->flush(dev, ring, ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains);
I915_GEM_DOMAIN_COMMAND, flush_domains);
} }
static inline void static inline void
...@@ -1853,7 +1852,7 @@ i915_gem_retire_requests_ring(struct drm_device *dev, ...@@ -1853,7 +1852,7 @@ i915_gem_retire_requests_ring(struct drm_device *dev,
WARN_ON(i915_verify_lists(dev)); WARN_ON(i915_verify_lists(dev));
seqno = ring->get_seqno(dev, ring); seqno = ring->get_seqno(ring);
while (!list_empty(&ring->request_list)) { while (!list_empty(&ring->request_list)) {
struct drm_i915_gem_request *request; struct drm_i915_gem_request *request;
...@@ -1894,7 +1893,7 @@ i915_gem_retire_requests_ring(struct drm_device *dev, ...@@ -1894,7 +1893,7 @@ i915_gem_retire_requests_ring(struct drm_device *dev,
if (unlikely (dev_priv->trace_irq_seqno && if (unlikely (dev_priv->trace_irq_seqno &&
i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
ring->user_irq_put(dev, ring); ring->user_irq_put(ring);
dev_priv->trace_irq_seqno = 0; dev_priv->trace_irq_seqno = 0;
} }
...@@ -1971,7 +1970,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno, ...@@ -1971,7 +1970,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
} }
BUG_ON(seqno == dev_priv->next_seqno); BUG_ON(seqno == dev_priv->next_seqno);
if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
if (HAS_PCH_SPLIT(dev)) if (HAS_PCH_SPLIT(dev))
ier = I915_READ(DEIER) | I915_READ(GTIER); ier = I915_READ(DEIER) | I915_READ(GTIER);
else else
...@@ -1986,19 +1985,17 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno, ...@@ -1986,19 +1985,17 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
trace_i915_gem_request_wait_begin(dev, seqno); trace_i915_gem_request_wait_begin(dev, seqno);
ring->waiting_gem_seqno = seqno; ring->waiting_gem_seqno = seqno;
ring->user_irq_get(dev, ring); ring->user_irq_get(ring);
if (interruptible) if (interruptible)
ret = wait_event_interruptible(ring->irq_queue, ret = wait_event_interruptible(ring->irq_queue,
i915_seqno_passed( i915_seqno_passed(ring->get_seqno(ring), seqno)
ring->get_seqno(dev, ring), seqno)
|| atomic_read(&dev_priv->mm.wedged)); || atomic_read(&dev_priv->mm.wedged));
else else
wait_event(ring->irq_queue, wait_event(ring->irq_queue,
i915_seqno_passed( i915_seqno_passed(ring->get_seqno(ring), seqno)
ring->get_seqno(dev, ring), seqno)
|| atomic_read(&dev_priv->mm.wedged)); || atomic_read(&dev_priv->mm.wedged));
ring->user_irq_put(dev, ring); ring->user_irq_put(ring);
ring->waiting_gem_seqno = 0; ring->waiting_gem_seqno = 0;
trace_i915_gem_request_wait_end(dev, seqno); trace_i915_gem_request_wait_end(dev, seqno);
...@@ -2008,7 +2005,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno, ...@@ -2008,7 +2005,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
if (ret && ret != -ERESTARTSYS) if (ret && ret != -ERESTARTSYS)
DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
__func__, ret, seqno, ring->get_seqno(dev, ring), __func__, ret, seqno, ring->get_seqno(ring),
dev_priv->next_seqno); dev_priv->next_seqno);
/* Directly dispatch request retiring. While we have the work queue /* Directly dispatch request retiring. While we have the work queue
...@@ -2040,7 +2037,7 @@ i915_gem_flush_ring(struct drm_device *dev, ...@@ -2040,7 +2037,7 @@ i915_gem_flush_ring(struct drm_device *dev,
uint32_t invalidate_domains, uint32_t invalidate_domains,
uint32_t flush_domains) uint32_t flush_domains)
{ {
ring->flush(dev, ring, invalidate_domains, flush_domains); ring->flush(ring, invalidate_domains, flush_domains);
i915_gem_process_flushing_list(dev, flush_domains, ring); i915_gem_process_flushing_list(dev, flush_domains, ring);
} }
...@@ -3532,17 +3529,17 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) ...@@ -3532,17 +3529,17 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
return 0; return 0;
ret = 0; ret = 0;
if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
/* And wait for the seqno passing without holding any locks and /* And wait for the seqno passing without holding any locks and
* causing extra latency for others. This is safe as the irq * causing extra latency for others. This is safe as the irq
* generation is designed to be run atomically and so is * generation is designed to be run atomically and so is
* lockless. * lockless.
*/ */
ring->user_irq_get(dev, ring); ring->user_irq_get(ring);
ret = wait_event_interruptible(ring->irq_queue, ret = wait_event_interruptible(ring->irq_queue,
i915_seqno_passed(ring->get_seqno(dev, ring), seqno) i915_seqno_passed(ring->get_seqno(ring), seqno)
|| atomic_read(&dev_priv->mm.wedged)); || atomic_read(&dev_priv->mm.wedged));
ring->user_irq_put(dev, ring); ring->user_irq_put(ring);
if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
ret = -EIO; ret = -EIO;
...@@ -3829,17 +3826,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, ...@@ -3829,17 +3826,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
else else
flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
intel_ring_begin(dev, ring, 2); intel_ring_begin(ring, 2);
intel_ring_emit(dev, ring, intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
MI_WAIT_FOR_EVENT | flip_mask); intel_ring_emit(ring, MI_NOOP);
intel_ring_emit(dev, ring, MI_NOOP); intel_ring_advance(ring);
intel_ring_advance(dev, ring);
} }
} }
/* Exec the batchbuffer */ /* Exec the batchbuffer */
ret = ring->dispatch_gem_execbuffer(dev, ring, args, ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset);
cliprects, exec_offset);
if (ret) { if (ret) {
DRM_ERROR("dispatch failed %d\n", ret); DRM_ERROR("dispatch failed %d\n", ret);
goto err; goto err;
...@@ -4520,9 +4515,9 @@ i915_gem_init_ringbuffer(struct drm_device *dev) ...@@ -4520,9 +4515,9 @@ i915_gem_init_ringbuffer(struct drm_device *dev)
return 0; return 0;
cleanup_bsd_ring: cleanup_bsd_ring:
intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); intel_cleanup_ring_buffer(&dev_priv->bsd_ring);
cleanup_render_ring: cleanup_render_ring:
intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); intel_cleanup_ring_buffer(&dev_priv->render_ring);
cleanup_pipe_control: cleanup_pipe_control:
if (HAS_PIPE_CONTROL(dev)) if (HAS_PIPE_CONTROL(dev))
i915_gem_cleanup_pipe_control(dev); i915_gem_cleanup_pipe_control(dev);
...@@ -4534,9 +4529,9 @@ i915_gem_cleanup_ringbuffer(struct drm_device *dev) ...@@ -4534,9 +4529,9 @@ i915_gem_cleanup_ringbuffer(struct drm_device *dev)
{ {
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); intel_cleanup_ring_buffer(&dev_priv->render_ring);
intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); intel_cleanup_ring_buffer(&dev_priv->bsd_ring);
intel_cleanup_ring_buffer(dev, &dev_priv->blt_ring); intel_cleanup_ring_buffer(&dev_priv->blt_ring);
if (HAS_PIPE_CONTROL(dev)) if (HAS_PIPE_CONTROL(dev))
i915_gem_cleanup_pipe_control(dev); i915_gem_cleanup_pipe_control(dev);
} }
......
drivers/gpu/drm/i915/i915_irq.c
View file @ 78501eac
...@@ -297,7 +297,7 @@ static void notify_ring(struct drm_device *dev, ...@@ -297,7 +297,7 @@ static void notify_ring(struct drm_device *dev,
struct intel_ring_buffer *ring) struct intel_ring_buffer *ring)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
u32 seqno = ring->get_seqno(dev, ring); u32 seqno = ring->get_seqno(ring);
ring->irq_gem_seqno = seqno; ring->irq_gem_seqno = seqno;
trace_i915_gem_request_complete(dev, seqno); trace_i915_gem_request_complete(dev, seqno);
wake_up_all(&ring->irq_queue); wake_up_all(&ring->irq_queue);
...@@ -586,7 +586,7 @@ static void i915_capture_error_state(struct drm_device *dev) ...@@ -586,7 +586,7 @@ static void i915_capture_error_state(struct drm_device *dev)
DRM_DEBUG_DRIVER("generating error event\n"); DRM_DEBUG_DRIVER("generating error event\n");
error->seqno = error->seqno =
dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring); dev_priv->render_ring.get_seqno(&dev_priv->render_ring);
error->eir = I915_READ(EIR); error->eir = I915_READ(EIR);
error->pgtbl_er = I915_READ(PGTBL_ER); error->pgtbl_er = I915_READ(PGTBL_ER);
error->pipeastat = I915_READ(PIPEASTAT); error->pipeastat = I915_READ(PIPEASTAT);
...@@ -1117,7 +1117,7 @@ void i915_trace_irq_get(struct drm_device *dev, u32 seqno) ...@@ -1117,7 +1117,7 @@ void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
struct intel_ring_buffer *render_ring = &dev_priv->render_ring; struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
if (dev_priv->trace_irq_seqno == 0) if (dev_priv->trace_irq_seqno == 0)
render_ring->user_irq_get(dev, render_ring); render_ring->user_irq_get(render_ring);
dev_priv->trace_irq_seqno = seqno; dev_priv->trace_irq_seqno = seqno;
} }
...@@ -1141,10 +1141,10 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr) ...@@ -1141,10 +1141,10 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr)
if (master_priv->sarea_priv) if (master_priv->sarea_priv)
master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
render_ring->user_irq_get(dev, render_ring); render_ring->user_irq_get(render_ring);
DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ, DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
READ_BREADCRUMB(dev_priv) >= irq_nr); READ_BREADCRUMB(dev_priv) >= irq_nr);
render_ring->user_irq_put(dev, render_ring); render_ring->user_irq_put(render_ring);
if (ret == -EBUSY) { if (ret == -EBUSY) {
DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
...@@ -1338,7 +1338,7 @@ void i915_hangcheck_elapsed(unsigned long data) ...@@ -1338,7 +1338,7 @@ void i915_hangcheck_elapsed(unsigned long data)
/* If all work is done then ACTHD clearly hasn't advanced. */ /* If all work is done then ACTHD clearly hasn't advanced. */
if (list_empty(&dev_priv->render_ring.request_list) || if (list_empty(&dev_priv->render_ring.request_list) ||
i915_seqno_passed(dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring), i915_seqno_passed(dev_priv->render_ring.get_seqno(&dev_priv->render_ring),
i915_get_tail_request(dev)->seqno)) { i915_get_tail_request(dev)->seqno)) {
bool missed_wakeup = false; bool missed_wakeup = false;
......
drivers/gpu/drm/i915/intel_ringbuffer.c
View file @ 78501eac
...@@ -49,11 +49,11 @@ static u32 i915_gem_get_seqno(struct drm_device *dev) ...@@ -49,11 +49,11 @@ static u32 i915_gem_get_seqno(struct drm_device *dev)
} }
static void static void
render_ring_flush(struct drm_device *dev, render_ring_flush(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring,
u32 invalidate_domains, u32 invalidate_domains,
u32 flush_domains) u32 flush_domains)
{ {
struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
u32 cmd; u32 cmd;
...@@ -112,43 +112,39 @@ render_ring_flush(struct drm_device *dev, ...@@ -112,43 +112,39 @@ render_ring_flush(struct drm_device *dev,
#if WATCH_EXEC #if WATCH_EXEC
DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
#endif #endif
intel_ring_begin(dev, ring, 2); intel_ring_begin(ring, 2);
intel_ring_emit(dev, ring, cmd); intel_ring_emit(ring, cmd);
intel_ring_emit(dev, ring, MI_NOOP); intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(dev, ring); intel_ring_advance(ring);
} }
} }
static void ring_write_tail(struct drm_device *dev, static void ring_write_tail(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring,
u32 value) u32 value)
{ {
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = ring->dev->dev_private;
I915_WRITE_TAIL(ring, value); I915_WRITE_TAIL(ring, value);
} }
u32 intel_ring_get_active_head(struct drm_device *dev, u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = ring->dev->dev_private;
u32 acthd_reg = INTEL_INFO(dev)->gen >= 4 ? u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
RING_ACTHD(ring->mmio_base) : ACTHD; RING_ACTHD(ring->mmio_base) : ACTHD;
return I915_READ(acthd_reg); return I915_READ(acthd_reg);
} }
static int init_ring_common(struct drm_device *dev, static int init_ring_common(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
drm_i915_private_t *dev_priv = ring->dev->dev_private;
struct drm_i915_gem_object *obj_priv = to_intel_bo(ring->gem_object);
u32 head; u32 head;
drm_i915_private_t *dev_priv = dev->dev_private;
struct drm_i915_gem_object *obj_priv;
obj_priv = to_intel_bo(ring->gem_object);
/* Stop the ring if it's running. */ /* Stop the ring if it's running. */
I915_WRITE_CTL(ring, 0); I915_WRITE_CTL(ring, 0);
I915_WRITE_HEAD(ring, 0); I915_WRITE_HEAD(ring, 0);
ring->write_tail(dev, ring, 0); ring->write_tail(ring, 0);
/* Initialize the ring. */ /* Initialize the ring. */
I915_WRITE_START(ring, obj_priv->gtt_offset); I915_WRITE_START(ring, obj_priv->gtt_offset);
...@@ -192,8 +188,8 @@ static int init_ring_common(struct drm_device *dev, ...@@ -192,8 +188,8 @@ static int init_ring_common(struct drm_device *dev,
return -EIO; return -EIO;
} }
if (!drm_core_check_feature(dev, DRIVER_MODESET)) if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
i915_kernel_lost_context(dev); i915_kernel_lost_context(ring->dev);
else { else {
ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
...@@ -204,29 +200,29 @@ static int init_ring_common(struct drm_device *dev, ...@@ -204,29 +200,29 @@ static int init_ring_common(struct drm_device *dev,
return 0; return 0;
} }
static int init_render_ring(struct drm_device *dev, static int init_render_ring(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
drm_i915_private_t *dev_priv = dev->dev_private; struct drm_device *dev = ring->dev;
int ret = init_ring_common(dev, ring); int ret = init_ring_common(ring);
int mode;
if (INTEL_INFO(dev)->gen > 3) { if (INTEL_INFO(dev)->gen > 3) {
mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; drm_i915_private_t *dev_priv = dev->dev_private;
int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
if (IS_GEN6(dev)) if (IS_GEN6(dev))
mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
I915_WRITE(MI_MODE, mode); I915_WRITE(MI_MODE, mode);
} }
return ret; return ret;
} }
#define PIPE_CONTROL_FLUSH(addr) \ #define PIPE_CONTROL_FLUSH(ring__, addr__) \
do { \ do { \
OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \ intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
PIPE_CONTROL_DEPTH_STALL | 2); \ PIPE_CONTROL_DEPTH_STALL | 2); \
OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT); \ intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
OUT_RING(0); \ intel_ring_emit(ring__, 0); \
OUT_RING(0); \ intel_ring_emit(ring__, 0); \
} while (0) } while (0)
/** /**
...@@ -238,26 +234,26 @@ do { \ ...@@ -238,26 +234,26 @@ do { \
* Returned sequence numbers are nonzero on success. * Returned sequence numbers are nonzero on success.
*/ */
static u32 static u32
render_ring_add_request(struct drm_device *dev, render_ring_add_request(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring,
u32 flush_domains) u32 flush_domains)
{ {
struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
u32 seqno; u32 seqno;
seqno = i915_gem_get_seqno(dev); seqno = i915_gem_get_seqno(dev);
if (IS_GEN6(dev)) { if (IS_GEN6(dev)) {
BEGIN_LP_RING(6); intel_ring_begin(ring, 6);
OUT_RING(GFX_OP_PIPE_CONTROL | 3); intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | 3);
OUT_RING(PIPE_CONTROL_QW_WRITE | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH |
PIPE_CONTROL_NOTIFY); PIPE_CONTROL_NOTIFY);
OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
OUT_RING(seqno); intel_ring_emit(ring, seqno);
OUT_RING(0); intel_ring_emit(ring, 0);
OUT_RING(0); intel_ring_emit(ring, 0);
ADVANCE_LP_RING(); intel_ring_advance(ring);
} else if (HAS_PIPE_CONTROL(dev)) { } else if (HAS_PIPE_CONTROL(dev)) {
u32 scratch_addr = dev_priv->seqno_gfx_addr + 128; u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
...@@ -266,46 +262,46 @@ render_ring_add_request(struct drm_device *dev, ...@@ -266,46 +262,46 @@ render_ring_add_request(struct drm_device *dev,
* PIPE_NOTIFY buffers out to memory before requesting * PIPE_NOTIFY buffers out to memory before requesting
* an interrupt. * an interrupt.
*/ */
BEGIN_LP_RING(32); intel_ring_begin(ring, 32);
OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
OUT_RING(seqno); intel_ring_emit(ring, seqno);
OUT_RING(0); intel_ring_emit(ring, 0);
PIPE_CONTROL_FLUSH(scratch_addr); PIPE_CONTROL_FLUSH(ring, scratch_addr);
scratch_addr += 128; /* write to separate cachelines */ scratch_addr += 128; /* write to separate cachelines */
PIPE_CONTROL_FLUSH(scratch_addr); PIPE_CONTROL_FLUSH(ring, scratch_addr);
scratch_addr += 128; scratch_addr += 128;
PIPE_CONTROL_FLUSH(scratch_addr); PIPE_CONTROL_FLUSH(ring, scratch_addr);
scratch_addr += 128; scratch_addr += 128;
PIPE_CONTROL_FLUSH(scratch_addr); PIPE_CONTROL_FLUSH(ring, scratch_addr);
scratch_addr += 128; scratch_addr += 128;
PIPE_CONTROL_FLUSH(scratch_addr); PIPE_CONTROL_FLUSH(ring, scratch_addr);
scratch_addr += 128; scratch_addr += 128;
PIPE_CONTROL_FLUSH(scratch_addr); PIPE_CONTROL_FLUSH(ring, scratch_addr);
OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
PIPE_CONTROL_NOTIFY); PIPE_CONTROL_NOTIFY);
OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
OUT_RING(seqno); intel_ring_emit(ring, seqno);
OUT_RING(0); intel_ring_emit(ring, 0);
ADVANCE_LP_RING(); intel_ring_advance(ring);
} else { } else {
BEGIN_LP_RING(4); intel_ring_begin(ring, 4);
OUT_RING(MI_STORE_DWORD_INDEX); intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
OUT_RING(seqno); intel_ring_emit(ring, seqno);
OUT_RING(MI_USER_INTERRUPT); intel_ring_emit(ring, MI_USER_INTERRUPT);
ADVANCE_LP_RING(); intel_ring_advance(ring);
} }
return seqno; return seqno;
} }
static u32 static u32
render_ring_get_seqno(struct drm_device *dev, render_ring_get_seqno(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
if (HAS_PIPE_CONTROL(dev)) if (HAS_PIPE_CONTROL(dev))
return ((volatile u32 *)(dev_priv->seqno_page))[0]; return ((volatile u32 *)(dev_priv->seqno_page))[0];
...@@ -314,9 +310,9 @@ render_ring_get_seqno(struct drm_device *dev, ...@@ -314,9 +310,9 @@ render_ring_get_seqno(struct drm_device *dev,
} }
static void static void
render_ring_get_user_irq(struct drm_device *dev, render_ring_get_user_irq(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
unsigned long irqflags; unsigned long irqflags;
...@@ -331,9 +327,9 @@ render_ring_get_user_irq(struct drm_device *dev, ...@@ -331,9 +327,9 @@ render_ring_get_user_irq(struct drm_device *dev,
} }
static void static void
render_ring_put_user_irq(struct drm_device *dev, render_ring_put_user_irq(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
unsigned long irqflags; unsigned long irqflags;
...@@ -348,56 +344,41 @@ render_ring_put_user_irq(struct drm_device *dev, ...@@ -348,56 +344,41 @@ render_ring_put_user_irq(struct drm_device *dev,
spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
} }
void intel_ring_setup_status_page(struct drm_device *dev, void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = ring->dev->dev_private;
if (IS_GEN6(dev)) { u32 mmio = IS_GEN6(ring->dev) ?
I915_WRITE(RING_HWS_PGA_GEN6(ring->mmio_base), RING_HWS_PGA_GEN6(ring->mmio_base) :
ring->status_page.gfx_addr); RING_HWS_PGA(ring->mmio_base);
I915_READ(RING_HWS_PGA_GEN6(ring->mmio_base)); /* posting read */ I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
} else { POSTING_READ(mmio);
I915_WRITE(RING_HWS_PGA(ring->mmio_base),
ring->status_page.gfx_addr);
I915_READ(RING_HWS_PGA(ring->mmio_base)); /* posting read */
}
} }
static void static void
bsd_ring_flush(struct drm_device *dev, bsd_ring_flush(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring,
u32 invalidate_domains, u32 invalidate_domains,
u32 flush_domains) u32 flush_domains)
{ {
intel_ring_begin(dev, ring, 2); intel_ring_begin(ring, 2);
intel_ring_emit(dev, ring, MI_FLUSH); intel_ring_emit(ring, MI_FLUSH);
intel_ring_emit(dev, ring, MI_NOOP); intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(dev, ring); intel_ring_advance(ring);
}
static int init_bsd_ring(struct drm_device *dev,
struct intel_ring_buffer *ring)
{
return init_ring_common(dev, ring);
} }
static u32 static u32
ring_add_request(struct drm_device *dev, ring_add_request(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring,
u32 flush_domains) u32 flush_domains)
{ {
u32 seqno; u32 seqno;
seqno = i915_gem_get_seqno(dev); seqno = i915_gem_get_seqno(ring->dev);
intel_ring_begin(dev, ring, 4); intel_ring_begin(ring, 4);
intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX); intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
intel_ring_emit(dev, ring, intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); intel_ring_emit(ring, seqno);
intel_ring_emit(dev, ring, seqno); intel_ring_emit(ring, MI_USER_INTERRUPT);
intel_ring_emit(dev, ring, MI_USER_INTERRUPT); intel_ring_advance(ring);
intel_ring_advance(dev, ring);
DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno); DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
...@@ -405,53 +386,55 @@ ring_add_request(struct drm_device *dev, ...@@ -405,53 +386,55 @@ ring_add_request(struct drm_device *dev,
} }
static void static void
bsd_ring_get_user_irq(struct drm_device *dev, bsd_ring_get_user_irq(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
/* do nothing */ /* do nothing */
} }
static void static void
bsd_ring_put_user_irq(struct drm_device *dev, bsd_ring_put_user_irq(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
/* do nothing */ /* do nothing */
} }
static u32 static u32
ring_status_page_get_seqno(struct drm_device *dev, ring_status_page_get_seqno(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
return intel_read_status_page(ring, I915_GEM_HWS_INDEX); return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
} }
static int static int
ring_dispatch_gem_execbuffer(struct drm_device *dev, ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring,
struct drm_i915_gem_execbuffer2 *exec, struct drm_i915_gem_execbuffer2 *exec,
struct drm_clip_rect *cliprects, struct drm_clip_rect *cliprects,
uint64_t exec_offset) uint64_t exec_offset)
{ {
uint32_t exec_start; uint32_t exec_start;
exec_start = (uint32_t) exec_offset + exec->batch_start_offset; exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
intel_ring_begin(dev, ring, 2);
intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START | intel_ring_begin(ring, 2);
(2 << 6) | MI_BATCH_NON_SECURE_I965); intel_ring_emit(ring,
intel_ring_emit(dev, ring, exec_start); MI_BATCH_BUFFER_START |
intel_ring_advance(dev, ring); (2 << 6) |
MI_BATCH_NON_SECURE_I965);
intel_ring_emit(ring, exec_start);
intel_ring_advance(ring);
return 0; return 0;
} }
static int static int
render_ring_dispatch_gem_execbuffer(struct drm_device *dev, render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring,
struct drm_i915_gem_execbuffer2 *exec, struct drm_i915_gem_execbuffer2 *exec,
struct drm_clip_rect *cliprects, struct drm_clip_rect *cliprects,
uint64_t exec_offset) uint64_t exec_offset)
{ {
struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
int nbox = exec->num_cliprects; int nbox = exec->num_cliprects;
int i = 0, count; int i = 0, count;
uint32_t exec_start, exec_len; uint32_t exec_start, exec_len;
exec_start = (uint32_t) exec_offset + exec->batch_start_offset; exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
exec_len = (uint32_t) exec->batch_len; exec_len = (uint32_t) exec->batch_len;
...@@ -468,46 +451,44 @@ render_ring_dispatch_gem_execbuffer(struct drm_device *dev, ...@@ -468,46 +451,44 @@ render_ring_dispatch_gem_execbuffer(struct drm_device *dev,
} }
if (IS_I830(dev) || IS_845G(dev)) { if (IS_I830(dev) || IS_845G(dev)) {
intel_ring_begin(dev, ring, 4); intel_ring_begin(ring, 4);
intel_ring_emit(dev, ring, MI_BATCH_BUFFER); intel_ring_emit(ring, MI_BATCH_BUFFER);
intel_ring_emit(dev, ring, intel_ring_emit(ring, exec_start | MI_BATCH_NON_SECURE);
exec_start | MI_BATCH_NON_SECURE); intel_ring_emit(ring, exec_start + exec_len - 4);
intel_ring_emit(dev, ring, exec_start + exec_len - 4); intel_ring_emit(ring, 0);
intel_ring_emit(dev, ring, 0);
} else { } else {
intel_ring_begin(dev, ring, 2); intel_ring_begin(ring, 2);
if (INTEL_INFO(dev)->gen >= 4) { if (INTEL_INFO(dev)->gen >= 4) {
intel_ring_emit(dev, ring, intel_ring_emit(ring,
MI_BATCH_BUFFER_START | (2 << 6) MI_BATCH_BUFFER_START | (2 << 6)
| MI_BATCH_NON_SECURE_I965); | MI_BATCH_NON_SECURE_I965);
intel_ring_emit(dev, ring, exec_start); intel_ring_emit(ring, exec_start);
} else { } else {
intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START intel_ring_emit(ring, MI_BATCH_BUFFER_START
| (2 << 6)); | (2 << 6));
intel_ring_emit(dev, ring, exec_start | intel_ring_emit(ring, exec_start |
MI_BATCH_NON_SECURE); MI_BATCH_NON_SECURE);
} }
} }
intel_ring_advance(dev, ring); intel_ring_advance(ring);
} }
if (IS_G4X(dev) || IS_GEN5(dev)) { if (IS_G4X(dev) || IS_GEN5(dev)) {
intel_ring_begin(dev, ring, 2); intel_ring_begin(ring, 2);
intel_ring_emit(dev, ring, MI_FLUSH | intel_ring_emit(ring, MI_FLUSH |
MI_NO_WRITE_FLUSH | MI_NO_WRITE_FLUSH |
MI_INVALIDATE_ISP ); MI_INVALIDATE_ISP );
intel_ring_emit(dev, ring, MI_NOOP); intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(dev, ring); intel_ring_advance(ring);
} }
/* XXX breadcrumb */ /* XXX breadcrumb */
return 0; return 0;
} }
static void cleanup_status_page(struct drm_device *dev, static void cleanup_status_page(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = ring->dev->dev_private;
struct drm_gem_object *obj; struct drm_gem_object *obj;
struct drm_i915_gem_object *obj_priv; struct drm_i915_gem_object *obj_priv;
...@@ -524,9 +505,9 @@ static void cleanup_status_page(struct drm_device *dev, ...@@ -524,9 +505,9 @@ static void cleanup_status_page(struct drm_device *dev,
memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
} }
static int init_status_page(struct drm_device *dev, static int init_status_page(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
struct drm_gem_object *obj; struct drm_gem_object *obj;
struct drm_i915_gem_object *obj_priv; struct drm_i915_gem_object *obj_priv;
...@@ -555,7 +536,7 @@ static int init_status_page(struct drm_device *dev, ...@@ -555,7 +536,7 @@ static int init_status_page(struct drm_device *dev,
ring->status_page.obj = obj; ring->status_page.obj = obj;
memset(ring->status_page.page_addr, 0, PAGE_SIZE); memset(ring->status_page.page_addr, 0, PAGE_SIZE);
intel_ring_setup_status_page(dev, ring); intel_ring_setup_status_page(ring);
DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
ring->name, ring->status_page.gfx_addr); ring->name, ring->status_page.gfx_addr);
...@@ -583,7 +564,7 @@ int intel_init_ring_buffer(struct drm_device *dev, ...@@ -583,7 +564,7 @@ int intel_init_ring_buffer(struct drm_device *dev,
INIT_LIST_HEAD(&ring->gpu_write_list); INIT_LIST_HEAD(&ring->gpu_write_list);
if (I915_NEED_GFX_HWS(dev)) { if (I915_NEED_GFX_HWS(dev)) {
ret = init_status_page(dev, ring); ret = init_status_page(ring);
if (ret) if (ret)
return ret; return ret;
} }
...@@ -616,7 +597,7 @@ int intel_init_ring_buffer(struct drm_device *dev, ...@@ -616,7 +597,7 @@ int intel_init_ring_buffer(struct drm_device *dev,
} }
ring->virtual_start = ring->map.handle; ring->virtual_start = ring->map.handle;
ret = ring->init(dev, ring); ret = ring->init(ring);
if (ret) if (ret)
goto err_unmap; goto err_unmap;
...@@ -639,33 +620,32 @@ int intel_init_ring_buffer(struct drm_device *dev, ...@@ -639,33 +620,32 @@ int intel_init_ring_buffer(struct drm_device *dev,
drm_gem_object_unreference(obj); drm_gem_object_unreference(obj);
ring->gem_object = NULL; ring->gem_object = NULL;
err_hws: err_hws:
cleanup_status_page(dev, ring); cleanup_status_page(ring);
return ret; return ret;
} }
void intel_cleanup_ring_buffer(struct drm_device *dev, void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
if (ring->gem_object == NULL) if (ring->gem_object == NULL)
return; return;
drm_core_ioremapfree(&ring->map, dev); drm_core_ioremapfree(&ring->map, ring->dev);
i915_gem_object_unpin(ring->gem_object); i915_gem_object_unpin(ring->gem_object);
drm_gem_object_unreference(ring->gem_object); drm_gem_object_unreference(ring->gem_object);
ring->gem_object = NULL; ring->gem_object = NULL;
cleanup_status_page(dev, ring);
cleanup_status_page(ring);
} }
static int intel_wrap_ring_buffer(struct drm_device *dev, static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
unsigned int *virt; unsigned int *virt;
int rem; int rem;
rem = ring->size - ring->tail; rem = ring->size - ring->tail;
if (ring->space < rem) { if (ring->space < rem) {
int ret = intel_wait_ring_buffer(dev, ring, rem); int ret = intel_wait_ring_buffer(ring, rem);
if (ret) if (ret)
return ret; return ret;
} }
...@@ -683,11 +663,11 @@ static int intel_wrap_ring_buffer(struct drm_device *dev, ...@@ -683,11 +663,11 @@ static int intel_wrap_ring_buffer(struct drm_device *dev,
return 0; return 0;
} }
int intel_wait_ring_buffer(struct drm_device *dev, int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
struct intel_ring_buffer *ring, int n)
{ {
unsigned long end; struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
unsigned long end;
trace_i915_ring_wait_begin (dev); trace_i915_ring_wait_begin (dev);
end = jiffies + 3 * HZ; end = jiffies + 3 * HZ;
...@@ -697,7 +677,7 @@ int intel_wait_ring_buffer(struct drm_device *dev, ...@@ -697,7 +677,7 @@ int intel_wait_ring_buffer(struct drm_device *dev,
if (ring->space < 0) if (ring->space < 0)
ring->space += ring->size; ring->space += ring->size;
if (ring->space >= n) { if (ring->space >= n) {
trace_i915_ring_wait_end (dev); trace_i915_ring_wait_end(dev);
return 0; return 0;
} }
...@@ -713,24 +693,24 @@ int intel_wait_ring_buffer(struct drm_device *dev, ...@@ -713,24 +693,24 @@ int intel_wait_ring_buffer(struct drm_device *dev,
return -EBUSY; return -EBUSY;
} }
void intel_ring_begin(struct drm_device *dev, void intel_ring_begin(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring,
int num_dwords) int num_dwords)
{ {
int n = 4*num_dwords; int n = 4*num_dwords;
if (unlikely(ring->tail + n > ring->size)) if (unlikely(ring->tail + n > ring->size))
intel_wrap_ring_buffer(dev, ring); intel_wrap_ring_buffer(ring);
if (unlikely(ring->space < n)) if (unlikely(ring->space < n))
intel_wait_ring_buffer(dev, ring, n); intel_wait_ring_buffer(ring, n);
ring->space -= n; ring->space -= n;
} }
void intel_ring_advance(struct drm_device *dev, void intel_ring_advance(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
ring->tail &= ring->size - 1; ring->tail &= ring->size - 1;
ring->write_tail(dev, ring, ring->tail); ring->write_tail(ring, ring->tail);
} }
static const struct intel_ring_buffer render_ring = { static const struct intel_ring_buffer render_ring = {
...@@ -745,7 +725,7 @@ static const struct intel_ring_buffer render_ring = { ...@@ -745,7 +725,7 @@ static const struct intel_ring_buffer render_ring = {
.get_seqno = render_ring_get_seqno, .get_seqno = render_ring_get_seqno,
.user_irq_get = render_ring_get_user_irq, .user_irq_get = render_ring_get_user_irq,
.user_irq_put = render_ring_put_user_irq, .user_irq_put = render_ring_put_user_irq,
.dispatch_gem_execbuffer = render_ring_dispatch_gem_execbuffer, .dispatch_execbuffer = render_ring_dispatch_execbuffer,
}; };
/* ring buffer for bit-stream decoder */ /* ring buffer for bit-stream decoder */
...@@ -755,22 +735,21 @@ static const struct intel_ring_buffer bsd_ring = { ...@@ -755,22 +735,21 @@ static const struct intel_ring_buffer bsd_ring = {
.id = RING_BSD, .id = RING_BSD,
.mmio_base = BSD_RING_BASE, .mmio_base = BSD_RING_BASE,
.size = 32 * PAGE_SIZE, .size = 32 * PAGE_SIZE,
.init = init_bsd_ring, .init = init_ring_common,
.write_tail = ring_write_tail, .write_tail = ring_write_tail,
.flush = bsd_ring_flush, .flush = bsd_ring_flush,
.add_request = ring_add_request, .add_request = ring_add_request,
.get_seqno = ring_status_page_get_seqno, .get_seqno = ring_status_page_get_seqno,
.user_irq_get = bsd_ring_get_user_irq, .user_irq_get = bsd_ring_get_user_irq,
.user_irq_put = bsd_ring_put_user_irq, .user_irq_put = bsd_ring_put_user_irq,
.dispatch_gem_execbuffer = ring_dispatch_gem_execbuffer, .dispatch_execbuffer = ring_dispatch_execbuffer,
}; };
static void gen6_bsd_ring_write_tail(struct drm_device *dev, static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring,
u32 value) u32 value)
{ {
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = ring->dev->dev_private;
/* Every tail move must follow the sequence below */ /* Every tail move must follow the sequence below */
I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
...@@ -789,22 +768,20 @@ static void gen6_bsd_ring_write_tail(struct drm_device *dev, ...@@ -789,22 +768,20 @@ static void gen6_bsd_ring_write_tail(struct drm_device *dev,
GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
} }
static void gen6_ring_flush(struct drm_device *dev, static void gen6_ring_flush(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring,
u32 invalidate_domains, u32 invalidate_domains,
u32 flush_domains) u32 flush_domains)
{ {
intel_ring_begin(dev, ring, 4); intel_ring_begin(ring, 4);
intel_ring_emit(dev, ring, MI_FLUSH_DW); intel_ring_emit(ring, MI_FLUSH_DW);
intel_ring_emit(dev, ring, 0); intel_ring_emit(ring, 0);
intel_ring_emit(dev, ring, 0); intel_ring_emit(ring, 0);
intel_ring_emit(dev, ring, 0); intel_ring_emit(ring, 0);
intel_ring_advance(dev, ring); intel_ring_advance(ring);
} }
static int static int
gen6_ring_dispatch_gem_execbuffer(struct drm_device *dev, gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring,
struct drm_i915_gem_execbuffer2 *exec, struct drm_i915_gem_execbuffer2 *exec,
struct drm_clip_rect *cliprects, struct drm_clip_rect *cliprects,
uint64_t exec_offset) uint64_t exec_offset)
...@@ -813,12 +790,11 @@ gen6_ring_dispatch_gem_execbuffer(struct drm_device *dev, ...@@ -813,12 +790,11 @@ gen6_ring_dispatch_gem_execbuffer(struct drm_device *dev,
exec_start = (uint32_t) exec_offset + exec->batch_start_offset; exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
intel_ring_begin(dev, ring, 2); intel_ring_begin(ring, 2);
intel_ring_emit(dev, ring, intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
/* bit0-7 is the length on GEN6+ */ /* bit0-7 is the length on GEN6+ */
intel_ring_emit(dev, ring, exec_start); intel_ring_emit(ring, exec_start);
intel_ring_advance(dev, ring); intel_ring_advance(ring);
return 0; return 0;
} }
...@@ -829,27 +805,25 @@ static const struct intel_ring_buffer gen6_bsd_ring = { ...@@ -829,27 +805,25 @@ static const struct intel_ring_buffer gen6_bsd_ring = {
.id = RING_BSD, .id = RING_BSD,
.mmio_base = GEN6_BSD_RING_BASE, .mmio_base = GEN6_BSD_RING_BASE,
.size = 32 * PAGE_SIZE, .size = 32 * PAGE_SIZE,
.init = init_bsd_ring, .init = init_ring_common,
.write_tail = gen6_bsd_ring_write_tail, .write_tail = gen6_bsd_ring_write_tail,
.flush = gen6_ring_flush, .flush = gen6_ring_flush,
.add_request = ring_add_request, .add_request = ring_add_request,
.get_seqno = ring_status_page_get_seqno, .get_seqno = ring_status_page_get_seqno,
.user_irq_get = bsd_ring_get_user_irq, .user_irq_get = bsd_ring_get_user_irq,
.user_irq_put = bsd_ring_put_user_irq, .user_irq_put = bsd_ring_put_user_irq,
.dispatch_gem_execbuffer = gen6_ring_dispatch_gem_execbuffer, .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
}; };
/* Blitter support (SandyBridge+) */ /* Blitter support (SandyBridge+) */
static void static void
blt_ring_get_user_irq(struct drm_device *dev, blt_ring_get_user_irq(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
/* do nothing */ /* do nothing */
} }
static void static void
blt_ring_put_user_irq(struct drm_device *dev, blt_ring_put_user_irq(struct intel_ring_buffer *ring)
struct intel_ring_buffer *ring)
{ {
/* do nothing */ /* do nothing */
} }
...@@ -866,7 +840,7 @@ static const struct intel_ring_buffer gen6_blt_ring = { ...@@ -866,7 +840,7 @@ static const struct intel_ring_buffer gen6_blt_ring = {
.get_seqno = ring_status_page_get_seqno, .get_seqno = ring_status_page_get_seqno,
.user_irq_get = blt_ring_get_user_irq, .user_irq_get = blt_ring_get_user_irq,
.user_irq_put = blt_ring_put_user_irq, .user_irq_put = blt_ring_put_user_irq,
.dispatch_gem_execbuffer = gen6_ring_dispatch_gem_execbuffer, .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
}; };
int intel_init_render_ring_buffer(struct drm_device *dev) int intel_init_render_ring_buffer(struct drm_device *dev)
......
drivers/gpu/drm/i915/intel_ringbuffer.h
View file @ 78501eac
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
#define _INTEL_RINGBUFFER_H_ #define _INTEL_RINGBUFFER_H_
struct intel_hw_status_page { struct intel_hw_status_page {
void *page_addr; u32 __iomem *page_addr;
unsigned int gfx_addr; unsigned int gfx_addr;
struct drm_gem_object *obj; struct drm_gem_object *obj;
}; };
...@@ -38,28 +38,20 @@ struct intel_ring_buffer { ...@@ -38,28 +38,20 @@ struct intel_ring_buffer {
u32 irq_gem_seqno; /* last seq seem at irq time */ u32 irq_gem_seqno; /* last seq seem at irq time */
u32 waiting_gem_seqno; u32 waiting_gem_seqno;
int user_irq_refcount; int user_irq_refcount;
void (*user_irq_get)(struct drm_device *dev, void (*user_irq_get)(struct intel_ring_buffer *ring);
struct intel_ring_buffer *ring); void (*user_irq_put)(struct intel_ring_buffer *ring);
void (*user_irq_put)(struct drm_device *dev,
struct intel_ring_buffer *ring);
int (*init)(struct drm_device *dev, int (*init)(struct intel_ring_buffer *ring);
struct intel_ring_buffer *ring);
void (*write_tail)(struct drm_device *dev, void (*write_tail)(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring,
u32 value); u32 value);
void (*flush)(struct drm_device *dev, void (*flush)(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring,
u32 invalidate_domains, u32 invalidate_domains,
u32 flush_domains); u32 flush_domains);
u32 (*add_request)(struct drm_device *dev, u32 (*add_request)(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring,
u32 flush_domains); u32 flush_domains);
u32 (*get_seqno)(struct drm_device *dev, u32 (*get_seqno)(struct intel_ring_buffer *ring);
struct intel_ring_buffer *ring); int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
int (*dispatch_gem_execbuffer)(struct drm_device *dev,
struct intel_ring_buffer *ring,
struct drm_i915_gem_execbuffer2 *exec, struct drm_i915_gem_execbuffer2 *exec,
struct drm_clip_rect *cliprects, struct drm_clip_rect *cliprects,
uint64_t exec_offset); uint64_t exec_offset);
...@@ -104,41 +96,29 @@ static inline u32 ...@@ -104,41 +96,29 @@ static inline u32
intel_read_status_page(struct intel_ring_buffer *ring, intel_read_status_page(struct intel_ring_buffer *ring,
int reg) int reg)
{ {
u32 *regs = ring->status_page.page_addr; return ioread32(ring->status_page.page_addr + reg);
return regs[reg];
} }
int intel_init_ring_buffer(struct drm_device *dev, void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
struct intel_ring_buffer *ring); int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
void intel_cleanup_ring_buffer(struct drm_device *dev, void intel_ring_begin(struct intel_ring_buffer *ring, int n);
struct intel_ring_buffer *ring);
int intel_wait_ring_buffer(struct drm_device *dev, static inline void intel_ring_emit(struct intel_ring_buffer *ring,
struct intel_ring_buffer *ring, int n); u32 data)
void intel_ring_begin(struct drm_device *dev,
struct intel_ring_buffer *ring, int n);
static inline void intel_ring_emit(struct drm_device *dev,
struct intel_ring_buffer *ring,
unsigned int data)
{ {
unsigned int *virt = ring->virtual_start + ring->tail; iowrite32(data, ring->virtual_start + ring->tail);
*virt = data;
ring->tail += 4; ring->tail += 4;
} }
void intel_ring_advance(struct drm_device *dev, void intel_ring_advance(struct intel_ring_buffer *ring);
struct intel_ring_buffer *ring);
u32 intel_ring_get_seqno(struct drm_device *dev, u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
struct intel_ring_buffer *ring);
int intel_init_render_ring_buffer(struct drm_device *dev); int intel_init_render_ring_buffer(struct drm_device *dev);
int intel_init_bsd_ring_buffer(struct drm_device *dev); int intel_init_bsd_ring_buffer(struct drm_device *dev);
int intel_init_blt_ring_buffer(struct drm_device *dev); int intel_init_blt_ring_buffer(struct drm_device *dev);
u32 intel_ring_get_active_head(struct drm_device *dev, u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
struct intel_ring_buffer *ring); void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
void intel_ring_setup_status_page(struct drm_device *dev,
struct intel_ring_buffer *ring);
#endif /* _INTEL_RINGBUFFER_H_ */ #endif /* _INTEL_RINGBUFFER_H_ */
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