Commit 79cf95c7 authored by Tuomas Tynkkynen's avatar Tuomas Tynkkynen Committed by Thierry Reding

clk: tegra: Add the DFLL as a possible parent of the cclk_g clock

The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.
Signed-off-by: default avatarTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: default avatarMikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: default avatarMichael Turquette <mturquette@linaro.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent c38864a7
...@@ -44,7 +44,9 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", ...@@ -44,7 +44,9 @@ static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
"pll_p", "pll_p_out4", "unused", "pll_p", "pll_p_out4", "unused",
"unused", "pll_x" }; "unused", "pll_x", "unused", "unused",
"unused", "unused", "unused", "unused",
"dfllCPU_out" };
static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
"pll_p", "pll_p_out4", "unused", "pll_p", "pll_p_out4", "unused",
......
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