Commit 79eee7aa authored by Ben Skeggs's avatar Ben Skeggs

drm/nvc0/ltcg: mask off intr 0x10

NVIDIA do that at startup too on Fermi, so perhaps the heap of 0x10
intrs we receive are normal and we can ignore them.

On Kepler NVIDIA *don't* do this, but the hardware appears to come up
with the bit masked off by default - so that's probably why :)

This should silence some interrupt spam seen on Fermi+ boards.

Backported patch from reworked nouveau kernel tree.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent c7ead11d
...@@ -124,6 +124,7 @@ nvc0_fb_init(struct drm_device *dev) ...@@ -124,6 +124,7 @@ nvc0_fb_init(struct drm_device *dev)
priv = dev_priv->engine.fb.priv; priv = dev_priv->engine.fb.priv;
nv_wr32(dev, 0x100c10, priv->r100c10 >> 8); nv_wr32(dev, 0x100c10, priv->r100c10 >> 8);
nv_mask(dev, 0x17e820, 0x00100000, 0x00000000); /* NV_PLTCG_INTR_EN */
return 0; return 0;
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment