Skip to content

L
linux
Commit 7acd2251 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Stephen Boyd
Browse files
Options

clk: qcom: dispcc-sdm845: convert to parent data 

Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-12-dmitry.baryshkov@linaro.orgSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 2e30f649
Hide whitespace changes
Inline Side-by-side
Showing with 109 additions and 107 deletions
drivers/clk/qcom/dispcc-sdm845.c
View file @ 7acd2251
...@@ -33,6 +33,21 @@ enum { ...@@ -33,6 +33,21 @@ enum {
P_DP_PHY_PLL_VCO_DIV_CLK, P_DP_PHY_PLL_VCO_DIV_CLK,
}; };
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
};
static const struct parent_map disp_cc_parent_map_0[] = { static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 }, { P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
...@@ -40,11 +55,11 @@ static const struct parent_map disp_cc_parent_map_0[] = { ...@@ -40,11 +55,11 @@ static const struct parent_map disp_cc_parent_map_0[] = {
{ P_CORE_BI_PLL_TEST_SE, 7 }, { P_CORE_BI_PLL_TEST_SE, 7 },
}; };
static const char * const disp_cc_parent_names_0[] = { static const struct clk_parent_data disp_cc_parent_data_0[] = {
"bi_tcxo", { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
"dsi0_phy_pll_out_byteclk", { .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" },
"dsi1_phy_pll_out_byteclk", { .fw_name = "dsi1_phy_pll_out_byteclk", .name = "dsi1_phy_pll_out_byteclk" },
"core_bi_pll_test_se", { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
}; };
static const struct parent_map disp_cc_parent_map_1[] = { static const struct parent_map disp_cc_parent_map_1[] = {
...@@ -54,11 +69,11 @@ static const struct parent_map disp_cc_parent_map_1[] = { ...@@ -54,11 +69,11 @@ static const struct parent_map disp_cc_parent_map_1[] = {
{ P_CORE_BI_PLL_TEST_SE, 7 }, { P_CORE_BI_PLL_TEST_SE, 7 },
}; };
static const char * const disp_cc_parent_names_1[] = { static const struct clk_parent_data disp_cc_parent_data_1[] = {
"bi_tcxo", { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
"dp_link_clk_divsel_ten", { .fw_name = "dp_link_clk_divsel_ten", .name = "dp_link_clk_divsel_ten" },
"dp_vco_divided_clk_src_mux", { .fw_name = "dp_vco_divided_clk_src_mux", .name = "dp_vco_divided_clk_src_mux" },
"core_bi_pll_test_se", { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
}; };
static const struct parent_map disp_cc_parent_map_2[] = { static const struct parent_map disp_cc_parent_map_2[] = {
...@@ -66,9 +81,9 @@ static const struct parent_map disp_cc_parent_map_2[] = { ...@@ -66,9 +81,9 @@ static const struct parent_map disp_cc_parent_map_2[] = {
{ P_CORE_BI_PLL_TEST_SE, 7 }, { P_CORE_BI_PLL_TEST_SE, 7 },
}; };
static const char * const disp_cc_parent_names_2[] = { static const struct clk_parent_data disp_cc_parent_data_2[] = {
"bi_tcxo", { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
"core_bi_pll_test_se", { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
}; };
static const struct parent_map disp_cc_parent_map_3[] = { static const struct parent_map disp_cc_parent_map_3[] = {
...@@ -79,12 +94,12 @@ static const struct parent_map disp_cc_parent_map_3[] = { ...@@ -79,12 +94,12 @@ static const struct parent_map disp_cc_parent_map_3[] = {
{ P_CORE_BI_PLL_TEST_SE, 7 }, { P_CORE_BI_PLL_TEST_SE, 7 },
}; };
static const char * const disp_cc_parent_names_3[] = { static const struct clk_parent_data disp_cc_parent_data_3[] = {
"bi_tcxo", { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
"disp_cc_pll0", { .hw = &disp_cc_pll0.clkr.hw },
"gcc_disp_gpll0_clk_src", { .fw_name = "gcc_disp_gpll0_clk_src", .name = "gcc_disp_gpll0_clk_src" },
"gcc_disp_gpll0_div_clk_src", { .fw_name = "gcc_disp_gpll0_div_clk_src", .name = "gcc_disp_gpll0_div_clk_src" },
"core_bi_pll_test_se", { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
}; };
static const struct parent_map disp_cc_parent_map_4[] = { static const struct parent_map disp_cc_parent_map_4[] = {
...@@ -94,24 +109,11 @@ static const struct parent_map disp_cc_parent_map_4[] = { ...@@ -94,24 +109,11 @@ static const struct parent_map disp_cc_parent_map_4[] = {
{ P_CORE_BI_PLL_TEST_SE, 7 }, { P_CORE_BI_PLL_TEST_SE, 7 },
}; };
static const char * const disp_cc_parent_names_4[] = { static const struct clk_parent_data disp_cc_parent_data_4[] = {
"bi_tcxo", { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
"dsi0_phy_pll_out_dsiclk", { .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" },
"dsi1_phy_pll_out_dsiclk", { .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" },
"core_bi_pll_test_se", { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0",
.parent_names = (const char *[]){ "bi_tcxo" },
.num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops,
},
},
}; };
/* Return the HW recalc rate for idle use case */ /* Return the HW recalc rate for idle use case */
...@@ -122,8 +124,8 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { ...@@ -122,8 +124,8 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.parent_map = disp_cc_parent_map_0, .parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src", .name = "disp_cc_mdss_byte0_clk_src",
.parent_names = disp_cc_parent_names_0, .parent_data = disp_cc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops, .ops = &clk_byte2_ops,
}, },
...@@ -137,8 +139,8 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { ...@@ -137,8 +139,8 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
.parent_map = disp_cc_parent_map_0, .parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte1_clk_src", .name = "disp_cc_mdss_byte1_clk_src",
.parent_names = disp_cc_parent_names_0, .parent_data = disp_cc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops, .ops = &clk_byte2_ops,
}, },
...@@ -157,8 +159,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { ...@@ -157,8 +159,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk_src", .name = "disp_cc_mdss_dp_aux_clk_src",
.parent_names = disp_cc_parent_names_2, .parent_data = disp_cc_parent_data_2,
.num_parents = 2, .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -171,8 +173,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { ...@@ -171,8 +173,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
.parent_map = disp_cc_parent_map_1, .parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk_src", .name = "disp_cc_mdss_dp_crypto_clk_src",
.parent_names = disp_cc_parent_names_1, .parent_data = disp_cc_parent_data_1,
.num_parents = 4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.ops = &clk_byte2_ops, .ops = &clk_byte2_ops,
}, },
}; };
...@@ -184,8 +186,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { ...@@ -184,8 +186,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
.parent_map = disp_cc_parent_map_1, .parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk_src", .name = "disp_cc_mdss_dp_link_clk_src",
.parent_names = disp_cc_parent_names_1, .parent_data = disp_cc_parent_data_1,
.num_parents = 4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops, .ops = &clk_byte2_ops,
}, },
...@@ -198,8 +200,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { ...@@ -198,8 +200,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
.parent_map = disp_cc_parent_map_1, .parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel1_clk_src", .name = "disp_cc_mdss_dp_pixel1_clk_src",
.parent_names = disp_cc_parent_names_1, .parent_data = disp_cc_parent_data_1,
.num_parents = 4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops, .ops = &clk_dp_ops,
}, },
...@@ -212,8 +214,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { ...@@ -212,8 +214,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
.parent_map = disp_cc_parent_map_1, .parent_map = disp_cc_parent_map_1,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk_src", .name = "disp_cc_mdss_dp_pixel_clk_src",
.parent_names = disp_cc_parent_names_1, .parent_data = disp_cc_parent_data_1,
.num_parents = 4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_dp_ops, .ops = &clk_dp_ops,
}, },
...@@ -232,8 +234,8 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { ...@@ -232,8 +234,8 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src", .name = "disp_cc_mdss_esc0_clk_src",
.parent_names = disp_cc_parent_names_0, .parent_data = disp_cc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -246,8 +248,8 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { ...@@ -246,8 +248,8 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc1_clk_src", .name = "disp_cc_mdss_esc1_clk_src",
.parent_names = disp_cc_parent_names_0, .parent_data = disp_cc_parent_data_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -273,8 +275,8 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { ...@@ -273,8 +275,8 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src", .name = "disp_cc_mdss_mdp_clk_src",
.parent_names = disp_cc_parent_names_3, .parent_data = disp_cc_parent_data_3,
.num_parents = 5, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
}; };
...@@ -287,8 +289,8 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { ...@@ -287,8 +289,8 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.parent_map = disp_cc_parent_map_4, .parent_map = disp_cc_parent_map_4,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src", .name = "disp_cc_mdss_pclk0_clk_src",
.parent_names = disp_cc_parent_names_4, .parent_data = disp_cc_parent_data_4,
.num_parents = 4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops, .ops = &clk_pixel_ops,
}, },
...@@ -302,8 +304,8 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { ...@@ -302,8 +304,8 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
.parent_map = disp_cc_parent_map_4, .parent_map = disp_cc_parent_map_4,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk1_clk_src", .name = "disp_cc_mdss_pclk1_clk_src",
.parent_names = disp_cc_parent_names_4, .parent_data = disp_cc_parent_data_4,
.num_parents = 4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops, .ops = &clk_pixel_ops,
}, },
...@@ -326,8 +328,8 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { ...@@ -326,8 +328,8 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk_src", .name = "disp_cc_mdss_rot_clk_src",
.parent_names = disp_cc_parent_names_3, .parent_data = disp_cc_parent_data_3,
.num_parents = 5, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
}; };
...@@ -340,8 +342,8 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { ...@@ -340,8 +342,8 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src", .name = "disp_cc_mdss_vsync_clk_src",
.parent_names = disp_cc_parent_names_2, .parent_data = disp_cc_parent_data_2,
.num_parents = 2, .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -381,8 +383,8 @@ static struct clk_branch disp_cc_mdss_byte0_clk = { ...@@ -381,8 +383,8 @@ static struct clk_branch disp_cc_mdss_byte0_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk", .name = "disp_cc_mdss_byte0_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_byte0_clk_src", &disp_cc_mdss_byte0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -399,8 +401,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { ...@@ -399,8 +401,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.clkr = { .clkr = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_div_clk_src", .name = "disp_cc_mdss_byte0_div_clk_src",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_byte0_clk_src", &disp_cc_mdss_byte0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_regmap_div_ops, .ops = &clk_regmap_div_ops,
...@@ -417,8 +419,8 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = { ...@@ -417,8 +419,8 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_intf_clk", .name = "disp_cc_mdss_byte0_intf_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_byte0_div_clk_src", &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -436,8 +438,8 @@ static struct clk_branch disp_cc_mdss_byte1_clk = { ...@@ -436,8 +438,8 @@ static struct clk_branch disp_cc_mdss_byte1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte1_clk", .name = "disp_cc_mdss_byte1_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_byte1_clk_src", &disp_cc_mdss_byte1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -454,8 +456,8 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { ...@@ -454,8 +456,8 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
.clkr = { .clkr = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte1_div_clk_src", .name = "disp_cc_mdss_byte1_div_clk_src",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_byte1_clk_src", &disp_cc_mdss_byte1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_regmap_div_ops, .ops = &clk_regmap_div_ops,
...@@ -472,8 +474,8 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = { ...@@ -472,8 +474,8 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte1_intf_clk", .name = "disp_cc_mdss_byte1_intf_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_byte1_div_clk_src", &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -490,8 +492,8 @@ static struct clk_branch disp_cc_mdss_dp_aux_clk = { ...@@ -490,8 +492,8 @@ static struct clk_branch disp_cc_mdss_dp_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_aux_clk", .name = "disp_cc_mdss_dp_aux_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_dp_aux_clk_src", &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -508,8 +510,8 @@ static struct clk_branch disp_cc_mdss_dp_crypto_clk = { ...@@ -508,8 +510,8 @@ static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_crypto_clk", .name = "disp_cc_mdss_dp_crypto_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_dp_crypto_clk_src", &disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -526,8 +528,8 @@ static struct clk_branch disp_cc_mdss_dp_link_clk = { ...@@ -526,8 +528,8 @@ static struct clk_branch disp_cc_mdss_dp_link_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_clk", .name = "disp_cc_mdss_dp_link_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_dp_link_clk_src", &disp_cc_mdss_dp_link_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -545,8 +547,8 @@ static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { ...@@ -545,8 +547,8 @@ static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_link_intf_clk", .name = "disp_cc_mdss_dp_link_intf_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_dp_link_clk_src", &disp_cc_mdss_dp_link_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_branch2_ops, .ops = &clk_branch2_ops,
...@@ -562,8 +564,8 @@ static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { ...@@ -562,8 +564,8 @@ static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel1_clk", .name = "disp_cc_mdss_dp_pixel1_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_dp_pixel1_clk_src", &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -580,8 +582,8 @@ static struct clk_branch disp_cc_mdss_dp_pixel_clk = { ...@@ -580,8 +582,8 @@ static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_dp_pixel_clk", .name = "disp_cc_mdss_dp_pixel_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_dp_pixel_clk_src", &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -598,8 +600,8 @@ static struct clk_branch disp_cc_mdss_esc0_clk = { ...@@ -598,8 +600,8 @@ static struct clk_branch disp_cc_mdss_esc0_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk", .name = "disp_cc_mdss_esc0_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_esc0_clk_src", &disp_cc_mdss_esc0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -616,8 +618,8 @@ static struct clk_branch disp_cc_mdss_esc1_clk = { ...@@ -616,8 +618,8 @@ static struct clk_branch disp_cc_mdss_esc1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc1_clk", .name = "disp_cc_mdss_esc1_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_esc1_clk_src", &disp_cc_mdss_esc1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -634,8 +636,8 @@ static struct clk_branch disp_cc_mdss_mdp_clk = { ...@@ -634,8 +636,8 @@ static struct clk_branch disp_cc_mdss_mdp_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk", .name = "disp_cc_mdss_mdp_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_mdp_clk_src", &disp_cc_mdss_mdp_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -652,8 +654,8 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = { ...@@ -652,8 +654,8 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_lut_clk", .name = "disp_cc_mdss_mdp_lut_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_mdp_clk_src", &disp_cc_mdss_mdp_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_branch2_ops, .ops = &clk_branch2_ops,
...@@ -670,8 +672,8 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = { ...@@ -670,8 +672,8 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk", .name = "disp_cc_mdss_pclk0_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_pclk0_clk_src", &disp_cc_mdss_pclk0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -689,8 +691,8 @@ static struct clk_branch disp_cc_mdss_pclk1_clk = { ...@@ -689,8 +691,8 @@ static struct clk_branch disp_cc_mdss_pclk1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk1_clk", .name = "disp_cc_mdss_pclk1_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_pclk1_clk_src", &disp_cc_mdss_pclk1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -707,8 +709,8 @@ static struct clk_branch disp_cc_mdss_rot_clk = { ...@@ -707,8 +709,8 @@ static struct clk_branch disp_cc_mdss_rot_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk", .name = "disp_cc_mdss_rot_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_rot_clk_src", &disp_cc_mdss_rot_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -738,8 +740,8 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { ...@@ -738,8 +740,8 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rscc_vsync_clk", .name = "disp_cc_mdss_rscc_vsync_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_vsync_clk_src", &disp_cc_mdss_vsync_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -756,8 +758,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { ...@@ -756,8 +758,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk", .name = "disp_cc_mdss_vsync_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"disp_cc_mdss_vsync_clk_src", &disp_cc_mdss_vsync_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7