Commit 7bf1d7e1 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman

powerpc/32: Use START_EXCEPTION() as much as possible

Everywhere where it is possible, use START_EXCEPTION().

This will help for proper exception init in future patches.
Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/d47c1cc242bbbef8658327503726abdaef9b63ef.1615552867.git.christophe.leroy@csgroup.eu
parent 5b5e5bc5
...@@ -247,17 +247,15 @@ _ENTRY(crit_esr) ...@@ -247,17 +247,15 @@ _ENTRY(crit_esr)
EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_STD) EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_STD)
/* 0x1000 - Programmable Interval Timer (PIT) Exception */ /* 0x1000 - Programmable Interval Timer (PIT) Exception */
. = 0x1000 START_EXCEPTION(0x1000, DecrementerTrap)
b Decrementer b Decrementer
/* 0x1010 - Fixed Interval Timer (FIT) Exception /* 0x1010 - Fixed Interval Timer (FIT) Exception */
*/ START_EXCEPTION(0x1010, FITExceptionTrap)
. = 0x1010
b FITException b FITException
/* 0x1020 - Watchdog Timer (WDT) Exception /* 0x1020 - Watchdog Timer (WDT) Exception */
*/ START_EXCEPTION(0x1020, WDTExceptionTrap)
. = 0x1020
b WDTException b WDTException
/* 0x1100 - Data TLB Miss Exception /* 0x1100 - Data TLB Miss Exception
......
...@@ -121,8 +121,7 @@ instruction_counter: ...@@ -121,8 +121,7 @@ instruction_counter:
EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD) EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
/* Machine check */ /* Machine check */
. = 0x200 START_EXCEPTION(0x200, MachineCheck)
MachineCheck:
EXCEPTION_PROLOG handle_dar_dsisr=1 EXCEPTION_PROLOG handle_dar_dsisr=1
addi r3,r1,STACK_FRAME_OVERHEAD addi r3,r1,STACK_FRAME_OVERHEAD
EXC_XFER_STD(0x200, machine_check_exception) EXC_XFER_STD(0x200, machine_check_exception)
...@@ -131,8 +130,7 @@ MachineCheck: ...@@ -131,8 +130,7 @@ MachineCheck:
EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
/* Alignment exception */ /* Alignment exception */
. = 0x600 START_EXCEPTION(0x600, Alignment)
Alignment:
EXCEPTION_PROLOG handle_dar_dsisr=1 EXCEPTION_PROLOG handle_dar_dsisr=1
addi r3,r1,STACK_FRAME_OVERHEAD addi r3,r1,STACK_FRAME_OVERHEAD
b .Lalignment_exception_ool b .Lalignment_exception_ool
...@@ -149,8 +147,7 @@ Alignment: ...@@ -149,8 +147,7 @@ Alignment:
EXC_XFER_STD(0x600, alignment_exception) EXC_XFER_STD(0x600, alignment_exception)
/* System call */ /* System call */
. = 0xc00 START_EXCEPTION(0xc00, SystemCall)
SystemCall:
SYSCALL_ENTRY 0xc00 SYSCALL_ENTRY 0xc00
/* Single step - not used on 601 */ /* Single step - not used on 601 */
...@@ -161,7 +158,6 @@ SystemCall: ...@@ -161,7 +158,6 @@ SystemCall:
*/ */
EXCEPTION(0x1000, SoftEmu, emulation_assist_interrupt, EXC_XFER_STD) EXCEPTION(0x1000, SoftEmu, emulation_assist_interrupt, EXC_XFER_STD)
. = 0x1100
/* /*
* For the MPC8xx, this is a software tablewalk to load the instruction * For the MPC8xx, this is a software tablewalk to load the instruction
* TLB. The task switch loads the M_TWB register with the pointer to the first * TLB. The task switch loads the M_TWB register with the pointer to the first
...@@ -183,7 +179,7 @@ SystemCall: ...@@ -183,7 +179,7 @@ SystemCall:
#define INVALIDATE_ADJACENT_PAGES_CPU15(addr, tmp) #define INVALIDATE_ADJACENT_PAGES_CPU15(addr, tmp)
#endif #endif
InstructionTLBMiss: START_EXCEPTION(0x1100, InstructionTLBMiss)
mtspr SPRN_SPRG_SCRATCH2, r10 mtspr SPRN_SPRG_SCRATCH2, r10
mtspr SPRN_M_TW, r11 mtspr SPRN_M_TW, r11
...@@ -239,8 +235,7 @@ InstructionTLBMiss: ...@@ -239,8 +235,7 @@ InstructionTLBMiss:
rfi rfi
#endif #endif
. = 0x1200 START_EXCEPTION(0x1200, DataStoreTLBMiss)
DataStoreTLBMiss:
mtspr SPRN_SPRG_SCRATCH2, r10 mtspr SPRN_SPRG_SCRATCH2, r10
mtspr SPRN_M_TW, r11 mtspr SPRN_M_TW, r11
mfcr r11 mfcr r11
...@@ -303,8 +298,7 @@ DataStoreTLBMiss: ...@@ -303,8 +298,7 @@ DataStoreTLBMiss:
* to many reasons, such as executing guarded memory or illegal instruction * to many reasons, such as executing guarded memory or illegal instruction
* addresses. There is nothing to do but handle a big time error fault. * addresses. There is nothing to do but handle a big time error fault.
*/ */
. = 0x1300 START_EXCEPTION(0x1300, InstructionTLBError)
InstructionTLBError:
EXCEPTION_PROLOG EXCEPTION_PROLOG
andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */ andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
andis. r10,r9,SRR1_ISI_NOPT@h andis. r10,r9,SRR1_ISI_NOPT@h
...@@ -320,8 +314,7 @@ InstructionTLBError: ...@@ -320,8 +314,7 @@ InstructionTLBError:
* many reasons, including a dirty update to a pte. We bail out to * many reasons, including a dirty update to a pte. We bail out to
* a higher level function that can handle it. * a higher level function that can handle it.
*/ */
. = 0x1400 START_EXCEPTION(0x1400, DataTLBError)
DataTLBError:
EXCEPTION_PROLOG_0 handle_dar_dsisr=1 EXCEPTION_PROLOG_0 handle_dar_dsisr=1
mfspr r11, SPRN_DAR mfspr r11, SPRN_DAR
cmpwi cr1, r11, RPN_PATTERN cmpwi cr1, r11, RPN_PATTERN
...@@ -354,8 +347,7 @@ do_databreakpoint: ...@@ -354,8 +347,7 @@ do_databreakpoint:
stw r4,_DAR(r11) stw r4,_DAR(r11)
EXC_XFER_STD(0x1c00, do_break) EXC_XFER_STD(0x1c00, do_break)
. = 0x1c00 START_EXCEPTION(0x1c00, DataBreakpoint)
DataBreakpoint:
EXCEPTION_PROLOG_0 handle_dar_dsisr=1 EXCEPTION_PROLOG_0 handle_dar_dsisr=1
mfspr r11, SPRN_SRR0 mfspr r11, SPRN_SRR0
cmplwi cr1, r11, (.Ldtlbie - PAGE_OFFSET)@l cmplwi cr1, r11, (.Ldtlbie - PAGE_OFFSET)@l
...@@ -368,8 +360,7 @@ DataBreakpoint: ...@@ -368,8 +360,7 @@ DataBreakpoint:
rfi rfi
#ifdef CONFIG_PERF_EVENTS #ifdef CONFIG_PERF_EVENTS
. = 0x1d00 START_EXCEPTION(0x1d00, InstructionBreakpoint)
InstructionBreakpoint:
mtspr SPRN_SPRG_SCRATCH0, r10 mtspr SPRN_SPRG_SCRATCH0, r10
lwz r10, (instruction_counter - PAGE_OFFSET)@l(0) lwz r10, (instruction_counter - PAGE_OFFSET)@l(0)
addi r10, r10, -1 addi r10, r10, -1
......
...@@ -255,9 +255,7 @@ __secondary_hold_acknowledge: ...@@ -255,9 +255,7 @@ __secondary_hold_acknowledge:
* pointer when we take an exception from supervisor mode.) * pointer when we take an exception from supervisor mode.)
* -- paulus. * -- paulus.
*/ */
. = 0x200 START_EXCEPTION(0x200, MachineCheck)
DO_KVM 0x200
MachineCheck:
EXCEPTION_PROLOG_0 EXCEPTION_PROLOG_0
#ifdef CONFIG_PPC_CHRP #ifdef CONFIG_PPC_CHRP
mtspr SPRN_SPRG_SCRATCH2,r1 mtspr SPRN_SPRG_SCRATCH2,r1
...@@ -278,9 +276,7 @@ MachineCheck: ...@@ -278,9 +276,7 @@ MachineCheck:
#endif #endif
/* Data access exception. */ /* Data access exception. */
. = 0x300 START_EXCEPTION(0x300, DataAccess)
DO_KVM 0x300
DataAccess:
#ifdef CONFIG_PPC_BOOK3S_604 #ifdef CONFIG_PPC_BOOK3S_604
BEGIN_MMU_FTR_SECTION BEGIN_MMU_FTR_SECTION
mtspr SPRN_SPRG_SCRATCH2,r10 mtspr SPRN_SPRG_SCRATCH2,r10
...@@ -304,9 +300,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE) ...@@ -304,9 +300,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
b handle_page_fault_tramp_1 b handle_page_fault_tramp_1
/* Instruction access exception. */ /* Instruction access exception. */
. = 0x400 START_EXCEPTION(0x400, InstructionAccess)
DO_KVM 0x400
InstructionAccess:
mtspr SPRN_SPRG_SCRATCH0,r10 mtspr SPRN_SPRG_SCRATCH0,r10
mtspr SPRN_SPRG_SCRATCH1,r11 mtspr SPRN_SPRG_SCRATCH1,r11
mfspr r10, SPRN_SPRG_THREAD mfspr r10, SPRN_SPRG_THREAD
...@@ -336,9 +330,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE) ...@@ -336,9 +330,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
/* Alignment exception */ /* Alignment exception */
. = 0x600 START_EXCEPTION(0x600, Alignment)
DO_KVM 0x600
Alignment:
EXCEPTION_PROLOG handle_dar_dsisr=1 EXCEPTION_PROLOG handle_dar_dsisr=1
addi r3,r1,STACK_FRAME_OVERHEAD addi r3,r1,STACK_FRAME_OVERHEAD
b alignment_exception_tramp b alignment_exception_tramp
...@@ -347,9 +339,7 @@ Alignment: ...@@ -347,9 +339,7 @@ Alignment:
EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
/* Floating-point unavailable */ /* Floating-point unavailable */
. = 0x800 START_EXCEPTION(0x800, FPUnavailable)
DO_KVM 0x800
FPUnavailable:
#ifdef CONFIG_PPC_FPU #ifdef CONFIG_PPC_FPU
BEGIN_FTR_SECTION BEGIN_FTR_SECTION
/* /*
...@@ -375,9 +365,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE) ...@@ -375,9 +365,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_STD) EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_STD)
/* System call */ /* System call */
. = 0xc00 START_EXCEPTION(0xc00, SystemCall)
DO_KVM 0xc00
SystemCall:
SYSCALL_ENTRY 0xc00 SYSCALL_ENTRY 0xc00
EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
...@@ -391,12 +379,10 @@ SystemCall: ...@@ -391,12 +379,10 @@ SystemCall:
* non-altivec kernel running on a machine with altivec just * non-altivec kernel running on a machine with altivec just
* by executing an altivec instruction. * by executing an altivec instruction.
*/ */
. = 0xf00 START_EXCEPTION(0xf00, PerformanceMonitorTrap)
DO_KVM 0xf00
b PerformanceMonitor b PerformanceMonitor
. = 0xf20 START_EXCEPTION(0xf20, AltiVecUnavailableTrap)
DO_KVM 0xf20
b AltiVecUnavailable b AltiVecUnavailable
/* /*
......
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