Commit 7c1a2d8a authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/gfx9: put queue resets behind a debug option

Pending extended validation.
Reviewed-and-tested-by: default avatarJiadong Zhu <Jiadong.Zhu@amd.com>
Acked-by: default avatarFelix Kuehling <felix.kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a9b67c03
......@@ -1151,6 +1151,10 @@ uint64_t kgd_gfx_v9_hqd_get_pq_addr(struct amdgpu_device *adev,
uint32_t low, high;
uint64_t queue_addr = 0;
if (!adev->debug_exp_resets &&
!adev->gfx.num_gfx_rings)
return 0;
kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst);
amdgpu_gfx_rlc_enter_safe_mode(adev, inst);
......
......@@ -7233,6 +7233,10 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring,
unsigned long flags;
int i, r;
if (!adev->debug_exp_resets &&
!adev->gfx.num_gfx_rings)
return -EINVAL;
if (amdgpu_sriov_vf(adev))
return -EINVAL;
......
......@@ -3052,6 +3052,9 @@ static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring,
struct amdgpu_device *adev = ring->adev;
uint32_t value = 0;
if (!adev->debug_exp_resets)
return;
value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
......@@ -3475,6 +3478,9 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring,
unsigned long flags;
int r, i;
if (!adev->debug_exp_resets)
return -EINVAL;
if (amdgpu_sriov_vf(adev))
return -EINVAL;
......
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