Commit 7c1b7023 authored by David S. Miller's avatar David S. Miller

Merge branch 'cxgb4-next'

Hariprasad Shenai says:

====================
Add support for few debugfs entries

This patch series adds support for devlog, cim_la, cim_qcfg and mps_tcam
debugfs entries.

The patches series is created against 'net-next' tree.
And includes patches on cxgb4 driver.

We have included all the maintainers of respective drivers. Kindly review the
change and let us know in case of any review comments.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents cd91cc5b ef82f662
...@@ -290,11 +290,21 @@ enum chip_type { ...@@ -290,11 +290,21 @@ enum chip_type {
T5_LAST_REV = T5_A1, T5_LAST_REV = T5_A1,
}; };
struct devlog_params {
u32 memtype; /* which memory (EDC0, EDC1, MC) */
u32 start; /* start of log in firmware memory */
u32 size; /* size of log */
};
struct adapter_params { struct adapter_params {
struct sge_params sge; struct sge_params sge;
struct tp_params tp; struct tp_params tp;
struct vpd_params vpd; struct vpd_params vpd;
struct pci_params pci; struct pci_params pci;
struct devlog_params devlog;
enum pcie_memwin drv_memwin;
unsigned int cim_la_size;
unsigned int sf_size; /* serial flash size in bytes */ unsigned int sf_size; /* serial flash size in bytes */
unsigned int sf_nsec; /* # of flash sectors */ unsigned int sf_nsec; /* # of flash sectors */
...@@ -1026,6 +1036,12 @@ int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, ...@@ -1026,6 +1036,12 @@ int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
u64 *parity); u64 *parity);
int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
u64 *parity); u64 *parity);
int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
unsigned int *valp);
int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
const unsigned int *valp);
int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
const char *t4_get_port_type_description(enum fw_port_type port_type); const char *t4_get_port_type_description(enum fw_port_type port_type);
void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
......
...@@ -44,6 +44,18 @@ struct t4_debugfs_entry { ...@@ -44,6 +44,18 @@ struct t4_debugfs_entry {
unsigned char data; unsigned char data;
}; };
struct seq_tab {
int (*show)(struct seq_file *seq, void *v, int idx);
unsigned int rows; /* # of entries */
unsigned char width; /* size in bytes of each entry */
unsigned char skip_first; /* whether the first line is a header */
char data[0]; /* the table data */
};
struct seq_tab *seq_open_tab(struct file *f, unsigned int rows,
unsigned int width, unsigned int have_header,
int (*show)(struct seq_file *seq, void *v, int i));
int t4_setup_debugfs(struct adapter *adap); int t4_setup_debugfs(struct adapter *adap);
void add_debugfs_files(struct adapter *adap, void add_debugfs_files(struct adapter *adap,
struct t4_debugfs_entry *files, struct t4_debugfs_entry *files,
......
...@@ -5541,6 +5541,8 @@ static int adap_init0(struct adapter *adap) ...@@ -5541,6 +5541,8 @@ static int adap_init0(struct adapter *adap)
enum dev_state state; enum dev_state state;
u32 params[7], val[7]; u32 params[7], val[7];
struct fw_caps_config_cmd caps_cmd; struct fw_caps_config_cmd caps_cmd;
struct fw_devlog_cmd devlog_cmd;
u32 devlog_meminfo;
int reset = 1; int reset = 1;
/* Contact FW, advertising Master capability */ /* Contact FW, advertising Master capability */
...@@ -5621,6 +5623,30 @@ static int adap_init0(struct adapter *adap) ...@@ -5621,6 +5623,30 @@ static int adap_init0(struct adapter *adap)
if (ret < 0) if (ret < 0)
goto bye; goto bye;
/* Read firmware device log parameters. We really need to find a way
* to get these parameters initialized with some default values (which
* are likely to be correct) for the case where we either don't
* attache to the firmware or it's crashed when we probe the adapter.
* That way we'll still be able to perform early firmware startup
* debugging ... If the request to get the Firmware's Device Log
* parameters fails, we'll live so we don't make that a fatal error.
*/
memset(&devlog_cmd, 0, sizeof(devlog_cmd));
devlog_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_DEVLOG_CMD) |
FW_CMD_REQUEST_F | FW_CMD_READ_F);
devlog_cmd.retval_len16 = htonl(FW_LEN16(devlog_cmd));
ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
&devlog_cmd);
if (ret == 0) {
devlog_meminfo =
ntohl(devlog_cmd.memtype_devlog_memaddr16_devlog);
adap->params.devlog.memtype =
FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
adap->params.devlog.start =
FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
adap->params.devlog.size = ntohl(devlog_cmd.memsize_devlog);
}
/* /*
* Find out what ports are available to us. Note that we need to do * Find out what ports are available to us. Note that we need to do
* this before calling adap_init0_no_config() since it needs nports * this before calling adap_init0_no_config() since it needs nports
......
...@@ -4031,6 +4031,7 @@ int t4_prep_adapter(struct adapter *adapter) ...@@ -4031,6 +4031,7 @@ int t4_prep_adapter(struct adapter *adapter)
return -EINVAL; return -EINVAL;
} }
adapter->params.cim_la_size = CIMLA_SIZE;
init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
/* /*
...@@ -4323,3 +4324,157 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf) ...@@ -4323,3 +4324,157 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
} }
return 0; return 0;
} }
/**
* t4_read_cimq_cfg - read CIM queue configuration
* @adap: the adapter
* @base: holds the queue base addresses in bytes
* @size: holds the queue sizes in bytes
* @thres: holds the queue full thresholds in bytes
*
* Returns the current configuration of the CIM queues, starting with
* the IBQs, then the OBQs.
*/
void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
{
unsigned int i, v;
int cim_num_obq = is_t4(adap->params.chip) ?
CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
for (i = 0; i < CIM_NUM_IBQ; i++) {
t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
QUENUMSELECT_V(i));
v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
/* value is in 256-byte units */
*base++ = CIMQBASE_G(v) * 256;
*size++ = CIMQSIZE_G(v) * 256;
*thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
}
for (i = 0; i < cim_num_obq; i++) {
t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
QUENUMSELECT_V(i));
v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
/* value is in 256-byte units */
*base++ = CIMQBASE_G(v) * 256;
*size++ = CIMQSIZE_G(v) * 256;
}
}
/**
* t4_cim_read - read a block from CIM internal address space
* @adap: the adapter
* @addr: the start address within the CIM address space
* @n: number of words to read
* @valp: where to store the result
*
* Reads a block of 4-byte words from the CIM intenal address space.
*/
int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
unsigned int *valp)
{
int ret = 0;
if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
return -EBUSY;
for ( ; !ret && n--; addr += 4) {
t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
0, 5, 2);
if (!ret)
*valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
}
return ret;
}
/**
* t4_cim_write - write a block into CIM internal address space
* @adap: the adapter
* @addr: the start address within the CIM address space
* @n: number of words to write
* @valp: set of values to write
*
* Writes a block of 4-byte words into the CIM intenal address space.
*/
int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
const unsigned int *valp)
{
int ret = 0;
if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
return -EBUSY;
for ( ; !ret && n--; addr += 4) {
t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
0, 5, 2);
}
return ret;
}
static int t4_cim_write1(struct adapter *adap, unsigned int addr,
unsigned int val)
{
return t4_cim_write(adap, addr, 1, &val);
}
/**
* t4_cim_read_la - read CIM LA capture buffer
* @adap: the adapter
* @la_buf: where to store the LA data
* @wrptr: the HW write pointer within the capture buffer
*
* Reads the contents of the CIM LA buffer with the most recent entry at
* the end of the returned data and with the entry at @wrptr first.
* We try to leave the LA in the running state we find it in.
*/
int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
{
int i, ret;
unsigned int cfg, val, idx;
ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
if (ret)
return ret;
if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
if (ret)
return ret;
}
ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
if (ret)
goto restart;
idx = UPDBGLAWRPTR_G(val);
if (wrptr)
*wrptr = idx;
for (i = 0; i < adap->params.cim_la_size; i++) {
ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
if (ret)
break;
ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
if (ret)
break;
if (val & UPDBGLARDEN_F) {
ret = -ETIMEDOUT;
break;
}
ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
if (ret)
break;
idx = (idx + 1) & UPDBGLARDPTR_M;
}
restart:
if (cfg & UPDBGLAEN_F) {
int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
cfg & ~UPDBGLARDEN_F);
if (!ret)
ret = r;
}
return ret;
}
...@@ -55,6 +55,13 @@ enum { ...@@ -55,6 +55,13 @@ enum {
WOL_PAT_LEN = 128, /* length of WoL patterns */ WOL_PAT_LEN = 128, /* length of WoL patterns */
}; };
enum {
CIM_NUM_IBQ = 6, /* # of CIM IBQs */
CIM_NUM_OBQ = 6, /* # of CIM OBQs */
CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */
CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
};
enum { enum {
SF_PAGE_SIZE = 256, /* serial flash page size */ SF_PAGE_SIZE = 256, /* serial flash page size */
SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
...@@ -110,6 +117,18 @@ enum { ...@@ -110,6 +117,18 @@ enum {
SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */ SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */
}; };
/* PCI-e memory window access */
enum pcie_memwin {
MEMWIN_NIC = 0,
MEMWIN_RSVD1 = 1,
MEMWIN_RSVD2 = 2,
MEMWIN_RDMA = 3,
MEMWIN_RSVD4 = 4,
MEMWIN_FOISCSI = 5,
MEMWIN_CSIOSTOR = 6,
MEMWIN_RSVD7 = 7,
};
struct sge_qstat { /* data written to SGE queue status entries */ struct sge_qstat { /* data written to SGE queue status entries */
__be32 qid; __be32 qid;
__be16 cidx; __be16 cidx;
......
...@@ -1708,6 +1708,66 @@ ...@@ -1708,6 +1708,66 @@
#define MPS_RX_PERR_INT_CAUSE_A 0x11074 #define MPS_RX_PERR_INT_CAUSE_A 0x11074
#define MPS_CLS_TCAM_Y_L_A 0xf000
#define MPS_CLS_TCAM_X_L_A 0xf008
#define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16)
#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
#define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16)
#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
#define MPS_CLS_SRAM_L_A 0xe000
#define MPS_CLS_SRAM_H_A 0xe004
#define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8)
#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
#define MPS_CLS_SRAM_H(idx) (MPS_CLS_SRAM_H_A + (idx) * 8)
#define NUM_MPS_CLS_SRAM_H_INSTANCES 336
#define MULTILISTEN0_S 25
#define REPLICATE_S 11
#define REPLICATE_V(x) ((x) << REPLICATE_S)
#define REPLICATE_F REPLICATE_V(1U)
#define PF_S 8
#define PF_M 0x7U
#define PF_G(x) (((x) >> PF_S) & PF_M)
#define VF_VALID_S 7
#define VF_VALID_V(x) ((x) << VF_VALID_S)
#define VF_VALID_F VF_VALID_V(1U)
#define VF_S 0
#define VF_M 0x7fU
#define VF_G(x) (((x) >> VF_S) & VF_M)
#define SRAM_PRIO3_S 22
#define SRAM_PRIO3_M 0x7U
#define SRAM_PRIO3_G(x) (((x) >> SRAM_PRIO3_S) & SRAM_PRIO3_M)
#define SRAM_PRIO2_S 19
#define SRAM_PRIO2_M 0x7U
#define SRAM_PRIO2_G(x) (((x) >> SRAM_PRIO2_S) & SRAM_PRIO2_M)
#define SRAM_PRIO1_S 16
#define SRAM_PRIO1_M 0x7U
#define SRAM_PRIO1_G(x) (((x) >> SRAM_PRIO1_S) & SRAM_PRIO1_M)
#define SRAM_PRIO0_S 13
#define SRAM_PRIO0_M 0x7U
#define SRAM_PRIO0_G(x) (((x) >> SRAM_PRIO0_S) & SRAM_PRIO0_M)
#define SRAM_VLD_S 12
#define SRAM_VLD_V(x) ((x) << SRAM_VLD_S)
#define SRAM_VLD_F SRAM_VLD_V(1U)
#define PORTMAP_S 0
#define PORTMAP_M 0xfU
#define PORTMAP_G(x) (((x) >> PORTMAP_S) & PORTMAP_M)
#define CPL_INTR_CAUSE_A 0x19054 #define CPL_INTR_CAUSE_A 0x19054
#define CIM_OP_MAP_PERR_S 5 #define CIM_OP_MAP_PERR_S 5
...@@ -2062,4 +2122,93 @@ ...@@ -2062,4 +2122,93 @@
#define PL_VF_WHOAMI_A 0x0 #define PL_VF_WHOAMI_A 0x0
#define PL_VF_REVISION_A 0x8 #define PL_VF_REVISION_A 0x8
/* registers for module CIM */
#define CIM_HOST_ACC_CTRL_A 0x7b50
#define CIM_HOST_ACC_DATA_A 0x7b54
#define UP_UP_DBG_LA_CFG_A 0x140
#define UP_UP_DBG_LA_DATA_A 0x144
#define HOSTBUSY_S 17
#define HOSTBUSY_V(x) ((x) << HOSTBUSY_S)
#define HOSTBUSY_F HOSTBUSY_V(1U)
#define HOSTWRITE_S 16
#define HOSTWRITE_V(x) ((x) << HOSTWRITE_S)
#define HOSTWRITE_F HOSTWRITE_V(1U)
#define UPDBGLARDEN_S 1
#define UPDBGLARDEN_V(x) ((x) << UPDBGLARDEN_S)
#define UPDBGLARDEN_F UPDBGLARDEN_V(1U)
#define UPDBGLAEN_S 0
#define UPDBGLAEN_V(x) ((x) << UPDBGLAEN_S)
#define UPDBGLAEN_F UPDBGLAEN_V(1U)
#define UPDBGLARDPTR_S 2
#define UPDBGLARDPTR_M 0xfffU
#define UPDBGLARDPTR_V(x) ((x) << UPDBGLARDPTR_S)
#define UPDBGLAWRPTR_S 16
#define UPDBGLAWRPTR_M 0xfffU
#define UPDBGLAWRPTR_G(x) (((x) >> UPDBGLAWRPTR_S) & UPDBGLAWRPTR_M)
#define UPDBGLACAPTPCONLY_S 30
#define UPDBGLACAPTPCONLY_V(x) ((x) << UPDBGLACAPTPCONLY_S)
#define UPDBGLACAPTPCONLY_F UPDBGLACAPTPCONLY_V(1U)
#define CIM_QUEUE_CONFIG_REF_A 0x7b48
#define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c
#define CIMQSIZE_S 24
#define CIMQSIZE_M 0x3fU
#define CIMQSIZE_G(x) (((x) >> CIMQSIZE_S) & CIMQSIZE_M)
#define CIMQBASE_S 16
#define CIMQBASE_M 0x3fU
#define CIMQBASE_G(x) (((x) >> CIMQBASE_S) & CIMQBASE_M)
#define QUEFULLTHRSH_S 0
#define QUEFULLTHRSH_M 0x1ffU
#define QUEFULLTHRSH_G(x) (((x) >> QUEFULLTHRSH_S) & QUEFULLTHRSH_M)
#define UP_IBQ_0_RDADDR_A 0x10
#define UP_IBQ_0_SHADOW_RDADDR_A 0x280
#define UP_OBQ_0_REALADDR_A 0x104
#define UP_OBQ_0_SHADOW_REALADDR_A 0x394
#define IBQRDADDR_S 0
#define IBQRDADDR_M 0x1fffU
#define IBQRDADDR_G(x) (((x) >> IBQRDADDR_S) & IBQRDADDR_M)
#define IBQWRADDR_S 0
#define IBQWRADDR_M 0x1fffU
#define IBQWRADDR_G(x) (((x) >> IBQWRADDR_S) & IBQWRADDR_M)
#define QUERDADDR_S 0
#define QUERDADDR_M 0x7fffU
#define QUERDADDR_G(x) (((x) >> QUERDADDR_S) & QUERDADDR_M)
#define QUEREMFLITS_S 0
#define QUEREMFLITS_M 0x7ffU
#define QUEREMFLITS_G(x) (((x) >> QUEREMFLITS_S) & QUEREMFLITS_M)
#define QUEEOPCNT_S 16
#define QUEEOPCNT_M 0xfffU
#define QUEEOPCNT_G(x) (((x) >> QUEEOPCNT_S) & QUEEOPCNT_M)
#define QUESOPCNT_S 0
#define QUESOPCNT_M 0xfffU
#define QUESOPCNT_G(x) (((x) >> QUESOPCNT_S) & QUESOPCNT_M)
#define OBQSELECT_S 4
#define OBQSELECT_V(x) ((x) << OBQSELECT_S)
#define OBQSELECT_F OBQSELECT_V(1U)
#define IBQSELECT_S 3
#define IBQSELECT_V(x) ((x) << IBQSELECT_S)
#define IBQSELECT_F IBQSELECT_V(1U)
#define QUENUMSELECT_S 0
#define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S)
#endif /* __T4_REGS_H */ #endif /* __T4_REGS_H */
...@@ -673,6 +673,7 @@ enum fw_cmd_opcodes { ...@@ -673,6 +673,7 @@ enum fw_cmd_opcodes {
FW_RSS_IND_TBL_CMD = 0x20, FW_RSS_IND_TBL_CMD = 0x20,
FW_RSS_GLB_CONFIG_CMD = 0x22, FW_RSS_GLB_CONFIG_CMD = 0x22,
FW_RSS_VI_CONFIG_CMD = 0x23, FW_RSS_VI_CONFIG_CMD = 0x23,
FW_DEVLOG_CMD = 0x25,
FW_CLIP_CMD = 0x28, FW_CLIP_CMD = 0x28,
FW_LASTC2E_CMD = 0x40, FW_LASTC2E_CMD = 0x40,
FW_ERROR_CMD = 0x80, FW_ERROR_CMD = 0x80,
...@@ -3038,4 +3039,84 @@ enum fw_hdr_flags { ...@@ -3038,4 +3039,84 @@ enum fw_hdr_flags {
FW_HDR_FLAGS_RESET_HALT = 0x00000001, FW_HDR_FLAGS_RESET_HALT = 0x00000001,
}; };
/* length of the formatting string */
#define FW_DEVLOG_FMT_LEN 192
/* maximum number of the formatting string parameters */
#define FW_DEVLOG_FMT_PARAMS_NUM 8
/* priority levels */
enum fw_devlog_level {
FW_DEVLOG_LEVEL_EMERG = 0x0,
FW_DEVLOG_LEVEL_CRIT = 0x1,
FW_DEVLOG_LEVEL_ERR = 0x2,
FW_DEVLOG_LEVEL_NOTICE = 0x3,
FW_DEVLOG_LEVEL_INFO = 0x4,
FW_DEVLOG_LEVEL_DEBUG = 0x5,
FW_DEVLOG_LEVEL_MAX = 0x5,
};
/* facilities that may send a log message */
enum fw_devlog_facility {
FW_DEVLOG_FACILITY_CORE = 0x00,
FW_DEVLOG_FACILITY_CF = 0x01,
FW_DEVLOG_FACILITY_SCHED = 0x02,
FW_DEVLOG_FACILITY_TIMER = 0x04,
FW_DEVLOG_FACILITY_RES = 0x06,
FW_DEVLOG_FACILITY_HW = 0x08,
FW_DEVLOG_FACILITY_FLR = 0x10,
FW_DEVLOG_FACILITY_DMAQ = 0x12,
FW_DEVLOG_FACILITY_PHY = 0x14,
FW_DEVLOG_FACILITY_MAC = 0x16,
FW_DEVLOG_FACILITY_PORT = 0x18,
FW_DEVLOG_FACILITY_VI = 0x1A,
FW_DEVLOG_FACILITY_FILTER = 0x1C,
FW_DEVLOG_FACILITY_ACL = 0x1E,
FW_DEVLOG_FACILITY_TM = 0x20,
FW_DEVLOG_FACILITY_QFC = 0x22,
FW_DEVLOG_FACILITY_DCB = 0x24,
FW_DEVLOG_FACILITY_ETH = 0x26,
FW_DEVLOG_FACILITY_OFLD = 0x28,
FW_DEVLOG_FACILITY_RI = 0x2A,
FW_DEVLOG_FACILITY_ISCSI = 0x2C,
FW_DEVLOG_FACILITY_FCOE = 0x2E,
FW_DEVLOG_FACILITY_FOISCSI = 0x30,
FW_DEVLOG_FACILITY_FOFCOE = 0x32,
FW_DEVLOG_FACILITY_MAX = 0x32,
};
/* log message format */
struct fw_devlog_e {
__be64 timestamp;
__be32 seqno;
__be16 reserved1;
__u8 level;
__u8 facility;
__u8 fmt[FW_DEVLOG_FMT_LEN];
__be32 params[FW_DEVLOG_FMT_PARAMS_NUM];
__be32 reserved3[4];
};
struct fw_devlog_cmd {
__be32 op_to_write;
__be32 retval_len16;
__u8 level;
__u8 r2[7];
__be32 memtype_devlog_memaddr16_devlog;
__be32 memsize_devlog;
__be32 r3[2];
};
#define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28
#define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf
#define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \
(((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
#define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0
#define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff
#define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \
(((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
#endif /* _T4FW_INTERFACE_H_ */ #endif /* _T4FW_INTERFACE_H_ */
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