Commit 7cb9cf02 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu

Pull m68knommu arch updates from Greg Ungerer:
 "Most of it is a cleanup of the ColdFire hardware header files.  We
  have had a few occurrances of bugs caused by inconsistent definitions
  of peripheral addresses.  These patches make them all consistent, and
  also clean out a bunch of old crap.  Overall we remove about 1000
  lines."

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (27 commits)
  m68knommu: fix inconsistent formating in ColdFire 5407 definitions
  m68knommu: fix inconsistent formating in ColdFire 5307 definitions
  m68knommu: fix inconsistent formating in ColdFire 527x definitions
  m68knommu: fix inconsistent formating in ColdFire 5272 definitions
  m68knommu: fix inconsistent formating in ColdFire 523x definitions
  m68knommu: clean up ColdFire 54xx General Timer definitions
  m68knommu: clean up Pin Assignment definitions for the 54xx ColdFire CPU
  m68knommu: fix multi-function pin setup for FEC module on ColdFire 523x
  m68knommu: move ColdFire slice timer address defiens to 54xx header
  m68knommu: use read/write IO access functions in ColdFire m532x setup code
  m68knommu: modify ColdFire 532x GPIO register definitions to be consistent
  m68knommu: remove a lot of unsed definitions for 532x ColdFire
  m68knommu: use definitions for the ColdFire 528x FEC multi-function pins
  m68knommu: remove address offsets relative to IPSBAR for ColdFire 527x
  m68knommu: remove unused ColdFire 5282 register definitions
  m68knommu: fix wrong register offsets used for ColdFire 5272 multi-function pins
  m68knommu: make ColdFire 5249 MBAR2 register definitions absolute addresses
  m68knommu: make remaining ColdFire 5272 register definitions absolute addresses
  m68knommu: make ColdFire Park and Assignment register definitions absolute addresses
  m68knommu: make ColdFire Chip Select register definitions absolute addresses
  ...
parents dc92b1f9 a2551728
...@@ -34,10 +34,9 @@ static inline void __clear_cache_all(void) ...@@ -34,10 +34,9 @@ static inline void __clear_cache_all(void)
{ {
#ifdef CACHE_INVALIDATE #ifdef CACHE_INVALIDATE
__asm__ __volatile__ ( __asm__ __volatile__ (
"movel %0, %%d0\n\t" "movec %0, %%CACR\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t" "nop\n\t"
: : "i" (CACHE_INVALIDATE) : "d0" ); : : "r" (CACHE_INVALIDATE) );
#endif #endif
} }
...@@ -58,10 +57,9 @@ static inline void __flush_icache_all(void) ...@@ -58,10 +57,9 @@ static inline void __flush_icache_all(void)
{ {
#ifdef CACHE_INVALIDATEI #ifdef CACHE_INVALIDATEI
__asm__ __volatile__ ( __asm__ __volatile__ (
"movel %0, %%d0\n\t" "movec %0, %%CACR\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t" "nop\n\t"
: : "i" (CACHE_INVALIDATEI) : "d0" ); : : "r" (CACHE_INVALIDATEI) );
#endif #endif
} }
...@@ -72,19 +70,18 @@ static inline void __flush_dcache_all(void) ...@@ -72,19 +70,18 @@ static inline void __flush_dcache_all(void)
#endif #endif
#ifdef CACHE_INVALIDATED #ifdef CACHE_INVALIDATED
__asm__ __volatile__ ( __asm__ __volatile__ (
"movel %0, %%d0\n\t" "movec %0, %%CACR\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t" "nop\n\t"
: : "i" (CACHE_INVALIDATED) : "d0" ); : : "r" (CACHE_INVALIDATED) );
#else #else
/* Flush the wrtite buffer */ /* Flush the write buffer */
__asm__ __volatile__ ( "nop" ); __asm__ __volatile__ ( "nop" );
#endif #endif
} }
/* /*
* Push cache entries at supplied address. We want to write back any dirty * Push cache entries at supplied address. We want to write back any dirty
* data and the invalidate the cache lines associated with this address. * data and then invalidate the cache lines associated with this address.
*/ */
static inline void cache_push(unsigned long paddr, int len) static inline void cache_push(unsigned long paddr, int len)
{ {
......
...@@ -21,33 +21,33 @@ ...@@ -21,33 +21,33 @@
/* /*
* Define the 5206 SIM register set addresses. * Define the 5206 SIM register set addresses.
*/ */
#define MCFSIM_SIMR 0x03 /* SIM Config reg (r/w) */ #define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */
#define MCFSIM_ICR1 0x14 /* Intr Ctrl reg 1 (r/w) */ #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 0x15 /* Intr Ctrl reg 2 (r/w) */ #define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 0x16 /* Intr Ctrl reg 3 (r/w) */ #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 0x17 /* Intr Ctrl reg 4 (r/w) */ #define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 0x18 /* Intr Ctrl reg 5 (r/w) */ #define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 0x19 /* Intr Ctrl reg 6 (r/w) */ #define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 0x1a /* Intr Ctrl reg 7 (r/w) */ #define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 0x1b /* Intr Ctrl reg 8 (r/w) */ #define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 0x1c /* Intr Ctrl reg 9 (r/w) */ #define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 0x1d /* Intr Ctrl reg 10 (r/w) */ #define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 0x1e /* Intr Ctrl reg 11 (r/w) */ #define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */
#define MCFSIM_ICR12 0x1f /* Intr Ctrl reg 12 (r/w) */ #define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */
#define MCFSIM_ICR13 0x20 /* Intr Ctrl reg 13 (r/w) */ #define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */
#ifdef CONFIG_M5206e #ifdef CONFIG_M5206e
#define MCFSIM_ICR14 0x21 /* Intr Ctrl reg 14 (r/w) */ #define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */
#define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */ #define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */
#endif #endif
#define MCFSIM_IMR 0x36 /* Interrupt Mask reg (r/w) */ #define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */
#define MCFSIM_IPR 0x3a /* Interrupt Pend reg (r/w) */ #define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */
#define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */ #define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */
#define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/ #define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */
#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */ #define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */
#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */ #define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */
#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */ #define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */ #define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
...@@ -58,36 +58,36 @@ ...@@ -58,36 +58,36 @@
#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */ #define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */ #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */ #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */ #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
#define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */ #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
#define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */ #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
#define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */ #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
#define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */ #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
#define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */ #define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */
#define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */ #define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */
#define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */ #define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
#define MCFSIM_CSAR3 0x88 /* CS 3 Address reg (r/w) */ #define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */
#define MCFSIM_CSMR3 0x8c /* CS 3 Mask reg (r/w) */ #define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */
#define MCFSIM_CSCR3 0x92 /* CS 3 Control reg (r/w) */ #define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
#define MCFSIM_CSAR4 0x94 /* CS 4 Address reg (r/w) */ #define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */
#define MCFSIM_CSMR4 0x98 /* CS 4 Mask reg (r/w) */ #define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */
#define MCFSIM_CSCR4 0x9e /* CS 4 Control reg (r/w) */ #define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
#define MCFSIM_CSAR5 0xa0 /* CS 5 Address reg (r/w) */ #define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */
#define MCFSIM_CSMR5 0xa4 /* CS 5 Mask reg (r/w) */ #define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */
#define MCFSIM_CSCR5 0xaa /* CS 5 Control reg (r/w) */ #define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */
#define MCFSIM_CSAR6 0xac /* CS 6 Address reg (r/w) */ #define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */
#define MCFSIM_CSMR6 0xb0 /* CS 6 Mask reg (r/w) */ #define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */
#define MCFSIM_CSCR6 0xb6 /* CS 6 Control reg (r/w) */ #define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */
#define MCFSIM_CSAR7 0xb8 /* CS 7 Address reg (r/w) */ #define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */
#define MCFSIM_CSMR7 0xbc /* CS 7 Mask reg (r/w) */ #define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */
#define MCFSIM_CSCR7 0xc2 /* CS 7 Control reg (r/w) */ #define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */
#define MCFSIM_DMCR 0xc6 /* Default control */ #define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */
#ifdef CONFIG_M5206e #ifdef CONFIG_M5206e
#define MCFSIM_PAR 0xca /* Pin Assignment reg (r/w) */ #define MCFSIM_PAR (MCF_MBAR + 0xca) /* Pin Assignment */
#else #else
#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */ #define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */
#endif #endif
#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */ #define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
......
...@@ -176,21 +176,29 @@ ...@@ -176,21 +176,29 @@
/* /*
* Generic GPIO support * Generic GPIO support
*/ */
#define MCFGPIO_PODR MCFGPIO_PODR_ADDR #define MCFGPIO_PODR MCFGPIO_PODR_ADDR
#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
#define MCFGPIO_PIN_MAX 107 #define MCFGPIO_PIN_MAX 107
#define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
/* /*
* Pin Assignment * Pin Assignment
*/ */
#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040)
#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042)
#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044)
#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045)
#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046)
#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047)
#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048)
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
#define MCFGPIO_PAR_ETPU (MCF_IPSBAR + 0x10004E)
/* /*
* DMA unit base addresses. * DMA unit base addresses.
......
...@@ -25,41 +25,41 @@ ...@@ -25,41 +25,41 @@
/* /*
* Define the 5249 SIM register set addresses. * Define the 5249 SIM register set addresses.
*/ */
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
...@@ -134,23 +134,23 @@ ...@@ -134,23 +134,23 @@
#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */ #define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */ #define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */ #define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */ #define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
#define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */ #define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
#define MCFSIM2_INTLEVEL1 0x140 /* Interrupt level reg 1 */ #define MCFSIM2_INTLEVEL1 (MCF_MBAR2 + 0x140) /* Intr level reg 1 */
#define MCFSIM2_INTLEVEL2 0x144 /* Interrupt level reg 2 */ #define MCFSIM2_INTLEVEL2 (MCF_MBAR2 + 0x144) /* Intr level reg 2 */
#define MCFSIM2_INTLEVEL3 0x148 /* Interrupt level reg 3 */ #define MCFSIM2_INTLEVEL3 (MCF_MBAR2 + 0x148) /* Intr level reg 3 */
#define MCFSIM2_INTLEVEL4 0x14c /* Interrupt level reg 4 */ #define MCFSIM2_INTLEVEL4 (MCF_MBAR2 + 0x14c) /* Intr level reg 4 */
#define MCFSIM2_INTLEVEL5 0x150 /* Interrupt level reg 5 */ #define MCFSIM2_INTLEVEL5 (MCF_MBAR2 + 0x150) /* Intr level reg 5 */
#define MCFSIM2_INTLEVEL6 0x154 /* Interrupt level reg 6 */ #define MCFSIM2_INTLEVEL6 (MCF_MBAR2 + 0x154) /* Intr level reg 6 */
#define MCFSIM2_INTLEVEL7 0x158 /* Interrupt level reg 7 */ #define MCFSIM2_INTLEVEL7 (MCF_MBAR2 + 0x158) /* Intr level reg 7 */
#define MCFSIM2_INTLEVEL8 0x15c /* Interrupt level reg 8 */ #define MCFSIM2_INTLEVEL8 (MCF_MBAR2 + 0x15c) /* Intr level reg 8 */
#define MCFSIM2_DMAROUTE 0x188 /* DMA routing */ #define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */ #define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */ #define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
/* /*
* Define the base interrupt for the second interrupt controller. * Define the base interrupt for the second interrupt controller.
......
...@@ -26,41 +26,41 @@ ...@@ -26,41 +26,41 @@
/* /*
* Define the 525x SIM register set addresses. * Define the 525x SIM register set addresses.
*/ */
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
......
...@@ -21,52 +21,52 @@ ...@@ -21,52 +21,52 @@
/* /*
* Define the 5272 SIM register set addresses. * Define the 5272 SIM register set addresses.
*/ */
#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ #define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */
#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ #define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */
#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ #define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */
#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ #define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */
#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ #define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */
#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */ #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */ #define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */ #define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */ #define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */
#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */ #define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */
#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */ #define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */
#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */ #define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */
#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */ #define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */
#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ #define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */
#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ #define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */
#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ #define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */
#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ #define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */
#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ #define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */
#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ #define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */
#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ #define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */
#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ #define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */
#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ #define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */
#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ #define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */
#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ #define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */
#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ #define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */
#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ #define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */
#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ #define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */
#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ #define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */
#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ #define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */
#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ #define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */
#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ #define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */
#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ #define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */
#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ #define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */
#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ #define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */
#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ #define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */
#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ #define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */
#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ #define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */
#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ #define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */
#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ #define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */
#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ #define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */
#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */ #define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
...@@ -132,8 +132,9 @@ ...@@ -132,8 +132,9 @@
/* /*
* Generic GPIO support * Generic GPIO support
*/ */
#define MCFGPIO_PIN_MAX 48 #define MCFGPIO_PIN_MAX 48
#define MCFGPIO_IRQ_MAX -1 #define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1 #define MCFGPIO_IRQ_VECBASE -1
/****************************************************************************/ /****************************************************************************/
#endif /* m5272sim_h */ #endif /* m5272sim_h */
...@@ -184,19 +184,33 @@ ...@@ -184,19 +184,33 @@
/* /*
* Generic GPIO support * Generic GPIO support
*/ */
#define MCFGPIO_PODR MCFGPIO_PODR_ADDR #define MCFGPIO_PODR MCFGPIO_PODR_ADDR
#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
#define MCFGPIO_PIN_MAX 100 #define MCFGPIO_PIN_MAX 100
#define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
/*
* Port Pin Assignment registers.
*/
#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040)
#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042)
#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044)
#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045)
#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046)
#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047)
#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048)
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
#endif
#define UART0_ENABLE_MASK 0x000f
#define UART1_ENABLE_MASK 0x0ff0
#define UART2_ENABLE_MASK 0x3000
#endif /* CONFIG_M5271 */
#ifdef CONFIG_M5275 #ifdef CONFIG_M5275
#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004)
...@@ -279,18 +293,36 @@ ...@@ -279,18 +293,36 @@
/* /*
* Generic GPIO support * Generic GPIO support
*/ */
#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
#define MCFGPIO_PIN_MAX 148 #define MCFGPIO_PIN_MAX 148
#define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
/*
* Port Pin Assignment registers.
*/
#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100070)
#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100071)
#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100072)
#define MCFGPIO_PAR_USB (MCF_IPSBAR + 0x100076)
#define MCFGPIO_PAR_FEC0HL (MCF_IPSBAR + 0x100078)
#define MCFGPIO_PAR_FEC1HL (MCF_IPSBAR + 0x100079)
#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10007A)
#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x10007C)
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E)
#endif #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100080)
#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100082)
#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100084)
#define UART0_ENABLE_MASK 0x000f
#define UART1_ENABLE_MASK 0x00f0
#define UART2_ENABLE_MASK 0x3f00
#endif /* CONFIG_M5275 */
/* /*
* PIT timer base addresses. * PIT timer base addresses.
...@@ -310,22 +342,6 @@ ...@@ -310,22 +342,6 @@
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
/*
* GPIO pins setups to enable the UARTs.
*/
#ifdef CONFIG_M5271
#define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */
#define UART0_ENABLE_MASK 0x000f
#define UART1_ENABLE_MASK 0x0ff0
#define UART2_ENABLE_MASK 0x3000
#endif
#ifdef CONFIG_M5275
#define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */
#define UART0_ENABLE_MASK 0x000f
#define UART1_ENABLE_MASK 0x00f0
#define UART2_ENABLE_MASK 0x3f00
#endif
/* /*
* Reset Control Unit (relative to IPSBAR). * Reset Control Unit (relative to IPSBAR).
*/ */
......
...@@ -233,23 +233,6 @@ ...@@ -233,23 +233,6 @@
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
#define MCFGPIO_PIN_MAX 180 #define MCFGPIO_PIN_MAX 180
/*
* Derek Cheung - 6 Feb 2005
* add I2C and QSPI register definition using Freescale's MCF5282
*/
/* set Port AS pin for I2C or UART */
#define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056)
/* Port UA Pin Assignment Register (8 Bit) */
#define MCF5282_GPIO_PUAPAR 0x10005C
/* Interrupt Mask Register Register Low */
#define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C)
/* Interrupt Control Register 7 */
#define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51)
/* /*
* Reset Control Unit (relative to IPSBAR). * Reset Control Unit (relative to IPSBAR).
*/ */
...@@ -259,37 +242,5 @@ ...@@ -259,37 +242,5 @@
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ #define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
/********************************************************************* /****************************************************************************/
*
* Inter-IC (I2C) Module
*
*********************************************************************/
/* Read/Write access macros for general use */
#define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address
#define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider
#define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control
#define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
#define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O
/* Bit level definitions and macros */
#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F))
#define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable
#define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable
#define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode
#define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode
#define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
#define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start
#define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit
#define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
#define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy
#define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost
#define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write
#define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt
#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge
#endif /* m528xsim_h */ #endif /* m528xsim_h */
...@@ -23,71 +23,71 @@ ...@@ -23,71 +23,71 @@
/* /*
* Define the 5307 SIM register set addresses. * Define the 5307 SIM register set addresses.
*/ */
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */
#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/ #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
#ifdef CONFIG_OLDMASK #ifdef CONFIG_OLDMASK
#define MCFSIM_CSBAR 0x98 /* CS Base Address reg (r/w) */ #define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
#define MCFSIM_CSBAMR 0x9c /* CS Base Mask reg (r/w) */ #define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */
#define MCFSIM_CSMR2 0x9e /* CS 2 Mask reg (r/w) */ #define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
#define MCFSIM_CSMR3 0xaa /* CS 3 Mask reg (r/w) */ #define MCFSIM_CSMR3 (MCF_MBAR + 0xaa) /* CS 3 Mask reg */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
#define MCFSIM_CSMR4 0xb6 /* CS 4 Mask reg (r/w) */ #define MCFSIM_CSMR4 (MCF_MBAR + 0xb6) /* CS 4 Mask reg */
#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
#define MCFSIM_CSMR5 0xc2 /* CS 5 Mask reg (r/w) */ #define MCFSIM_CSMR5 (MCF_MBAR + 0xc2) /* CS 5 Mask reg */
#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
#define MCFSIM_CSMR6 0xce /* CS 6 Mask reg (r/w) */ #define MCFSIM_CSMR6 (MCF_MBAR + 0xce) /* CS 6 Mask reg */
#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
#define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */ #define MCFSIM_CSMR7 (MCF_MBAR + 0xda) /* CS 7 Mask reg */
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
#else #else
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ #define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ #define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ #define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ #define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ #define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ #define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
#endif /* CONFIG_OLDMASK */ #endif /* CONFIG_OLDMASK */
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
...@@ -127,9 +127,9 @@ ...@@ -127,9 +127,9 @@
/* /*
* Generic GPIO support * Generic GPIO support
*/ */
#define MCFGPIO_PIN_MAX 16 #define MCFGPIO_PIN_MAX 16
#define MCFGPIO_IRQ_MAX -1 #define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1 #define MCFGPIO_IRQ_VECBASE -1
/* Definition offset address for CS2-7 -- old mask 5307 */ /* Definition offset address for CS2-7 -- old mask 5307 */
...@@ -167,9 +167,9 @@ ...@@ -167,9 +167,9 @@
/* /*
* Defines for the IRQPAR Register * Defines for the IRQPAR Register
*/ */
#define IRQ5_LEVEL4 0x80 #define IRQ5_LEVEL4 0x80
#define IRQ3_LEVEL6 0x40 #define IRQ3_LEVEL6 0x40
#define IRQ1_LEVEL2 0x20 #define IRQ1_LEVEL2 0x20
/* /*
* Define system peripheral IRQ usage. * Define system peripheral IRQ usage.
......
...@@ -15,10 +15,6 @@ ...@@ -15,10 +15,6 @@
#include <asm/m53xxacr.h> #include <asm/m53xxacr.h>
#define MCF_REG32(x) (*(volatile unsigned long *)(x))
#define MCF_REG16(x) (*(volatile unsigned short *)(x))
#define MCF_REG08(x) (*(volatile unsigned char *)(x))
#define MCFINT_VECBASE 64 #define MCFINT_VECBASE 64
#define MCFINT_UART0 26 /* Interrupt number for UART0 */ #define MCFINT_UART0 26 /* Interrupt number for UART0 */
#define MCFINT_UART1 27 /* Interrupt number for UART1 */ #define MCFINT_UART1 27 /* Interrupt number for UART1 */
...@@ -38,7 +34,7 @@ ...@@ -38,7 +34,7 @@
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
#define MCF_WTM_WCR MCF_REG16(0xFC098000) #define MCF_WTM_WCR 0xFC098000
/* /*
* Define the 532x SIM register set addresses. * Define the 532x SIM register set addresses.
...@@ -152,42 +148,6 @@ ...@@ -152,42 +148,6 @@
#define MCFPM_PPMHR1 0xfc040038 #define MCFPM_PPMHR1 0xfc040038
#define MCFPM_LPCR 0xec090007 #define MCFPM_LPCR 0xec090007
/*********************************************************************
*
* Inter-IC (I2C) Module
*
*********************************************************************/
/* Read/Write access macros for general use */
#define MCF532x_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address
#define MCF532x_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider
#define MCF532x_I2C_I2CR (volatile u8 *) (0xFC058008) // Control
#define MCF532x_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status
#define MCF532x_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O
/* Bit level definitions and macros */
#define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
#define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F))
#define MCF532x_I2C_I2CR_IEN (0x80) // I2C enable
#define MCF532x_I2C_I2CR_IIEN (0x40) // interrupt enable
#define MCF532x_I2C_I2CR_MSTA (0x20) // master/slave mode
#define MCF532x_I2C_I2CR_MTX (0x10) // transmit/receive mode
#define MCF532x_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
#define MCF532x_I2C_I2CR_RSTA (0x04) // repeat start
#define MCF532x_I2C_I2SR_ICF (0x80) // data transfer bit
#define MCF532x_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
#define MCF532x_I2C_I2SR_IBB (0x20) // I2C bus busy
#define MCF532x_I2C_I2SR_IAL (0x10) // aribitration lost
#define MCF532x_I2C_I2SR_SRW (0x04) // slave read/write
#define MCF532x_I2C_I2SR_IIF (0x02) // I2C interrupt
#define MCF532x_I2C_I2SR_RXAK (0x01) // received acknowledge
#define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053)
/* /*
* The M5329EVB board needs a help getting its devices initialized * The M5329EVB board needs a help getting its devices initialized
* at kernel start time if dBUG doesn't set it up (for example * at kernel start time if dBUG doesn't set it up (for example
...@@ -217,13 +177,13 @@ ...@@ -217,13 +177,13 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_CCM_CCR MCF_REG16(0xFC0A0004) #define MCF_CCM_CCR 0xFC0A0004
#define MCF_CCM_RCON MCF_REG16(0xFC0A0008) #define MCF_CCM_RCON 0xFC0A0008
#define MCF_CCM_CIR MCF_REG16(0xFC0A000A) #define MCF_CCM_CIR 0xFC0A000A
#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010) #define MCF_CCM_MISCCR 0xFC0A0010
#define MCF_CCM_CDR MCF_REG16(0xFC0A0012) #define MCF_CCM_CDR 0xFC0A0012
#define MCF_CCM_UHCSR MCF_REG16(0xFC0A0014) #define MCF_CCM_UHCSR 0xFC0A0014
#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0016) #define MCF_CCM_UOCSR 0xFC0A0016
/* Bit definitions and macros for MCF_CCM_CCR */ /* Bit definitions and macros for MCF_CCM_CCR */
#define MCF_CCM_CCR_RESERVED (0x0001) #define MCF_CCM_CCR_RESERVED (0x0001)
...@@ -285,78 +245,6 @@ ...@@ -285,78 +245,6 @@
#define MCF_CCM_UOCSR_DPPD (0x2000) #define MCF_CCM_UOCSR_DPPD (0x2000)
#define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) #define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
/*********************************************************************
*
* DMA Timers (DTIM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_DTIM0_DTMR MCF_REG16(0xFC070000)
#define MCF_DTIM0_DTXMR MCF_REG08(0xFC070002)
#define MCF_DTIM0_DTER MCF_REG08(0xFC070003)
#define MCF_DTIM0_DTRR MCF_REG32(0xFC070004)
#define MCF_DTIM0_DTCR MCF_REG32(0xFC070008)
#define MCF_DTIM0_DTCN MCF_REG32(0xFC07000C)
#define MCF_DTIM1_DTMR MCF_REG16(0xFC074000)
#define MCF_DTIM1_DTXMR MCF_REG08(0xFC074002)
#define MCF_DTIM1_DTER MCF_REG08(0xFC074003)
#define MCF_DTIM1_DTRR MCF_REG32(0xFC074004)
#define MCF_DTIM1_DTCR MCF_REG32(0xFC074008)
#define MCF_DTIM1_DTCN MCF_REG32(0xFC07400C)
#define MCF_DTIM2_DTMR MCF_REG16(0xFC078000)
#define MCF_DTIM2_DTXMR MCF_REG08(0xFC078002)
#define MCF_DTIM2_DTER MCF_REG08(0xFC078003)
#define MCF_DTIM2_DTRR MCF_REG32(0xFC078004)
#define MCF_DTIM2_DTCR MCF_REG32(0xFC078008)
#define MCF_DTIM2_DTCN MCF_REG32(0xFC07800C)
#define MCF_DTIM3_DTMR MCF_REG16(0xFC07C000)
#define MCF_DTIM3_DTXMR MCF_REG08(0xFC07C002)
#define MCF_DTIM3_DTER MCF_REG08(0xFC07C003)
#define MCF_DTIM3_DTRR MCF_REG32(0xFC07C004)
#define MCF_DTIM3_DTCR MCF_REG32(0xFC07C008)
#define MCF_DTIM3_DTCN MCF_REG32(0xFC07C00C)
#define MCF_DTIM_DTMR(x) MCF_REG16(0xFC070000+((x)*0x4000))
#define MCF_DTIM_DTXMR(x) MCF_REG08(0xFC070002+((x)*0x4000))
#define MCF_DTIM_DTER(x) MCF_REG08(0xFC070003+((x)*0x4000))
#define MCF_DTIM_DTRR(x) MCF_REG32(0xFC070004+((x)*0x4000))
#define MCF_DTIM_DTCR(x) MCF_REG32(0xFC070008+((x)*0x4000))
#define MCF_DTIM_DTCN(x) MCF_REG32(0xFC07000C+((x)*0x4000))
/* Bit definitions and macros for MCF_DTIM_DTMR */
#define MCF_DTIM_DTMR_RST (0x0001)
#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1)
#define MCF_DTIM_DTMR_FRR (0x0008)
#define MCF_DTIM_DTMR_ORRI (0x0010)
#define MCF_DTIM_DTMR_OM (0x0020)
#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6)
#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8)
#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
#define MCF_DTIM_DTMR_CE_FALL (0x0080)
#define MCF_DTIM_DTMR_CE_RISE (0x0040)
#define MCF_DTIM_DTMR_CE_NONE (0x0000)
#define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
#define MCF_DTIM_DTMR_CLK_STOP (0x0000)
/* Bit definitions and macros for MCF_DTIM_DTXMR */
#define MCF_DTIM_DTXMR_MODE16 (0x01)
#define MCF_DTIM_DTXMR_DMAEN (0x80)
/* Bit definitions and macros for MCF_DTIM_DTER */
#define MCF_DTIM_DTER_CAP (0x01)
#define MCF_DTIM_DTER_REF (0x02)
/* Bit definitions and macros for MCF_DTIM_DTRR */
#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DTIM_DTCR */
#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DTIM_DTCN */
#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
/********************************************************************* /*********************************************************************
* *
* FlexBus Chip Selects (FBCS) * FlexBus Chip Selects (FBCS)
...@@ -364,27 +252,24 @@ ...@@ -364,27 +252,24 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_FBCS0_CSAR MCF_REG32(0xFC008000) #define MCF_FBCS0_CSAR 0xFC008000
#define MCF_FBCS0_CSMR MCF_REG32(0xFC008004) #define MCF_FBCS0_CSMR 0xFC008004
#define MCF_FBCS0_CSCR MCF_REG32(0xFC008008) #define MCF_FBCS0_CSCR 0xFC008008
#define MCF_FBCS1_CSAR MCF_REG32(0xFC00800C) #define MCF_FBCS1_CSAR 0xFC00800C
#define MCF_FBCS1_CSMR MCF_REG32(0xFC008010) #define MCF_FBCS1_CSMR 0xFC008010
#define MCF_FBCS1_CSCR MCF_REG32(0xFC008014) #define MCF_FBCS1_CSCR 0xFC008014
#define MCF_FBCS2_CSAR MCF_REG32(0xFC008018) #define MCF_FBCS2_CSAR 0xFC008018
#define MCF_FBCS2_CSMR MCF_REG32(0xFC00801C) #define MCF_FBCS2_CSMR 0xFC00801C
#define MCF_FBCS2_CSCR MCF_REG32(0xFC008020) #define MCF_FBCS2_CSCR 0xFC008020
#define MCF_FBCS3_CSAR MCF_REG32(0xFC008024) #define MCF_FBCS3_CSAR 0xFC008024
#define MCF_FBCS3_CSMR MCF_REG32(0xFC008028) #define MCF_FBCS3_CSMR 0xFC008028
#define MCF_FBCS3_CSCR MCF_REG32(0xFC00802C) #define MCF_FBCS3_CSCR 0xFC00802C
#define MCF_FBCS4_CSAR MCF_REG32(0xFC008030) #define MCF_FBCS4_CSAR 0xFC008030
#define MCF_FBCS4_CSMR MCF_REG32(0xFC008034) #define MCF_FBCS4_CSMR 0xFC008034
#define MCF_FBCS4_CSCR MCF_REG32(0xFC008038) #define MCF_FBCS4_CSCR 0xFC008038
#define MCF_FBCS5_CSAR MCF_REG32(0xFC00803C) #define MCF_FBCS5_CSAR 0xFC00803C
#define MCF_FBCS5_CSMR MCF_REG32(0xFC008040) #define MCF_FBCS5_CSMR 0xFC008040
#define MCF_FBCS5_CSCR MCF_REG32(0xFC008044) #define MCF_FBCS5_CSCR 0xFC008044
#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C))
#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C))
#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C))
/* Bit definitions and macros for MCF_FBCS_CSAR */ /* Bit definitions and macros for MCF_FBCS_CSAR */
#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) #define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
...@@ -501,32 +386,32 @@ ...@@ -501,32 +386,32 @@
#define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B) #define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B)
#define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C) #define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C)
#define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D) #define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D)
#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050) #define MCFGPIO_PAR_FEC (0xFC0A4050)
#define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051) #define MCFGPIO_PAR_PWM (0xFC0A4051)
#define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052) #define MCFGPIO_PAR_BUSCTL (0xFC0A4052)
#define MCF_GPIO_PAR_FECI2C MCF_REG08(0xFC0A4053) #define MCFGPIO_PAR_FECI2C (0xFC0A4053)
#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4054) #define MCFGPIO_PAR_BE (0xFC0A4054)
#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4055) #define MCFGPIO_PAR_CS (0xFC0A4055)
#define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A4056) #define MCFGPIO_PAR_SSI (0xFC0A4056)
#define MCF_GPIO_PAR_UART MCF_REG16(0xFC0A4058) #define MCFGPIO_PAR_UART (0xFC0A4058)
#define MCF_GPIO_PAR_QSPI MCF_REG16(0xFC0A405A) #define MCFGPIO_PAR_QSPI (0xFC0A405A)
#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A405C) #define MCFGPIO_PAR_TIMER (0xFC0A405C)
#define MCF_GPIO_PAR_LCDDATA MCF_REG08(0xFC0A405D) #define MCFGPIO_PAR_LCDDATA (0xFC0A405D)
#define MCF_GPIO_PAR_LCDCTL MCF_REG16(0xFC0A405E) #define MCFGPIO_PAR_LCDCTL (0xFC0A405E)
#define MCF_GPIO_PAR_IRQ MCF_REG16(0xFC0A4060) #define MCFGPIO_PAR_IRQ (0xFC0A4060)
#define MCF_GPIO_MSCR_FLEXBUS MCF_REG08(0xFC0A4064) #define MCFGPIO_MSCR_FLEXBUS (0xFC0A4064)
#define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4065) #define MCFGPIO_MSCR_SDRAM (0xFC0A4065)
#define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4068) #define MCFGPIO_DSCR_I2C (0xFC0A4068)
#define MCF_GPIO_DSCR_PWM MCF_REG08(0xFC0A4069) #define MCFGPIO_DSCR_PWM (0xFC0A4069)
#define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A406A) #define MCFGPIO_DSCR_FEC (0xFC0A406A)
#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A406B) #define MCFGPIO_DSCR_UART (0xFC0A406B)
#define MCF_GPIO_DSCR_QSPI MCF_REG08(0xFC0A406C) #define MCFGPIO_DSCR_QSPI (0xFC0A406C)
#define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A406D) #define MCFGPIO_DSCR_TIMER (0xFC0A406D)
#define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A406E) #define MCFGPIO_DSCR_SSI (0xFC0A406E)
#define MCF_GPIO_DSCR_LCD MCF_REG08(0xFC0A406F) #define MCFGPIO_DSCR_LCD (0xFC0A406F)
#define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4070) #define MCFGPIO_DSCR_DEBUG (0xFC0A4070)
#define MCF_GPIO_DSCR_CLKRST MCF_REG08(0xFC0A4071) #define MCFGPIO_DSCR_CLKRST (0xFC0A4071)
#define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4072) #define MCFGPIO_DSCR_IRQ (0xFC0A4072)
/* Bit definitions and macros for MCF_GPIO_PODR_FECH */ /* Bit definitions and macros for MCF_GPIO_PODR_FECH */
#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01) #define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01)
...@@ -1215,709 +1100,6 @@ ...@@ -1215,709 +1100,6 @@
#define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_MAX 8
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
/*********************************************************************
*
* Interrupt Controller (INTC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
#define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
#define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
#define MCF_INTC0_ICR0 MCF_REG08(0xFC048040)
#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048040+((x)*0x001))
#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x)*0x004))
#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
#define MCF_INTC1_ICR0 MCF_REG08(0xFC04C040)
#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C040+((x)*0x001))
#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8)
#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x)*0x004))
#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
#define MCF_INTC_ICR0(x) MCF_REG08(0xFC048040+((x)*0x4000))
#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
/* Bit definitions and macros for MCF_INTC_IPRH */
#define MCF_INTC_IPRH_INT32 (0x00000001)
#define MCF_INTC_IPRH_INT33 (0x00000002)
#define MCF_INTC_IPRH_INT34 (0x00000004)
#define MCF_INTC_IPRH_INT35 (0x00000008)
#define MCF_INTC_IPRH_INT36 (0x00000010)
#define MCF_INTC_IPRH_INT37 (0x00000020)
#define MCF_INTC_IPRH_INT38 (0x00000040)
#define MCF_INTC_IPRH_INT39 (0x00000080)
#define MCF_INTC_IPRH_INT40 (0x00000100)
#define MCF_INTC_IPRH_INT41 (0x00000200)
#define MCF_INTC_IPRH_INT42 (0x00000400)
#define MCF_INTC_IPRH_INT43 (0x00000800)
#define MCF_INTC_IPRH_INT44 (0x00001000)
#define MCF_INTC_IPRH_INT45 (0x00002000)
#define MCF_INTC_IPRH_INT46 (0x00004000)
#define MCF_INTC_IPRH_INT47 (0x00008000)
#define MCF_INTC_IPRH_INT48 (0x00010000)
#define MCF_INTC_IPRH_INT49 (0x00020000)
#define MCF_INTC_IPRH_INT50 (0x00040000)
#define MCF_INTC_IPRH_INT51 (0x00080000)
#define MCF_INTC_IPRH_INT52 (0x00100000)
#define MCF_INTC_IPRH_INT53 (0x00200000)
#define MCF_INTC_IPRH_INT54 (0x00400000)
#define MCF_INTC_IPRH_INT55 (0x00800000)
#define MCF_INTC_IPRH_INT56 (0x01000000)
#define MCF_INTC_IPRH_INT57 (0x02000000)
#define MCF_INTC_IPRH_INT58 (0x04000000)
#define MCF_INTC_IPRH_INT59 (0x08000000)
#define MCF_INTC_IPRH_INT60 (0x10000000)
#define MCF_INTC_IPRH_INT61 (0x20000000)
#define MCF_INTC_IPRH_INT62 (0x40000000)
#define MCF_INTC_IPRH_INT63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IPRL */
#define MCF_INTC_IPRL_INT0 (0x00000001)
#define MCF_INTC_IPRL_INT1 (0x00000002)
#define MCF_INTC_IPRL_INT2 (0x00000004)
#define MCF_INTC_IPRL_INT3 (0x00000008)
#define MCF_INTC_IPRL_INT4 (0x00000010)
#define MCF_INTC_IPRL_INT5 (0x00000020)
#define MCF_INTC_IPRL_INT6 (0x00000040)
#define MCF_INTC_IPRL_INT7 (0x00000080)
#define MCF_INTC_IPRL_INT8 (0x00000100)
#define MCF_INTC_IPRL_INT9 (0x00000200)
#define MCF_INTC_IPRL_INT10 (0x00000400)
#define MCF_INTC_IPRL_INT11 (0x00000800)
#define MCF_INTC_IPRL_INT12 (0x00001000)
#define MCF_INTC_IPRL_INT13 (0x00002000)
#define MCF_INTC_IPRL_INT14 (0x00004000)
#define MCF_INTC_IPRL_INT15 (0x00008000)
#define MCF_INTC_IPRL_INT16 (0x00010000)
#define MCF_INTC_IPRL_INT17 (0x00020000)
#define MCF_INTC_IPRL_INT18 (0x00040000)
#define MCF_INTC_IPRL_INT19 (0x00080000)
#define MCF_INTC_IPRL_INT20 (0x00100000)
#define MCF_INTC_IPRL_INT21 (0x00200000)
#define MCF_INTC_IPRL_INT22 (0x00400000)
#define MCF_INTC_IPRL_INT23 (0x00800000)
#define MCF_INTC_IPRL_INT24 (0x01000000)
#define MCF_INTC_IPRL_INT25 (0x02000000)
#define MCF_INTC_IPRL_INT26 (0x04000000)
#define MCF_INTC_IPRL_INT27 (0x08000000)
#define MCF_INTC_IPRL_INT28 (0x10000000)
#define MCF_INTC_IPRL_INT29 (0x20000000)
#define MCF_INTC_IPRL_INT30 (0x40000000)
#define MCF_INTC_IPRL_INT31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IMRH */
#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IMRL */
#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_INTFRCH */
#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_INTFRCL */
#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_ICONFIG */
#define MCF_INTC_ICONFIG_EMASK (0x0020)
#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
/* Bit definitions and macros for MCF_INTC_SIMR */
#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0)
/* Bit definitions and macros for MCF_INTC_CIMR */
#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0)
/* Bit definitions and macros for MCF_INTC_CLMASK */
#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0)
/* Bit definitions and macros for MCF_INTC_SLMASK */
#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0)
/* Bit definitions and macros for MCF_INTC_ICR */
#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0)
/* Bit definitions and macros for MCF_INTC_SWIACK */
#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_INTC_LIACK */
#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
/********************************************************************/
/*********************************************************************
*
* LCD Controller (LCDC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_LCDC_LSSAR MCF_REG32(0xFC0AC000)
#define MCF_LCDC_LSR MCF_REG32(0xFC0AC004)
#define MCF_LCDC_LVPWR MCF_REG32(0xFC0AC008)
#define MCF_LCDC_LCPR MCF_REG32(0xFC0AC00C)
#define MCF_LCDC_LCWHBR MCF_REG32(0xFC0AC010)
#define MCF_LCDC_LCCMR MCF_REG32(0xFC0AC014)
#define MCF_LCDC_LPCR MCF_REG32(0xFC0AC018)
#define MCF_LCDC_LHCR MCF_REG32(0xFC0AC01C)
#define MCF_LCDC_LVCR MCF_REG32(0xFC0AC020)
#define MCF_LCDC_LPOR MCF_REG32(0xFC0AC024)
#define MCF_LCDC_LSCR MCF_REG32(0xFC0AC028)
#define MCF_LCDC_LPCCR MCF_REG32(0xFC0AC02C)
#define MCF_LCDC_LDCR MCF_REG32(0xFC0AC030)
#define MCF_LCDC_LRMCR MCF_REG32(0xFC0AC034)
#define MCF_LCDC_LICR MCF_REG32(0xFC0AC038)
#define MCF_LCDC_LIER MCF_REG32(0xFC0AC03C)
#define MCF_LCDC_LISR MCF_REG32(0xFC0AC040)
#define MCF_LCDC_LGWSAR MCF_REG32(0xFC0AC050)
#define MCF_LCDC_LGWSR MCF_REG32(0xFC0AC054)
#define MCF_LCDC_LGWVPWR MCF_REG32(0xFC0AC058)
#define MCF_LCDC_LGWPOR MCF_REG32(0xFC0AC05C)
#define MCF_LCDC_LGWPR MCF_REG32(0xFC0AC060)
#define MCF_LCDC_LGWCR MCF_REG32(0xFC0AC064)
#define MCF_LCDC_LGWDCR MCF_REG32(0xFC0AC068)
#define MCF_LCDC_BPLUT_BASE MCF_REG32(0xFC0AC800)
#define MCF_LCDC_GWLUT_BASE MCF_REG32(0xFC0ACC00)
/* Bit definitions and macros for MCF_LCDC_LSSAR */
#define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for MCF_LCDC_LSR */
#define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0)
#define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20)
/* Bit definitions and macros for MCF_LCDC_LVPWR */
#define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0)
/* Bit definitions and macros for MCF_LCDC_LCPR */
#define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0)
#define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16)
#define MCF_LCDC_LCPR_OP (0x10000000)
#define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30)
#define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000)
#define MCF_LCDC_LCPR_CC_OR (0x40000000)
#define MCF_LCDC_LCPR_CC_XOR (0x80000000)
#define MCF_LCDC_LCPR_CC_AND (0xC0000000)
#define MCF_LCDC_LCPR_OP_ON (0x10000000)
#define MCF_LCDC_LCPR_OP_OFF (0x00000000)
/* Bit definitions and macros for MCF_LCDC_LCWHBR */
#define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0)
#define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16)
#define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24)
#define MCF_LCDC_LCWHBR_BK_EN (0x80000000)
#define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000)
#define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000)
/* Bit definitions and macros for MCF_LCDC_LCCMR */
#define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0)
#define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
#define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
/* Bit definitions and macros for MCF_LCDC_LPCR */
#define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0)
#define MCF_LCDC_LPCR_SHARP (0x00000040)
#define MCF_LCDC_LPCR_SCLKSEL (0x00000080)
#define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8)
#define MCF_LCDC_LPCR_ACDSEL (0x00008000)
#define MCF_LCDC_LPCR_REV_VS (0x00010000)
#define MCF_LCDC_LPCR_SWAP_SEL (0x00020000)
#define MCF_LCDC_LPCR_ENDSEL (0x00040000)
#define MCF_LCDC_LPCR_SCLKIDLE (0x00080000)
#define MCF_LCDC_LPCR_OEPOL (0x00100000)
#define MCF_LCDC_LPCR_CLKPOL (0x00200000)
#define MCF_LCDC_LPCR_LPPOL (0x00400000)
#define MCF_LCDC_LPCR_FLM (0x00800000)
#define MCF_LCDC_LPCR_PIXPOL (0x01000000)
#define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25)
#define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28)
#define MCF_LCDC_LPCR_COLOR (0x40000000)
#define MCF_LCDC_LPCR_TFT (0x80000000)
#define MCF_LCDC_LPCR_MODE_MONOCGROME (0x00000000)
#define MCF_LCDC_LPCR_MODE_CSTN (0x40000000)
#define MCF_LCDC_LPCR_MODE_TFT (0xC0000000)
#define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000)
#define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000)
#define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000)
#define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000)
#define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000)
#define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000)
#define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000)
#define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000)
#define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000)
#define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000)
#define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000)
#define MCF_LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
/* Bit definitions and macros for MCF_LCDC_LHCR */
#define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0)
#define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
#define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
/* Bit definitions and macros for MCF_LCDC_LVCR */
#define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0)
#define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
#define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
/* Bit definitions and macros for MCF_LCDC_LPOR */
#define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0)
/* Bit definitions and macros for MCF_LCDC_LPCCR */
#define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0)
#define MCF_LCDC_LPCCR_CC_EN (0x00000100)
#define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9)
#define MCF_LCDC_LPCCR_LDMSK (0x00008000)
#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16)
#define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000)
#define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000)
#define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000)
/* Bit definitions and macros for MCF_LCDC_LDCR */
#define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0)
#define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16)
#define MCF_LCDC_LDCR_BURST (0x80000000)
/* Bit definitions and macros for MCF_LCDC_LRMCR */
#define MCF_LCDC_LRMCR_SEL_REF (0x00000001)
/* Bit definitions and macros for MCF_LCDC_LICR */
#define MCF_LCDC_LICR_INTCON (0x00000001)
#define MCF_LCDC_LICR_INTSYN (0x00000004)
#define MCF_LCDC_LICR_GW_INT_CON (0x00000010)
/* Bit definitions and macros for MCF_LCDC_LIER */
#define MCF_LCDC_LIER_BOF_EN (0x00000001)
#define MCF_LCDC_LIER_EOF_EN (0x00000002)
#define MCF_LCDC_LIER_ERR_RES_EN (0x00000004)
#define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008)
#define MCF_LCDC_LIER_GW_BOF_EN (0x00000010)
#define MCF_LCDC_LIER_GW_EOF_EN (0x00000020)
#define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040)
#define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080)
/* Bit definitions and macros for MCF_LCDC_LISR */
#define MCF_LCDC_LISR_BOF (0x00000001)
#define MCF_LCDC_LISR_EOF (0x00000002)
#define MCF_LCDC_LISR_ERR_RES (0x00000004)
#define MCF_LCDC_LISR_UDR_ERR (0x00000008)
#define MCF_LCDC_LISR_GW_BOF (0x00000010)
#define MCF_LCDC_LISR_GW_EOF (0x00000020)
#define MCF_LCDC_LISR_GW_ERR_RES (0x00000040)
#define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080)
/* Bit definitions and macros for MCF_LCDC_LGWSAR */
#define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for MCF_LCDC_LGWSR */
#define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0)
#define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20)
/* Bit definitions and macros for MCF_LCDC_LGWVPWR */
#define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0)
/* Bit definitions and macros for MCF_LCDC_LGWPOR */
#define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0)
/* Bit definitions and macros for MCF_LCDC_LGWPR */
#define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0)
#define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16)
/* Bit definitions and macros for MCF_LCDC_LGWCR */
#define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0)
#define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
#define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
#define MCF_LCDC_LGWCR_GW_RVS (0x00200000)
#define MCF_LCDC_LGWCR_GWE (0x00400000)
#define MCF_LCDC_LGWCR_GWCKE (0x00800000)
#define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for MCF_LCDC_LGWDCR */
#define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0)
#define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
#define MCF_LCDC_LGWDCR_GWBT (0x80000000)
/* Bit definitions and macros for MCF_LCDC_LSCR */
#define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26)
#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16)
#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8)
#define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4)
#define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0)
/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */
#define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */
#define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
/********************************************************************* /*********************************************************************
* *
* Phase Locked Loop (PLL) * Phase Locked Loop (PLL)
...@@ -1925,10 +1107,10 @@ ...@@ -1925,10 +1107,10 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_PLL_PODR MCF_REG08(0xFC0C0000) #define MCF_PLL_PODR 0xFC0C0000
#define MCF_PLL_PLLCR MCF_REG08(0xFC0C0004) #define MCF_PLL_PLLCR 0xFC0C0004
#define MCF_PLL_PMDR MCF_REG08(0xFC0C0008) #define MCF_PLL_PMDR 0xFC0C0008
#define MCF_PLL_PFDR MCF_REG08(0xFC0C000C) #define MCF_PLL_PFDR 0xFC0C000C
/* Bit definitions and macros for MCF_PLL_PODR */ /* Bit definitions and macros for MCF_PLL_PODR */
#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0) #define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0)
...@@ -1951,15 +1133,15 @@ ...@@ -1951,15 +1133,15 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_SCM_MPR MCF_REG32(0xFC000000) #define MCF_SCM_MPR 0xFC000000
#define MCF_SCM_PACRA MCF_REG32(0xFC000020) #define MCF_SCM_PACRA 0xFC000020
#define MCF_SCM_PACRB MCF_REG32(0xFC000024) #define MCF_SCM_PACRB 0xFC000024
#define MCF_SCM_PACRC MCF_REG32(0xFC000028) #define MCF_SCM_PACRC 0xFC000028
#define MCF_SCM_PACRD MCF_REG32(0xFC00002C) #define MCF_SCM_PACRD 0xFC00002C
#define MCF_SCM_PACRE MCF_REG32(0xFC000040) #define MCF_SCM_PACRE 0xFC000040
#define MCF_SCM_PACRF MCF_REG32(0xFC000044) #define MCF_SCM_PACRF 0xFC000044
#define MCF_SCM_BCR MCF_REG32(0xFC040024) #define MCF_SCM_BCR 0xFC040024
/********************************************************************* /*********************************************************************
* *
...@@ -1968,17 +1150,16 @@ ...@@ -1968,17 +1150,16 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_SDRAMC_SDMR MCF_REG32(0xFC0B8000) #define MCF_SDRAMC_SDMR 0xFC0B8000
#define MCF_SDRAMC_SDCR MCF_REG32(0xFC0B8004) #define MCF_SDRAMC_SDCR 0xFC0B8004
#define MCF_SDRAMC_SDCFG1 MCF_REG32(0xFC0B8008) #define MCF_SDRAMC_SDCFG1 0xFC0B8008
#define MCF_SDRAMC_SDCFG2 MCF_REG32(0xFC0B800C) #define MCF_SDRAMC_SDCFG2 0xFC0B800C
#define MCF_SDRAMC_LIMP_FIX MCF_REG32(0xFC0B8080) #define MCF_SDRAMC_LIMP_FIX 0xFC0B8080
#define MCF_SDRAMC_SDDS MCF_REG32(0xFC0B8100) #define MCF_SDRAMC_SDDS 0xFC0B8100
#define MCF_SDRAMC_SDCS0 MCF_REG32(0xFC0B8110) #define MCF_SDRAMC_SDCS0 0xFC0B8110
#define MCF_SDRAMC_SDCS1 MCF_REG32(0xFC0B8114) #define MCF_SDRAMC_SDCS1 0xFC0B8114
#define MCF_SDRAMC_SDCS2 MCF_REG32(0xFC0B8118) #define MCF_SDRAMC_SDCS2 0xFC0B8118
#define MCF_SDRAMC_SDCS3 MCF_REG32(0xFC0B811C) #define MCF_SDRAMC_SDCS3 0xFC0B811C
#define MCF_SDRAMC_SDCS(x) MCF_REG32(0xFC0B8110+((x)*0x004))
/* Bit definitions and macros for MCF_SDRAMC_SDMR */ /* Bit definitions and macros for MCF_SDRAMC_SDMR */
#define MCF_SDRAMC_SDMR_CMD (0x00010000) #define MCF_SDRAMC_SDMR_CMD (0x00010000)
...@@ -2046,143 +1227,9 @@ ...@@ -2046,143 +1227,9 @@
#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) #define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) #define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
/*********************************************************************
*
* FlexCAN module registers
*
*********************************************************************/
#define MCF_FLEXCAN_BASEADDR(x) (0xFC020000+(x)*0x0800)
#define MCF_FLEXCAN_CANMCR(x) MCF_REG32(0xFC020000+(x)*0x0800+0x00)
#define MCF_FLEXCAN_CANCTRL(x) MCF_REG32(0xFC020000+(x)*0x0800+0x04)
#define MCF_FLEXCAN_TIMER(x) MCF_REG32(0xFC020000+(x)*0x0800+0x08)
#define MCF_FLEXCAN_RXGMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x10)
#define MCF_FLEXCAN_RX14MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x14)
#define MCF_FLEXCAN_RX15MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x18)
#define MCF_FLEXCAN_ERRCNT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x1C)
#define MCF_FLEXCAN_ERRSTAT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x20)
#define MCF_FLEXCAN_IMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x28)
#define MCF_FLEXCAN_IFLAG(x) MCF_REG32(0xFC020000+(x)*0x0800+0x30)
#define MCF_FLEXCAN_MB_CNT(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0)
#define MCF_FLEXCAN_MB_ID(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4)
#define MCF_FLEXCAN_MB_DB(x,y,z) MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1)
/*
* FlexCAN Module Configuration Register
*/
#define CANMCR_MDIS (0x80000000)
#define CANMCR_FRZ (0x40000000)
#define CANMCR_HALT (0x10000000)
#define CANMCR_SOFTRST (0x02000000)
#define CANMCR_FRZACK (0x01000000)
#define CANMCR_SUPV (0x00800000)
#define CANMCR_MAXMB(x) ((x)&0x0F)
/*
* FlexCAN Control Register
*/
#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
#define CANCTRL_RJW(x) (((x)&0x03)<<22)
#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
#define CANCTRL_BOFFMSK (0x00008000)
#define CANCTRL_ERRMSK (0x00004000)
#define CANCTRL_CLKSRC (0x00002000)
#define CANCTRL_LPB (0x00001000)
#define CANCTRL_SAMP (0x00000080)
#define CANCTRL_BOFFREC (0x00000040)
#define CANCTRL_TSYNC (0x00000020)
#define CANCTRL_LBUF (0x00000010)
#define CANCTRL_LOM (0x00000008)
#define CANCTRL_PROPSEG(x) ((x)&0x07)
/*
* FlexCAN Error Counter Register
*/
#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
#define ERRCNT_TXECTR(x) ((x)&0xFF)
/*
* FlexCAN Error and Status Register
*/
#define ERRSTAT_BITERR(x) (((x)&0x03)<<14)
#define ERRSTAT_ACKERR (0x00002000)
#define ERRSTAT_CRCERR (0x00001000)
#define ERRSTAT_FRMERR (0x00000800)
#define ERRSTAT_STFERR (0x00000400)
#define ERRSTAT_TXWRN (0x00000200)
#define ERRSTAT_RXWRN (0x00000100)
#define ERRSTAT_IDLE (0x00000080)
#define ERRSTAT_TXRX (0x00000040)
#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4)
#define ERRSTAT_BOFFINT (0x00000004)
#define ERRSTAT_ERRINT (0x00000002)
/* /*
* Interrupt Mask Register
*/
#define IMASK_BUF15M (0x8000)
#define IMASK_BUF14M (0x4000)
#define IMASK_BUF13M (0x2000)
#define IMASK_BUF12M (0x1000)
#define IMASK_BUF11M (0x0800)
#define IMASK_BUF10M (0x0400)
#define IMASK_BUF9M (0x0200)
#define IMASK_BUF8M (0x0100)
#define IMASK_BUF7M (0x0080)
#define IMASK_BUF6M (0x0040)
#define IMASK_BUF5M (0x0020)
#define IMASK_BUF4M (0x0010)
#define IMASK_BUF3M (0x0008)
#define IMASK_BUF2M (0x0004)
#define IMASK_BUF1M (0x0002)
#define IMASK_BUF0M (0x0001)
#define IMASK_BUFnM(x) (0x1<<(x))
#define IMASK_BUFF_ENABLE_ALL (0x1111)
#define IMASK_BUFF_DISABLE_ALL (0x0000)
/*
* Interrupt Flag Register
*/
#define IFLAG_BUF15M (0x8000)
#define IFLAG_BUF14M (0x4000)
#define IFLAG_BUF13M (0x2000)
#define IFLAG_BUF12M (0x1000)
#define IFLAG_BUF11M (0x0800)
#define IFLAG_BUF10M (0x0400)
#define IFLAG_BUF9M (0x0200)
#define IFLAG_BUF8M (0x0100)
#define IFLAG_BUF7M (0x0080)
#define IFLAG_BUF6M (0x0040)
#define IFLAG_BUF5M (0x0020)
#define IFLAG_BUF4M (0x0010)
#define IFLAG_BUF3M (0x0008)
#define IFLAG_BUF2M (0x0004)
#define IFLAG_BUF1M (0x0002)
#define IFLAG_BUF0M (0x0001)
#define IFLAG_BUFF_SET_ALL (0xFFFF)
#define IFLAG_BUFF_CLEAR_ALL (0x0000)
#define IFLAG_BUFnM(x) (0x1<<(x))
/*
* Message Buffers
*/
#define MB_CNT_CODE(x) (((x)&0x0F)<<24)
#define MB_CNT_SRR (0x00400000)
#define MB_CNT_IDE (0x00200000)
#define MB_CNT_RTR (0x00100000)
#define MB_CNT_LENGTH(x) (((x)&0x0F)<<16)
#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF)
#define MB_ID_STD(x) (((x)&0x07FF)<<18)
#define MB_ID_EXT(x) ((x)&0x3FFFF)
/*********************************************************************
*
* Edge Port Module (EPORT) * Edge Port Module (EPORT)
* */
*********************************************************************/
/* Register read/write macros */
#define MCFEPORT_EPPAR (0xFC094000) #define MCFEPORT_EPPAR (0xFC094000)
#define MCFEPORT_EPDDR (0xFC094002) #define MCFEPORT_EPDDR (0xFC094002)
#define MCFEPORT_EPIER (0xFC094003) #define MCFEPORT_EPIER (0xFC094003)
...@@ -2190,91 +1237,5 @@ ...@@ -2190,91 +1237,5 @@
#define MCFEPORT_EPPDR (0xFC094005) #define MCFEPORT_EPPDR (0xFC094005)
#define MCFEPORT_EPFR (0xFC094006) #define MCFEPORT_EPFR (0xFC094006)
/* Bit definitions and macros for MCF_EPORT_EPPAR */
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
#define MCF_EPORT_EPPAR_LEVEL (0)
#define MCF_EPORT_EPPAR_RISING (1)
#define MCF_EPORT_EPPAR_FALLING (2)
#define MCF_EPORT_EPPAR_BOTH (3)
#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
/* Bit definitions and macros for MCF_EPORT_EPDDR */
#define MCF_EPORT_EPDDR_EPDD1 (0x02)
#define MCF_EPORT_EPDDR_EPDD2 (0x04)
#define MCF_EPORT_EPDDR_EPDD3 (0x08)
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPIER */
#define MCF_EPORT_EPIER_EPIE1 (0x02)
#define MCF_EPORT_EPIER_EPIE2 (0x04)
#define MCF_EPORT_EPIER_EPIE3 (0x08)
#define MCF_EPORT_EPIER_EPIE4 (0x10)
#define MCF_EPORT_EPIER_EPIE5 (0x20)
#define MCF_EPORT_EPIER_EPIE6 (0x40)
#define MCF_EPORT_EPIER_EPIE7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPDR */
#define MCF_EPORT_EPDR_EPD1 (0x02)
#define MCF_EPORT_EPDR_EPD2 (0x04)
#define MCF_EPORT_EPDR_EPD3 (0x08)
#define MCF_EPORT_EPDR_EPD4 (0x10)
#define MCF_EPORT_EPDR_EPD5 (0x20)
#define MCF_EPORT_EPDR_EPD6 (0x40)
#define MCF_EPORT_EPDR_EPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPPDR */
#define MCF_EPORT_EPPDR_EPPD1 (0x02)
#define MCF_EPORT_EPPDR_EPPD2 (0x04)
#define MCF_EPORT_EPPDR_EPPD3 (0x08)
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPFR */
#define MCF_EPORT_EPFR_EPF1 (0x02)
#define MCF_EPORT_EPFR_EPF2 (0x04)
#define MCF_EPORT_EPFR_EPF3 (0x08)
#define MCF_EPORT_EPFR_EPF4 (0x10)
#define MCF_EPORT_EPFR_EPF5 (0x20)
#define MCF_EPORT_EPFR_EPF6 (0x40)
#define MCF_EPORT_EPFR_EPF7 (0x80)
/********************************************************************/ /********************************************************************/
#endif /* m532xsim_h */ #endif /* m532xsim_h */
...@@ -23,55 +23,55 @@ ...@@ -23,55 +23,55 @@
/* /*
* Define the 5407 SIM register set addresses. * Define the 5407 SIM register set addresses.
*/ */
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/ #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ #define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ #define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ #define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ #define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ #define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ #define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
...@@ -102,9 +102,9 @@ ...@@ -102,9 +102,9 @@
/* /*
* Generic GPIO support * Generic GPIO support
*/ */
#define MCFGPIO_PIN_MAX 16 #define MCFGPIO_PIN_MAX 16
#define MCFGPIO_IRQ_MAX -1 #define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1 #define MCFGPIO_IRQ_VECBASE -1
/* /*
* Some symbol defines for the above... * Some symbol defines for the above...
...@@ -130,9 +130,9 @@ ...@@ -130,9 +130,9 @@
/* /*
* Defines for the IRQPAR Register * Defines for the IRQPAR Register
*/ */
#define IRQ5_LEVEL4 0x80 #define IRQ5_LEVEL4 0x80
#define IRQ3_LEVEL6 0x40 #define IRQ3_LEVEL6 0x40
#define IRQ1_LEVEL2 0x20 #define IRQ1_LEVEL2 0x20
/* /*
* Define system peripheral IRQ usage. * Define system peripheral IRQ usage.
......
...@@ -16,26 +16,26 @@ ...@@ -16,26 +16,26 @@
*********************************************************************/ *********************************************************************/
/* Register read/write macros */ /* Register read/write macros */
#define MCF_GPT_GMS0 0x000800 #define MCF_GPT_GMS0 (MCF_MBAR + 0x000800)
#define MCF_GPT_GCIR0 0x000804 #define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804)
#define MCF_GPT_GPWM0 0x000808 #define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808)
#define MCF_GPT_GSR0 0x00080C #define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C)
#define MCF_GPT_GMS1 0x000810 #define MCF_GPT_GMS1 (MCF_MBAR + 0x000810)
#define MCF_GPT_GCIR1 0x000814 #define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814)
#define MCF_GPT_GPWM1 0x000818 #define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818)
#define MCF_GPT_GSR1 0x00081C #define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C)
#define MCF_GPT_GMS2 0x000820 #define MCF_GPT_GMS2 (MCF_MBAR + 0x000820)
#define MCF_GPT_GCIR2 0x000824 #define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824)
#define MCF_GPT_GPWM2 0x000828 #define MCF_GPT_GPWM2 (MCF_MBAR + 0x000828)
#define MCF_GPT_GSR2 0x00082C #define MCF_GPT_GSR2 (MCF_MBAR + 0x00082C)
#define MCF_GPT_GMS3 0x000830 #define MCF_GPT_GMS3 (MCF_MBAR + 0x000830)
#define MCF_GPT_GCIR3 0x000834 #define MCF_GPT_GCIR3 (MCF_MBAR + 0x000834)
#define MCF_GPT_GPWM3 0x000838 #define MCF_GPT_GPWM3 (MCF_MBAR + 0x000838)
#define MCF_GPT_GSR3 0x00083C #define MCF_GPT_GSR3 (MCF_MBAR + 0x00083C)
#define MCF_GPT_GMS(x) (0x000800+((x)*0x010)) #define MCF_GPT_GMS(x) (MCF_MBAR + 0x000800 + ((x) * 0x010))
#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010)) #define MCF_GPT_GCIR(x) (MCF_MBAR + 0x000804 + ((x) * 0x010))
#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010)) #define MCF_GPT_GPWM(x) (MCF_MBAR + 0x000808 + ((x) * 0x010))
#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010)) #define MCF_GPT_GSR(x) (MCF_MBAR + 0x00080C + ((x) * 0x010))
/* Bit definitions and macros for MCF_GPT_GMS */ /* Bit definitions and macros for MCF_GPT_GMS */
#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) #define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
......
...@@ -46,6 +46,12 @@ ...@@ -46,6 +46,12 @@
#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33) #define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
#define MCF_IRQ_UART3 (MCFINT_VECBASE + 32) #define MCF_IRQ_UART3 (MCFINT_VECBASE + 32)
/*
* Slice Timer support.
*/
#define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */
#define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */
/* /*
* Generic GPIO support * Generic GPIO support
*/ */
...@@ -64,15 +70,25 @@ ...@@ -64,15 +70,25 @@
#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ #define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
/* /*
* Some PSC related definitions * Pin Assignment register definitions
*/ */
#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3)) #define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40)
#define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42)
#define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43)
#define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44)
#define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */
#define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */
#define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F)
#define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E)
#define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D)
#define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C)
#define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50)
#define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52)
#define MCF_PAR_SDA (0x0008) #define MCF_PAR_SDA (0x0008)
#define MCF_PAR_SCL (0x0004) #define MCF_PAR_SCL (0x0004)
#define MCF_PAR_PSC_TXD (0x04) #define MCF_PAR_PSC_TXD (0x04)
#define MCF_PAR_PSC_RXD (0x08) #define MCF_PAR_PSC_RXD (0x08)
#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
#define MCF_PAR_PSC_CTS_GPIO (0x00) #define MCF_PAR_PSC_CTS_GPIO (0x00)
#define MCF_PAR_PSC_CTS_BCLK (0x80) #define MCF_PAR_PSC_CTS_BCLK (0x80)
#define MCF_PAR_PSC_CTS_CTS (0xC0) #define MCF_PAR_PSC_CTS_CTS (0xC0)
...@@ -81,7 +97,4 @@ ...@@ -81,7 +97,4 @@
#define MCF_PAR_PSC_RTS_RTS (0x30) #define MCF_PAR_PSC_RTS_RTS (0x30)
#define MCF_PAR_PSC_CANRX (0x40) #define MCF_PAR_PSC_CANRX (0x40)
#define MCF_PAR_PCIBG (CONFIG_MBAR + 0xa48) /* PCI bus grant */
#define MCF_PAR_PCIBR (CONFIG_MBAR + 0xa4a) /* PCI */
#endif /* m54xxsim_h */ #endif /* m54xxsim_h */
...@@ -12,13 +12,6 @@ ...@@ -12,13 +12,6 @@
#define mcfslt_h #define mcfslt_h
/****************************************************************************/ /****************************************************************************/
/*
* Get address specific defines for the 547x.
*/
#define MCFSLT_TIMER0 0x900 /* Base address of TIMER0 */
#define MCFSLT_TIMER1 0x910 /* Base address of TIMER1 */
/* /*
* Define the SLT timer register set addresses. * Define the SLT timer register set addresses.
*/ */
......
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#ifdef CONFIG_COLDFIRE #ifdef CONFIG_COLDFIRE
#include <asm/coldfire.h> #include <asm/coldfire.h>
#include <asm/mcfsim.h> #include <asm/mcfsim.h>
#include <asm/io.h>
#endif #endif
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
...@@ -86,16 +87,12 @@ static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) ...@@ -86,16 +87,12 @@ static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
*/ */
static __inline__ unsigned int mcf_getppdata(void) static __inline__ unsigned int mcf_getppdata(void)
{ {
volatile unsigned short *pp; return readw(MCFSIM_PBDAT);
pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
return((unsigned int) *pp);
} }
static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
{ {
volatile unsigned short *pp; write((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT);
pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
*pp = (*pp & ~mask) | bits;
} }
#endif #endif
......
# #
# Makefile for arch/m68knommu/platform/68VZ328. # Makefile for arch/m68k/platform/68VZ328.
# #
obj-y := config.o obj-y := config.o
extra-$(DRAGEN2):= screen.h
$(obj)/screen.h: $(src)/screen.xbm $(src)/xbm2lcd.pl
perl $(src)/xbm2lcd.pl < $(src)/screen.xbm > $(obj)/screen.h
clean-files := $(obj)/screen.h
...@@ -347,12 +347,12 @@ static void __init mcf_uart_set_irq(void) ...@@ -347,12 +347,12 @@ static void __init mcf_uart_set_irq(void)
{ {
#ifdef MCFUART_UIVR #ifdef MCFUART_UIVR
/* UART0 interrupt setup */ /* UART0 interrupt setup */
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR); writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0); mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
/* UART1 interrupt setup */ /* UART1 interrupt setup */
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR); writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1); mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
#endif #endif
......
...@@ -60,7 +60,7 @@ ...@@ -60,7 +60,7 @@
#elif defined(CONFIG_M5272) #elif defined(CONFIG_M5272)
.macro GET_MEM_SIZE .macro GET_MEM_SIZE
movel MCF_MBAR+MCFSIM_CSOR7,%d0 /* get SDRAM address mask */ movel MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
andil #0xfffff000,%d0 /* mask out chip select options */ andil #0xfffff000,%d0 /* mask out chip select options */
negl %d0 /* negate bits */ negl %d0 /* negate bits */
.endm .endm
......
...@@ -20,22 +20,22 @@ ...@@ -20,22 +20,22 @@
static void intc2_irq_gpio_mask(struct irq_data *d) static void intc2_irq_gpio_mask(struct irq_data *d)
{ {
u32 imr; u32 imr;
imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); imr = readl(MCFSIM2_GPIOINTENABLE);
imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0)); imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); writel(imr, MCFSIM2_GPIOINTENABLE);
} }
static void intc2_irq_gpio_unmask(struct irq_data *d) static void intc2_irq_gpio_unmask(struct irq_data *d)
{ {
u32 imr; u32 imr;
imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); imr = readl(MCFSIM2_GPIOINTENABLE);
imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0)); imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); writel(imr, MCFSIM2_GPIOINTENABLE);
} }
static void intc2_irq_gpio_ack(struct irq_data *d) static void intc2_irq_gpio_ack(struct irq_data *d)
{ {
writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR); writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCFSIM2_GPIOINTCLEAR);
} }
static struct irq_chip intc2_irq_gpio_chip = { static struct irq_chip intc2_irq_gpio_chip = {
......
...@@ -86,7 +86,7 @@ static void intc_irq_mask(struct irq_data *d) ...@@ -86,7 +86,7 @@ static void intc_irq_mask(struct irq_data *d)
u32 v; u32 v;
irq -= MCFINT_VECBASE; irq -= MCFINT_VECBASE;
v = 0x8 << intc_irqmap[irq].index; v = 0x8 << intc_irqmap[irq].index;
writel(v, MCF_MBAR + intc_irqmap[irq].icr); writel(v, intc_irqmap[irq].icr);
} }
} }
...@@ -98,7 +98,7 @@ static void intc_irq_unmask(struct irq_data *d) ...@@ -98,7 +98,7 @@ static void intc_irq_unmask(struct irq_data *d)
u32 v; u32 v;
irq -= MCFINT_VECBASE; irq -= MCFINT_VECBASE;
v = 0xd << intc_irqmap[irq].index; v = 0xd << intc_irqmap[irq].index;
writel(v, MCF_MBAR + intc_irqmap[irq].icr); writel(v, intc_irqmap[irq].icr);
} }
} }
...@@ -111,10 +111,10 @@ static void intc_irq_ack(struct irq_data *d) ...@@ -111,10 +111,10 @@ static void intc_irq_ack(struct irq_data *d)
irq -= MCFINT_VECBASE; irq -= MCFINT_VECBASE;
if (intc_irqmap[irq].ack) { if (intc_irqmap[irq].ack) {
u32 v; u32 v;
v = readl(MCF_MBAR + intc_irqmap[irq].icr); v = readl(intc_irqmap[irq].icr);
v &= (0x7 << intc_irqmap[irq].index); v &= (0x7 << intc_irqmap[irq].index);
v |= (0x8 << intc_irqmap[irq].index); v |= (0x8 << intc_irqmap[irq].index);
writel(v, MCF_MBAR + intc_irqmap[irq].icr); writel(v, intc_irqmap[irq].icr);
} }
} }
} }
...@@ -127,12 +127,12 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type) ...@@ -127,12 +127,12 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
irq -= MCFINT_VECBASE; irq -= MCFINT_VECBASE;
if (intc_irqmap[irq].ack) { if (intc_irqmap[irq].ack) {
u32 v; u32 v;
v = readl(MCF_MBAR + MCFSIM_PITR); v = readl(MCFSIM_PITR);
if (type == IRQ_TYPE_EDGE_FALLING) if (type == IRQ_TYPE_EDGE_FALLING)
v &= ~(0x1 << (32 - irq)); v &= ~(0x1 << (32 - irq));
else else
v |= (0x1 << (32 - irq)); v |= (0x1 << (32 - irq));
writel(v, MCF_MBAR + MCFSIM_PITR); writel(v, MCFSIM_PITR);
} }
} }
return 0; return 0;
...@@ -163,10 +163,10 @@ void __init init_IRQ(void) ...@@ -163,10 +163,10 @@ void __init init_IRQ(void)
int irq, edge; int irq, edge;
/* Mask all interrupt sources */ /* Mask all interrupt sources */
writel(0x88888888, MCF_MBAR + MCFSIM_ICR1); writel(0x88888888, MCFSIM_ICR1);
writel(0x88888888, MCF_MBAR + MCFSIM_ICR2); writel(0x88888888, MCFSIM_ICR2);
writel(0x88888888, MCF_MBAR + MCFSIM_ICR3); writel(0x88888888, MCFSIM_ICR3);
writel(0x88888888, MCF_MBAR + MCFSIM_ICR4); writel(0x88888888, MCFSIM_ICR4);
for (irq = 0; (irq < NR_IRQS); irq++) { for (irq = 0; (irq < NR_IRQS); irq++) {
irq_set_chip(irq, &intc_irq_chip); irq_set_chip(irq, &intc_irq_chip);
......
...@@ -45,23 +45,23 @@ unsigned char mcf_irq2imr[NR_IRQS]; ...@@ -45,23 +45,23 @@ unsigned char mcf_irq2imr[NR_IRQS];
void mcf_setimr(int index) void mcf_setimr(int index)
{ {
u16 imr; u16 imr;
imr = __raw_readw(MCF_MBAR + MCFSIM_IMR); imr = __raw_readw(MCFSIM_IMR);
__raw_writew(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR); __raw_writew(imr | (0x1 << index), MCFSIM_IMR);
} }
void mcf_clrimr(int index) void mcf_clrimr(int index)
{ {
u16 imr; u16 imr;
imr = __raw_readw(MCF_MBAR + MCFSIM_IMR); imr = __raw_readw(MCFSIM_IMR);
__raw_writew(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR); __raw_writew(imr & ~(0x1 << index), MCFSIM_IMR);
} }
void mcf_maskimr(unsigned int mask) void mcf_maskimr(unsigned int mask)
{ {
u16 imr; u16 imr;
imr = __raw_readw(MCF_MBAR + MCFSIM_IMR); imr = __raw_readw(MCFSIM_IMR);
imr |= mask; imr |= mask;
__raw_writew(imr, MCF_MBAR + MCFSIM_IMR); __raw_writew(imr, MCFSIM_IMR);
} }
#else #else
...@@ -69,23 +69,23 @@ void mcf_maskimr(unsigned int mask) ...@@ -69,23 +69,23 @@ void mcf_maskimr(unsigned int mask)
void mcf_setimr(int index) void mcf_setimr(int index)
{ {
u32 imr; u32 imr;
imr = __raw_readl(MCF_MBAR + MCFSIM_IMR); imr = __raw_readl(MCFSIM_IMR);
__raw_writel(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR); __raw_writel(imr | (0x1 << index), MCFSIM_IMR);
} }
void mcf_clrimr(int index) void mcf_clrimr(int index)
{ {
u32 imr; u32 imr;
imr = __raw_readl(MCF_MBAR + MCFSIM_IMR); imr = __raw_readl(MCFSIM_IMR);
__raw_writel(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR); __raw_writel(imr & ~(0x1 << index), MCFSIM_IMR);
} }
void mcf_maskimr(unsigned int mask) void mcf_maskimr(unsigned int mask)
{ {
u32 imr; u32 imr;
imr = __raw_readl(MCF_MBAR + MCFSIM_IMR); imr = __raw_readl(MCFSIM_IMR);
imr |= mask; imr |= mask;
__raw_writel(imr, MCF_MBAR + MCFSIM_IMR); __raw_writel(imr, MCFSIM_IMR);
} }
#endif #endif
...@@ -104,9 +104,9 @@ void mcf_autovector(int irq) ...@@ -104,9 +104,9 @@ void mcf_autovector(int irq)
#ifdef MCFSIM_AVR #ifdef MCFSIM_AVR
if ((irq >= EIRQ1) && (irq <= EIRQ7)) { if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
u8 avec; u8 avec;
avec = __raw_readb(MCF_MBAR + MCFSIM_AVR); avec = __raw_readb(MCFSIM_AVR);
avec |= (0x1 << (irq - EIRQ1 + 1)); avec |= (0x1 << (irq - EIRQ1 + 1));
__raw_writeb(avec, MCF_MBAR + MCFSIM_AVR); __raw_writeb(avec, MCFSIM_AVR);
} }
#endif #endif
} }
......
...@@ -42,14 +42,8 @@ static void __init m523x_qspi_init(void) ...@@ -42,14 +42,8 @@ static void __init m523x_qspi_init(void)
static void __init m523x_fec_init(void) static void __init m523x_fec_init(void)
{ {
u16 par;
u8 v;
/* Set multi-function pins to ethernet use */ /* Set multi-function pins to ethernet use */
par = readw(MCF_IPSBAR + 0x100082); writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
writew(par | 0xf00, MCF_IPSBAR + 0x100082);
v = readb(MCF_IPSBAR + 0x100078);
writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
} }
/***************************************************************************/ /***************************************************************************/
......
...@@ -57,7 +57,7 @@ static void __init m5249_qspi_init(void) ...@@ -57,7 +57,7 @@ static void __init m5249_qspi_init(void)
{ {
/* QSPI irq setup */ /* QSPI irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
MCF_MBAR + MCFSIM_QSPIICR); MCFSIM_QSPIICR);
mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
} }
...@@ -72,11 +72,11 @@ static void __init m5249_smc91x_init(void) ...@@ -72,11 +72,11 @@ static void __init m5249_smc91x_init(void)
u32 gpio; u32 gpio;
/* Set the GPIO line as interrupt source for smc91x device */ /* Set the GPIO line as interrupt source for smc91x device */
gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); gpio = readl(MCFSIM2_GPIOINTENABLE);
writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5); gpio = readl(MCFSIM2_INTLEVEL5);
writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5); writel(gpio | 0x04000000, MCFSIM2_INTLEVEL5);
} }
#endif /* CONFIG_M5249C3 */ #endif /* CONFIG_M5249C3 */
......
...@@ -30,7 +30,7 @@ static void __init m525x_qspi_init(void) ...@@ -30,7 +30,7 @@ static void __init m525x_qspi_init(void)
/* QSPI irq setup */ /* QSPI irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
MCF_MBAR + MCFSIM_QSPIICR); MCFSIM_QSPIICR);
mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
} }
...@@ -42,7 +42,7 @@ static void __init m525x_i2c_init(void) ...@@ -42,7 +42,7 @@ static void __init m525x_i2c_init(void)
/* first I2C controller uses regular irq setup */ /* first I2C controller uses regular irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCF_MBAR + MCFSIM_I2CICR); MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C); mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
/* second I2C controller is completely different */ /* second I2C controller is completely different */
......
...@@ -35,13 +35,13 @@ static void __init m5272_uarts_init(void) ...@@ -35,13 +35,13 @@ static void __init m5272_uarts_init(void)
u32 v; u32 v;
/* Enable the output lines for the serial ports */ /* Enable the output lines for the serial ports */
v = readl(MCF_MBAR + MCFSIM_PBCNT); v = readl(MCFSIM_PBCNT);
v = (v & ~0x000000ff) | 0x00000055; v = (v & ~0x000000ff) | 0x00000055;
writel(v, MCF_MBAR + MCFSIM_PBCNT); writel(v, MCFSIM_PBCNT);
v = readl(MCF_MBAR + MCFSIM_PDCNT); v = readl(MCFSIM_PDCNT);
v = (v & ~0x000003fc) | 0x000002a8; v = (v & ~0x000003fc) | 0x000002a8;
writel(v, MCF_MBAR + MCFSIM_PDCNT); writel(v, MCFSIM_PDCNT);
} }
/***************************************************************************/ /***************************************************************************/
...@@ -50,9 +50,9 @@ static void m5272_cpu_reset(void) ...@@ -50,9 +50,9 @@ static void m5272_cpu_reset(void)
{ {
local_irq_disable(); local_irq_disable();
/* Set watchdog to reset, and enabled */ /* Set watchdog to reset, and enabled */
__raw_writew(0, MCF_MBAR + MCFSIM_WIRR); __raw_writew(0, MCFSIM_WIRR);
__raw_writew(1, MCF_MBAR + MCFSIM_WRRR); __raw_writew(1, MCFSIM_WRRR);
__raw_writew(0, MCF_MBAR + MCFSIM_WCR); __raw_writew(0, MCFSIM_WCR);
for (;;) for (;;)
/* wait for watchdog to timeout */; /* wait for watchdog to timeout */;
} }
...@@ -62,11 +62,8 @@ static void m5272_cpu_reset(void) ...@@ -62,11 +62,8 @@ static void m5272_cpu_reset(void)
void __init config_BSP(char *commandp, int size) void __init config_BSP(char *commandp, int size)
{ {
#if defined (CONFIG_MOD5272) #if defined (CONFIG_MOD5272)
volatile unsigned char *pivrp;
/* Set base of device vectors to be 64 */ /* Set base of device vectors to be 64 */
pivrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_PIVR); writeb(0x40, MCFSIM_PIVR);
*pivrp = 0x40;
#endif #endif
#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES) #if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
......
...@@ -53,9 +53,9 @@ static void __init m527x_uarts_init(void) ...@@ -53,9 +53,9 @@ static void __init m527x_uarts_init(void)
/* /*
* External Pin Mask Setting & Enable External Pin for Interface * External Pin Mask Setting & Enable External Pin for Interface
*/ */
sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); sepmask = readw(MCFGPIO_PAR_UART);
sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK; sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART); writew(sepmask, MCFGPIO_PAR_UART);
} }
/***************************************************************************/ /***************************************************************************/
...@@ -67,19 +67,19 @@ static void __init m527x_fec_init(void) ...@@ -67,19 +67,19 @@ static void __init m527x_fec_init(void)
/* Set multi-function pins to ethernet mode for fec0 */ /* Set multi-function pins to ethernet mode for fec0 */
#if defined(CONFIG_M5271) #if defined(CONFIG_M5271)
v = readb(MCF_IPSBAR + 0x100047); v = readb(MCFGPIO_PAR_FECI2C);
writeb(v | 0xf0, MCF_IPSBAR + 0x100047); writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
#else #else
par = readw(MCF_IPSBAR + 0x100082); par = readw(MCFGPIO_PAR_FECI2C);
writew(par | 0xf00, MCF_IPSBAR + 0x100082); writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
v = readb(MCF_IPSBAR + 0x100078); v = readb(MCFGPIO_PAR_FEC0HL);
writeb(v | 0xc0, MCF_IPSBAR + 0x100078); writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
/* Set multi-function pins to ethernet mode for fec1 */ /* Set multi-function pins to ethernet mode for fec1 */
par = readw(MCF_IPSBAR + 0x100082); par = readw(MCFGPIO_PAR_FECI2C);
writew(par | 0xa0, MCF_IPSBAR + 0x100082); writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
v = readb(MCF_IPSBAR + 0x100079); v = readb(MCFGPIO_PAR_FEC1HL);
writeb(v | 0xc0, MCF_IPSBAR + 0x100079); writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
#endif #endif
} }
......
...@@ -53,9 +53,9 @@ static void __init m528x_fec_init(void) ...@@ -53,9 +53,9 @@ static void __init m528x_fec_init(void)
u16 v16; u16 v16;
/* Set multi-function pins to ethernet mode for fec0 */ /* Set multi-function pins to ethernet mode for fec0 */
v16 = readw(MCF_IPSBAR + 0x100056); v16 = readw(MCFGPIO_PASPAR);
writew(v16 | 0xf00, MCF_IPSBAR + 0x100056); writew(v16 | 0xf00, MCFGPIO_PASPAR);
writeb(0xc0, MCF_IPSBAR + 0x100058); writeb(0xc0, MCFGPIO_PEHLPAR);
} }
/***************************************************************************/ /***************************************************************************/
......
...@@ -172,7 +172,7 @@ static void __init m532x_clk_init(void) ...@@ -172,7 +172,7 @@ static void __init m532x_clk_init(void)
static void __init m532x_qspi_init(void) static void __init m532x_qspi_init(void)
{ {
/* setup QSPS pins for QSPI with gpio CS control */ /* setup QSPS pins for QSPI with gpio CS control */
writew(0x01f0, MCF_GPIO_PAR_QSPI); writew(0x01f0, MCFGPIO_PAR_QSPI);
} }
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
...@@ -182,18 +182,24 @@ static void __init m532x_qspi_init(void) ...@@ -182,18 +182,24 @@ static void __init m532x_qspi_init(void)
static void __init m532x_uarts_init(void) static void __init m532x_uarts_init(void)
{ {
/* UART GPIO initialization */ /* UART GPIO initialization */
MCF_GPIO_PAR_UART |= 0x0FFF; writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
} }
/***************************************************************************/ /***************************************************************************/
static void __init m532x_fec_init(void) static void __init m532x_fec_init(void)
{ {
u8 v;
/* Set multi-function pins to ethernet mode for fec0 */ /* Set multi-function pins to ethernet mode for fec0 */
MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC | v = readb(MCFGPIO_PAR_FECI2C);
MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO); v |= MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO;
MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC); writeb(v, MCFGPIO_PAR_FECI2C);
v = readb(MCFGPIO_PAR_FEC);
v = MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC;
writeb(v, MCFGPIO_PAR_FEC);
} }
/***************************************************************************/ /***************************************************************************/
...@@ -298,7 +304,7 @@ asmlinkage void __init sysinit(void) ...@@ -298,7 +304,7 @@ asmlinkage void __init sysinit(void)
void wtm_init(void) void wtm_init(void)
{ {
/* Disable watchdog timer */ /* Disable watchdog timer */
MCF_WTM_WCR = 0; writew(0, MCF_WTM_WCR);
} }
#define MCF_SCM_BCR_GBW (0x00000100) #define MCF_SCM_BCR_GBW (0x00000100)
...@@ -307,53 +313,53 @@ void wtm_init(void) ...@@ -307,53 +313,53 @@ void wtm_init(void)
void scm_init(void) void scm_init(void)
{ {
/* All masters are trusted */ /* All masters are trusted */
MCF_SCM_MPR = 0x77777777; writel(0x77777777, MCF_SCM_MPR);
/* Allow supervisor/user, read/write, and trusted/untrusted /* Allow supervisor/user, read/write, and trusted/untrusted
access to all slaves */ access to all slaves */
MCF_SCM_PACRA = 0; writel(0, MCF_SCM_PACRA);
MCF_SCM_PACRB = 0; writel(0, MCF_SCM_PACRB);
MCF_SCM_PACRC = 0; writel(0, MCF_SCM_PACRC);
MCF_SCM_PACRD = 0; writel(0, MCF_SCM_PACRD);
MCF_SCM_PACRE = 0; writel(0, MCF_SCM_PACRE);
MCF_SCM_PACRF = 0; writel(0, MCF_SCM_PACRF);
/* Enable bursts */ /* Enable bursts */
MCF_SCM_BCR = (MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW); writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
} }
void fbcs_init(void) void fbcs_init(void)
{ {
MCF_GPIO_PAR_CS = 0x0000003E; writeb(0x3E, MCFGPIO_PAR_CS);
/* Latch chip select */ /* Latch chip select */
MCF_FBCS1_CSAR = 0x10080000; writel(0x10080000, MCF_FBCS1_CSAR);
MCF_FBCS1_CSCR = 0x002A3780; writel(0x002A3780, MCF_FBCS1_CSCR);
MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V); writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
/* Initialize latch to drive signals to inactive states */ /* Initialize latch to drive signals to inactive states */
*((u16 *)(0x10080000)) = 0xFFFF; writew(0xffff, 0x10080000);
/* External SRAM */ /* External SRAM */
MCF_FBCS1_CSAR = EXT_SRAM_ADDRESS; writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16 writel(MCF_FBCS_CSCR_PS_16 |
| MCF_FBCS_CSCR_AA MCF_FBCS_CSCR_AA |
| MCF_FBCS_CSCR_SBM MCF_FBCS_CSCR_SBM |
| MCF_FBCS_CSCR_WS(1)); MCF_FBCS_CSCR_WS(1),
MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K MCF_FBCS1_CSCR);
| MCF_FBCS_CSMR_V); writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
/* Boot Flash connected to FBCS0 */ /* Boot Flash connected to FBCS0 */
MCF_FBCS0_CSAR = FLASH_ADDRESS; writel(FLASH_ADDRESS, MCF_FBCS0_CSAR);
MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16 writel(MCF_FBCS_CSCR_PS_16 |
| MCF_FBCS_CSCR_BEM MCF_FBCS_CSCR_BEM |
| MCF_FBCS_CSCR_AA MCF_FBCS_CSCR_AA |
| MCF_FBCS_CSCR_SBM MCF_FBCS_CSCR_SBM |
| MCF_FBCS_CSCR_WS(7)); MCF_FBCS_CSCR_WS(7),
MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M MCF_FBCS0_CSCR);
| MCF_FBCS_CSMR_V); writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
} }
void sdramc_init(void) void sdramc_init(void)
...@@ -362,102 +368,102 @@ void sdramc_init(void) ...@@ -362,102 +368,102 @@ void sdramc_init(void)
* Check to see if the SDRAM has already been initialized * Check to see if the SDRAM has already been initialized
* by a run control tool * by a run control tool
*/ */
if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) { if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {
/* SDRAM chip select initialization */ /* SDRAM chip select initialization */
/* Initialize SDRAM chip select */ /* Initialize SDRAM chip select */
MCF_SDRAMC_SDCS0 = (0 writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
| MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE),
| MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE)); MCF_SDRAMC_SDCS0);
/* /*
* Basic configuration and initialization * Basic configuration and initialization
*/ */
MCF_SDRAMC_SDCFG1 = (0 writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
| MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 )) MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) |
| MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL * 2) + 2)) |
| MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2)) MCF_SDRAMC_SDCFG1_ACT2RW((int)(SDRAM_TRCD + 0.5)) |
| MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5)) MCF_SDRAMC_SDCFG1_PRE2ACT((int)(SDRAM_TRP + 0.5)) |
| MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5)) MCF_SDRAMC_SDCFG1_REF2ACT((int)(SDRAM_TRFC + 0.5)) |
| MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5)) MCF_SDRAMC_SDCFG1_WTLAT(3),
| MCF_SDRAMC_SDCFG1_WTLAT(3)); MCF_SDRAMC_SDCFG1);
MCF_SDRAMC_SDCFG2 = (0 writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
| MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1) MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL / 2 + SDRAM_TWR) |
| MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR) MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL / 2 - 1.0) + 0.5)) |
| MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL+SDRAM_BL/2-1.0)+0.5)) MCF_SDRAMC_SDCFG2_BL(SDRAM_BL - 1),
| MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1)); MCF_SDRAMC_SDCFG2);
/* /*
* Precharge and enable write to SDMR * Precharge and enable write to SDMR
*/ */
MCF_SDRAMC_SDCR = (0 writel(MCF_SDRAMC_SDCR_MODE_EN |
| MCF_SDRAMC_SDCR_MODE_EN MCF_SDRAMC_SDCR_CKE |
| MCF_SDRAMC_SDCR_CKE MCF_SDRAMC_SDCR_DDR |
| MCF_SDRAMC_SDCR_DDR MCF_SDRAMC_SDCR_MUX(1) |
| MCF_SDRAMC_SDCR_MUX(1) MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI / (SYSTEM_PERIOD * 64)) - 1) + 0.5)) |
| MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5)) MCF_SDRAMC_SDCR_PS_16 |
| MCF_SDRAMC_SDCR_PS_16 MCF_SDRAMC_SDCR_IPALL,
| MCF_SDRAMC_SDCR_IPALL); MCF_SDRAMC_SDCR);
/* /*
* Write extended mode register * Write extended mode register
*/ */
MCF_SDRAMC_SDMR = (0 writel(MCF_SDRAMC_SDMR_BNKAD_LEMR |
| MCF_SDRAMC_SDMR_BNKAD_LEMR MCF_SDRAMC_SDMR_AD(0x0) |
| MCF_SDRAMC_SDMR_AD(0x0) MCF_SDRAMC_SDMR_CMD,
| MCF_SDRAMC_SDMR_CMD); MCF_SDRAMC_SDMR);
/* /*
* Write mode register and reset DLL * Write mode register and reset DLL
*/ */
MCF_SDRAMC_SDMR = (0 writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
| MCF_SDRAMC_SDMR_BNKAD_LMR MCF_SDRAMC_SDMR_AD(0x163) |
| MCF_SDRAMC_SDMR_AD(0x163) MCF_SDRAMC_SDMR_CMD,
| MCF_SDRAMC_SDMR_CMD); MCF_SDRAMC_SDMR);
/* /*
* Execute a PALL command * Execute a PALL command
*/ */
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL; writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
/* /*
* Perform two REF cycles * Perform two REF cycles
*/ */
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
/* /*
* Write mode register and clear reset DLL * Write mode register and clear reset DLL
*/ */
MCF_SDRAMC_SDMR = (0 writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
| MCF_SDRAMC_SDMR_BNKAD_LMR MCF_SDRAMC_SDMR_AD(0x063) |
| MCF_SDRAMC_SDMR_AD(0x063) MCF_SDRAMC_SDMR_CMD,
| MCF_SDRAMC_SDMR_CMD); MCF_SDRAMC_SDMR);
/* /*
* Enable auto refresh and lock SDMR * Enable auto refresh and lock SDMR
*/ */
MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN; writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
MCF_SDRAMC_SDCR |= (0 MCF_SDRAMC_SDCR);
| MCF_SDRAMC_SDCR_REF writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
| MCF_SDRAMC_SDCR_DQS_OE(0xC)); MCF_SDRAMC_SDCR);
} }
} }
void gpio_init(void) void gpio_init(void)
{ {
/* Enable UART0 pins */ /* Enable UART0 pins */
MCF_GPIO_PAR_UART = ( 0 writew(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0,
| MCF_GPIO_PAR_UART_PAR_URXD0 MCFGPIO_PAR_UART);
| MCF_GPIO_PAR_UART_PAR_UTXD0);
/* Initialize TIN3 as a GPIO output to enable the write
half of the latch */
MCF_GPIO_PAR_TIMER = 0x00;
__raw_writeb(0x08, MCFGPIO_PDDR_TIMER);
__raw_writeb(0x00, MCFGPIO_PCLRR_TIMER);
/*
* Initialize TIN3 as a GPIO output to enable the write
* half of the latch.
*/
writeb(0x00, MCFGPIO_PAR_TIMER);
writeb(0x08, MCFGPIO_PDDR_TIMER);
writeb(0x00, MCFGPIO_PCLRR_TIMER);
} }
int clock_pll(int fsys, int flags) int clock_pll(int fsys, int flags)
...@@ -469,7 +475,7 @@ int clock_pll(int fsys, int flags) ...@@ -469,7 +475,7 @@ int clock_pll(int fsys, int flags)
if (fsys == 0) { if (fsys == 0) {
/* Return current PLL output */ /* Return current PLL output */
mfd = MCF_PLL_PFDR; mfd = readb(MCF_PLL_PFDR);
return (fref * mfd / (BUSDIV * 4)); return (fref * mfd / (BUSDIV * 4));
} }
...@@ -495,9 +501,10 @@ int clock_pll(int fsys, int flags) ...@@ -495,9 +501,10 @@ int clock_pll(int fsys, int flags)
* If it has then the SDRAM needs to be put into self refresh * If it has then the SDRAM needs to be put into self refresh
* mode before reprogramming the PLL. * mode before reprogramming the PLL.
*/ */
if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
/* Put SDRAM into self refresh mode */ /* Put SDRAM into self refresh mode */
MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE; writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
MCF_SDRAMC_SDCR);
/* /*
* Initialize the PLL to generate the new system clock frequency. * Initialize the PLL to generate the new system clock frequency.
...@@ -508,11 +515,10 @@ int clock_pll(int fsys, int flags) ...@@ -508,11 +515,10 @@ int clock_pll(int fsys, int flags)
clock_limp(DEFAULT_LPD); clock_limp(DEFAULT_LPD);
/* Reprogram PLL for desired fsys */ /* Reprogram PLL for desired fsys */
MCF_PLL_PODR = (0 writeb(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV),
| MCF_PLL_PODR_CPUDIV(BUSDIV/3) MCF_PLL_PODR);
| MCF_PLL_PODR_BUSDIV(BUSDIV));
MCF_PLL_PFDR = mfd; writeb(mfd, MCF_PLL_PFDR);
/* Exit LIMP mode */ /* Exit LIMP mode */
clock_exit_limp(); clock_exit_limp();
...@@ -520,12 +526,13 @@ int clock_pll(int fsys, int flags) ...@@ -520,12 +526,13 @@ int clock_pll(int fsys, int flags)
/* /*
* Return the SDRAM to normal operation if it is in use. * Return the SDRAM to normal operation if it is in use.
*/ */
if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF) if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
/* Exit self refresh mode */ /* Exit self refresh mode */
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE; writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
MCF_SDRAMC_SDCR);
/* Errata - workaround for SDRAM opeartion after exiting LIMP mode */ /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
MCF_SDRAMC_LIMP_FIX = MCF_SDRAMC_REFRESH; writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
/* wait for DQS logic to relock */ /* wait for DQS logic to relock */
for (i = 0; i < 0x200; i++) for (i = 0; i < 0x200; i++)
...@@ -546,14 +553,12 @@ int clock_limp(int div) ...@@ -546,14 +553,12 @@ int clock_limp(int div)
/* Save of the current value of the SSIDIV so we don't /* Save of the current value of the SSIDIV so we don't
overwrite the value*/ overwrite the value*/
temp = (MCF_CCM_CDR & MCF_CCM_CDR_SSIDIV(0xF)); temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);
/* Apply the divider to the system clock */ /* Apply the divider to the system clock */
MCF_CCM_CDR = ( 0 writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR);
| MCF_CCM_CDR_LPDIV(div)
| MCF_CCM_CDR_SSIDIV(temp));
MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP; writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
return (FREF/(3*(1 << div))); return (FREF/(3*(1 << div)));
} }
...@@ -563,10 +568,10 @@ int clock_exit_limp(void) ...@@ -563,10 +568,10 @@ int clock_exit_limp(void)
int fout; int fout;
/* Exit LIMP mode */ /* Exit LIMP mode */
MCF_CCM_MISCCR = (MCF_CCM_MISCCR & ~ MCF_CCM_MISCCR_LIMP); writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
/* Wait for PLL to lock */ /* Wait for PLL to lock */
while (!(MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK)) while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))
; ;
fout = get_sys_clock(); fout = get_sys_clock();
...@@ -579,10 +584,10 @@ int get_sys_clock(void) ...@@ -579,10 +584,10 @@ int get_sys_clock(void)
int divider; int divider;
/* Test to see if device is in LIMP mode */ /* Test to see if device is in LIMP mode */
if (MCF_CCM_MISCCR & MCF_CCM_MISCCR_LIMP) { if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {
divider = MCF_CCM_CDR & MCF_CCM_CDR_LPDIV(0xF); divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
return (FREF/(2 << divider)); return (FREF/(2 << divider));
} }
else else
return ((FREF * MCF_PLL_PFDR) / (BUSDIV * 4)); return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4);
} }
...@@ -30,14 +30,12 @@ ...@@ -30,14 +30,12 @@
static void __init m54xx_uarts_init(void) static void __init m54xx_uarts_init(void)
{ {
/* enable io pins */ /* enable io pins */
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
MCF_MBAR + MCF_PAR_PSC(0));
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS, __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
MCF_MBAR + MCF_PAR_PSC(1)); MCFGPIO_PAR_PSC1);
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS | __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
MCF_PAR_PSC_CTS_CTS, MCF_MBAR + MCF_PAR_PSC(2)); MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
MCF_MBAR + MCF_PAR_PSC(3));
} }
/***************************************************************************/ /***************************************************************************/
...@@ -46,10 +44,10 @@ static void mcf54xx_reset(void) ...@@ -46,10 +44,10 @@ static void mcf54xx_reset(void)
{ {
/* disable interrupts and enable the watchdog */ /* disable interrupts and enable the watchdog */
asm("movew #0x2700, %sr\n"); asm("movew #0x2700, %sr\n");
__raw_writel(0, MCF_MBAR + MCF_GPT_GMS0); __raw_writel(0, MCF_GPT_GMS0);
__raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0); __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
__raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4), __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
MCF_MBAR + MCF_GPT_GMS0); MCF_GPT_GMS0);
} }
/***************************************************************************/ /***************************************************************************/
......
...@@ -121,14 +121,14 @@ static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flasha ...@@ -121,14 +121,14 @@ static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flasha
static void __init nettel_smc91x_init(void) static void __init nettel_smc91x_init(void)
{ {
writew(0x00ec, MCF_MBAR + MCFSIM_PADDR); writew(0x00ec, MCFSIM_PADDR);
mcf_setppdata(0, 0x0080); mcf_setppdata(0, 0x0080);
writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT); writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR); writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR);
mcf_setppdata(0x0080, 0); mcf_setppdata(0x0080, 0);
/* Set correct chip select timing for SMC9196 accesses */ /* Set correct chip select timing for SMC9196 accesses */
writew(0x1180, MCF_MBAR + MCFSIM_CSCR3); writew(0x1180, MCFSIM_CSCR3);
/* Set the SMC interrupts to be auto-vectored */ /* Set the SMC interrupts to be auto-vectored */
mcf_autovector(NETTEL_SMC0_IRQ); mcf_autovector(NETTEL_SMC0_IRQ);
......
...@@ -272,8 +272,8 @@ static int __init mcf_pci_init(void) ...@@ -272,8 +272,8 @@ static int __init mcf_pci_init(void)
PACR_EXTMINTE(0x1f), PACR); PACR_EXTMINTE(0x1f), PACR);
/* Set required multi-function pins for PCI bus use */ /* Set required multi-function pins for PCI bus use */
__raw_writew(0x3ff, MCF_PAR_PCIBG); __raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
__raw_writew(0x3ff, MCF_PAR_PCIBR); __raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
/* Set up config space for local host bus controller */ /* Set up config space for local host bus controller */
__raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
......
...@@ -27,7 +27,7 @@ static void mcf_cpu_reset(void) ...@@ -27,7 +27,7 @@ static void mcf_cpu_reset(void)
{ {
local_irq_disable(); local_irq_disable();
/* Set watchdog to soft reset, and enabled */ /* Set watchdog to soft reset, and enabled */
__raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR); __raw_writeb(0xc0, MCFSIM_SYPCR);
for (;;) for (;;)
/* wait for watchdog to timeout */; /* wait for watchdog to timeout */;
} }
......
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
/* /*
* By default use Slice Timer 1 as the profiler clock timer. * By default use Slice Timer 1 as the profiler clock timer.
*/ */
#define PA(a) (MCF_MBAR + MCFSLT_TIMER1 + (a)) #define PA(a) (MCFSLT_TIMER1 + (a))
/* /*
* Choose a reasonably fast profile timer. Make it an odd value to * Choose a reasonably fast profile timer. Make it an odd value to
...@@ -76,7 +76,7 @@ void mcfslt_profile_init(void) ...@@ -76,7 +76,7 @@ void mcfslt_profile_init(void)
/* /*
* By default use Slice Timer 0 as the system clock timer. * By default use Slice Timer 0 as the system clock timer.
*/ */
#define TA(a) (MCF_MBAR + MCFSLT_TIMER0 + (a)) #define TA(a) (MCFSLT_TIMER0 + (a))
static u32 mcfslt_cycles_per_jiffy; static u32 mcfslt_cycles_per_jiffy;
static u32 mcfslt_cnt; static u32 mcfslt_cnt;
......
...@@ -56,13 +56,13 @@ static void init_timer_irq(void) ...@@ -56,13 +56,13 @@ static void init_timer_irq(void)
#ifdef MCFSIM_ICR_AUTOVEC #ifdef MCFSIM_ICR_AUTOVEC
/* Timer1 is always used as system timer */ /* Timer1 is always used as system timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3, writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER1ICR); MCFSIM_TIMER1ICR);
mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1); mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
#ifdef CONFIG_HIGHPROFILE #ifdef CONFIG_HIGHPROFILE
/* Timer2 is to be used as a high speed profile timer */ /* Timer2 is to be used as a high speed profile timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3, writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER2ICR); MCFSIM_TIMER2ICR);
mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2); mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
#endif #endif
#endif /* MCFSIM_ICR_AUTOVEC */ #endif /* MCFSIM_ICR_AUTOVEC */
......
...@@ -46,17 +46,17 @@ static void wdt_enable(void) ...@@ -46,17 +46,17 @@ static void wdt_enable(void)
unsigned int gms0; unsigned int gms0;
/* preserve GPIO usage, if any */ /* preserve GPIO usage, if any */
gms0 = __raw_readl(MCF_MBAR + MCF_GPT_GMS0); gms0 = __raw_readl(MCF_GPT_GMS0);
if (gms0 & MCF_GPT_GMS_TMS_GPIO) if (gms0 & MCF_GPT_GMS_TMS_GPIO)
gms0 &= (MCF_GPT_GMS_TMS_GPIO | MCF_GPT_GMS_GPIO_MASK gms0 &= (MCF_GPT_GMS_TMS_GPIO | MCF_GPT_GMS_GPIO_MASK
| MCF_GPT_GMS_OD); | MCF_GPT_GMS_OD);
else else
gms0 = MCF_GPT_GMS_TMS_GPIO | MCF_GPT_GMS_OD; gms0 = MCF_GPT_GMS_TMS_GPIO | MCF_GPT_GMS_OD;
__raw_writel(gms0, MCF_MBAR + MCF_GPT_GMS0); __raw_writel(gms0, MCF_GPT_GMS0);
__raw_writel(MCF_GPT_GCIR_PRE(heartbeat*(MCF_BUSCLK/0xffff)) | __raw_writel(MCF_GPT_GCIR_PRE(heartbeat*(MCF_BUSCLK/0xffff)) |
MCF_GPT_GCIR_CNT(0xffff), MCF_MBAR + MCF_GPT_GCIR0); MCF_GPT_GCIR_CNT(0xffff), MCF_GPT_GCIR0);
gms0 |= MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE; gms0 |= MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE;
__raw_writel(gms0, MCF_MBAR + MCF_GPT_GMS0); __raw_writel(gms0, MCF_GPT_GMS0);
} }
static void wdt_disable(void) static void wdt_disable(void)
...@@ -64,18 +64,18 @@ static void wdt_disable(void) ...@@ -64,18 +64,18 @@ static void wdt_disable(void)
unsigned int gms0; unsigned int gms0;
/* disable watchdog */ /* disable watchdog */
gms0 = __raw_readl(MCF_MBAR + MCF_GPT_GMS0); gms0 = __raw_readl(MCF_GPT_GMS0);
gms0 &= ~(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE); gms0 &= ~(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE);
__raw_writel(gms0, MCF_MBAR + MCF_GPT_GMS0); __raw_writel(gms0, MCF_GPT_GMS0);
} }
static void wdt_keepalive(void) static void wdt_keepalive(void)
{ {
unsigned int gms0; unsigned int gms0;
gms0 = __raw_readl(MCF_MBAR + MCF_GPT_GMS0); gms0 = __raw_readl(MCF_GPT_GMS0);
gms0 |= MCF_GPT_GMS_OCPW(0xA5); gms0 |= MCF_GPT_GMS_OCPW(0xA5);
__raw_writel(gms0, MCF_MBAR + MCF_GPT_GMS0); __raw_writel(gms0, MCF_GPT_GMS0);
} }
static int m54xx_wdt_open(struct inode *inode, struct file *file) static int m54xx_wdt_open(struct inode *inode, struct file *file)
...@@ -195,8 +195,7 @@ static struct miscdevice m54xx_wdt_miscdev = { ...@@ -195,8 +195,7 @@ static struct miscdevice m54xx_wdt_miscdev = {
static int __init m54xx_wdt_init(void) static int __init m54xx_wdt_init(void)
{ {
if (!request_mem_region(MCF_MBAR + MCF_GPT_GCIR0, 4, if (!request_mem_region(MCF_GPT_GCIR0, 4, "Coldfire M54xx Watchdog")) {
"Coldfire M54xx Watchdog")) {
pr_warn("I/O region busy\n"); pr_warn("I/O region busy\n");
return -EBUSY; return -EBUSY;
} }
...@@ -208,7 +207,7 @@ static int __init m54xx_wdt_init(void) ...@@ -208,7 +207,7 @@ static int __init m54xx_wdt_init(void)
static void __exit m54xx_wdt_exit(void) static void __exit m54xx_wdt_exit(void)
{ {
misc_deregister(&m54xx_wdt_miscdev); misc_deregister(&m54xx_wdt_miscdev);
release_mem_region(MCF_MBAR + MCF_GPT_GCIR0, 4); release_mem_region(MCF_GPT_GCIR0, 4);
} }
module_init(m54xx_wdt_init); module_init(m54xx_wdt_init);
......
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