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Commit 7cc1c4b2 authored by Mike Frysinger's avatar Mike Frysinger Committed by Bryan Wu
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[Blackfin] arch: update to latest anomaly sheets 

Signed-off-by: default avatarMike Frysinger <michael.frysinger@analog.com>
Signed-off-by: default avatarBryan Wu <bryan.wu@analog.com>
parent 79f1ec86
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Showing with 67 additions and 31 deletions
include/asm-blackfin/mach-bf533/anomaly.h
View file @ 7cc1c4b2
...@@ -7,9 +7,7 @@ ...@@ -7,9 +7,7 @@
*/ */
/* This file shoule be up to date with: /* This file shoule be up to date with:
* - Revision X, March 23, 2007; ADSP-BF533 Blackfin Processor Anomaly List * - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
* - Revision AB, March 23, 2007; ADSP-BF532 Blackfin Processor Anomaly List
* - Revision W, March 23, 2007; ADSP-BF531 Blackfin Processor Anomaly List
*/ */
#ifndef _MACH_ANOMALY_H_ #ifndef _MACH_ANOMALY_H_
...@@ -17,7 +15,7 @@ ...@@ -17,7 +15,7 @@
/* We do not support 0.1 or 0.2 silicon - sorry */ /* We do not support 0.1 or 0.2 silicon - sorry */
#if __SILICON_REVISION__ < 3 #if __SILICON_REVISION__ < 3
# error Kernel will not work on BF533 silicon version 0.0, 0.1, or 0.2 # error will not work on BF533 silicon version 0.0, 0.1, or 0.2
#endif #endif
#if defined(__ADSPBF531__) #if defined(__ADSPBF531__)
...@@ -251,6 +249,12 @@ ...@@ -251,6 +249,12 @@
#define ANOMALY_05000192 (__SILICON_REVISION__ < 3) #define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
/* Internal Voltage Regulator may not start up */ /* Internal Voltage Regulator may not start up */
#define ANOMALY_05000206 (__SILICON_REVISION__ < 3) #define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000266 (0) #define ANOMALY_05000266 (0)
......
include/asm-blackfin/mach-bf537/anomaly.h
View file @ 7cc1c4b2
...@@ -7,9 +7,7 @@ ...@@ -7,9 +7,7 @@
*/ */
/* This file shoule be up to date with: /* This file shoule be up to date with:
* - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List * - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
* - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List
* - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List
*/ */
#ifndef _MACH_ANOMALY_H_ #ifndef _MACH_ANOMALY_H_
...@@ -17,7 +15,7 @@ ...@@ -17,7 +15,7 @@
/* We do not support 0.1 silicon - sorry */ /* We do not support 0.1 silicon - sorry */
#if __SILICON_REVISION__ < 2 #if __SILICON_REVISION__ < 2
# error Kernel will not work on BF537 silicon version 0.0 or 0.1 # error will not work on BF537 silicon version 0.0 or 0.1
#endif #endif
#if defined(__ADSPBF534__) #if defined(__ADSPBF534__)
...@@ -44,6 +42,8 @@ ...@@ -44,6 +42,8 @@
#define ANOMALY_05000122 (1) #define ANOMALY_05000122 (1)
/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ /* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) #define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
#define ANOMALY_05000167 (1)
/* PPI_DELAY not functional in PPI modes with 0 frame syncs */ /* PPI_DELAY not functional in PPI modes with 0 frame syncs */
#define ANOMALY_05000180 (1) #define ANOMALY_05000180 (1)
/* Instruction Cache Is Not Functional */ /* Instruction Cache Is Not Functional */
...@@ -130,6 +130,12 @@ ...@@ -130,6 +130,12 @@
#define ANOMALY_05000321 (__SILICON_REVISION__ < 3) #define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */ /* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
#define ANOMALY_05000322 (1) #define ANOMALY_05000322 (1)
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
#define ANOMALY_05000359 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0) #define ANOMALY_05000125 (0)
......
include/asm-blackfin/mach-bf548/anomaly.h
View file @ 7cc1c4b2
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
*/ */
/* This file shoule be up to date with: /* This file shoule be up to date with:
* - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List * - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/ */
#ifndef _MACH_ANOMALY_H_ #ifndef _MACH_ANOMALY_H_
...@@ -26,47 +26,59 @@ ...@@ -26,47 +26,59 @@
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1) #define ANOMALY_05000272 (1)
/* False Hardware Error Exception when ISR context is not restored */ /* False Hardware Error Exception when ISR context is not restored */
#define ANOMALY_05000281 (1) #define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
#define ANOMALY_05000304 (1) #define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1) #define ANOMALY_05000310 (1)
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1) #define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
/* TWI Slave Boot Mode Is Not Functional */ /* TWI Slave Boot Mode Is Not Functional */
#define ANOMALY_05000324 (1) #define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
/* External FIFO Boot Mode Is Not Functional */ /* External FIFO Boot Mode Is Not Functional */
#define ANOMALY_05000325 (1) #define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
#define ANOMALY_05000327 (1) #define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
/* Incorrect Access of OTP_STATUS During otp_write() Function */ /* Incorrect Access of OTP_STATUS During otp_write() Function */
#define ANOMALY_05000328 (1) #define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
/* Synchronous Burst Flash Boot Mode Is Not Functional */ /* Synchronous Burst Flash Boot Mode Is Not Functional */
#define ANOMALY_05000329 (1) #define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
/* Host DMA Boot Mode Is Not Functional */ /* Host DMA Boot Mode Is Not Functional */
#define ANOMALY_05000330 (1) #define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
#define ANOMALY_05000334 (1) #define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
/* Inadequate Rotary Debounce Logic Duration */ /* Inadequate Rotary Debounce Logic Duration */
#define ANOMALY_05000335 (1) #define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
#define ANOMALY_05000336 (1) #define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
#define ANOMALY_05000337 (1) #define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
#define ANOMALY_05000338 (1) #define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
#define ANOMALY_05000340 (1) #define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
#define ANOMALY_05000344 (1) #define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
/* USB Calibration Value Is Not Intialized */ /* USB Calibration Value Is Not Intialized */
#define ANOMALY_05000346 (1) #define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ /* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
#define ANOMALY_05000347 (1) #define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
/* Data Lost when Core Reads SDH Data FIFO */ /* Data Lost when Core Reads SDH Data FIFO */
#define ANOMALY_05000349 (1) #define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
/* PLL Status Register Is Inaccurate */ /* PLL Status Register Is Inaccurate */
#define ANOMALY_05000351 (1) #define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* External Memory Read Access Hangs Core With PLL Bypass */
#define ANOMALY_05000360 (1)
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
#define ANOMALY_05000365 (1)
/* Addressing Conflict between Boot ROM and Asynchronous Memory */
#define ANOMALY_05000369 (1)
/* Mobile DDR Operation Not Functional */
#define ANOMALY_05000377 (1)
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
#define ANOMALY_05000378 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0) #define ANOMALY_05000125 (0)
......
include/asm-blackfin/mach-bf561/anomaly.h
View file @ 7cc1c4b2
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
*/ */
/* This file shoule be up to date with: /* This file shoule be up to date with:
* - Revision N, March 28, 2007; ADSP-BF561 Silicon Anomaly List * - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
*/ */
#ifndef _MACH_ANOMALY_H_ #ifndef _MACH_ANOMALY_H_
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */ /* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4 #if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
# error Kernel will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4 # error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
#endif #endif
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
...@@ -208,6 +208,8 @@ ...@@ -208,6 +208,8 @@
#define ANOMALY_05000275 (__SILICON_REVISION__ > 2) #define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
#define ANOMALY_05000276 (__SILICON_REVISION__ < 5) #define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 5) #define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
/* False Hardware Error Exception When ISR Context Is Not Restored */ /* False Hardware Error Exception When ISR Context Is Not Restored */
...@@ -246,6 +248,18 @@ ...@@ -246,6 +248,18 @@
#define ANOMALY_05000332 (__SILICON_REVISION__ < 5) #define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */ /* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
#define ANOMALY_05000333 (__SILICON_REVISION__ < 5) #define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* Conflicting Column Address Widths Causes SDRAM Errors */
#define ANOMALY_05000362 (1)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
/* Anomalies that don't exist on this proc */ /* Anomalies that don't exist on this proc */
#define ANOMALY_05000158 (0) #define ANOMALY_05000158 (0)
......
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