Commit 7d058bc4 authored by Beomho Seo's avatar Beomho Seo Committed by Sylwester Nawrocki

clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD UART

This patch adds CLK_IGNORE_UNUSED flag for sclk_aud_uart gate
clock for uart3 operation.
Signed-off-by: default avatarBeomho Seo <beomho.seo@samsung.com>
Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
[s.nawrocki@samsung.com: edited the patch's summary]
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 21a5560b
...@@ -2978,7 +2978,7 @@ static const struct samsung_gate_clock aud_gate_clks[] __initconst = { ...@@ -2978,7 +2978,7 @@ static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus", GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
ENABLE_SCLK_AUD1, 4, 0, 0), ENABLE_SCLK_AUD1, 4, 0, 0),
GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart", GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
ENABLE_SCLK_AUD1, 3, 0, 0), ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm", GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
ENABLE_SCLK_AUD1, 2, 0, 0), ENABLE_SCLK_AUD1, 2, 0, 0),
GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk", GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
......
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