[PATCH] sn: Remove the bridge and xbridge code - everything not PIC

From: Pat Gefre <pfg@sgi.com>

Remove the bridge and xbridge code - everything not PIC

arch/ia64/sn/io/machvec/pci_bus_cvlink.c

@@ -54,18 +54,6 @@ extern void register_pcibr_intr(int irq, pcibr_intr_t intr);
 void sn_dma_flush_init(unsigned long start, unsigned long end, int idx, int pin, int slot);
 
 
-/*
- * For the given device, initialize whether it is a PIC device.
- */
-static void
-set_isPIC(struct sn_device_sysdata *device_sysdata)
-{
-	pciio_info_t pciio_info = pciio_info_get(device_sysdata->vhdl);
-	pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-
-	device_sysdata->isPIC = IS_PIC_SOFT(pcibr_soft);;
-}
-
 /*
  * pci_bus_cvlink_init() - To be called once during initialization before 
  *	SGI IO Infrastructure init is called.
@@ -188,23 +176,11 @@ set_flush_addresses(struct pci_dev *device_dev,
 	 * Get the nasid from the bridge.
 	 */
 	nasid = NASID_GET(device_sysdata->dma_buf_sync);
-	if (IS_PIC_DEVICE(device_dev)) {
 	device_sysdata->dma_buf_sync = (volatile unsigned int *)
 		&bridge->b_wr_req_buf[pciio_slot].reg;
 	device_sysdata->xbow_buf_sync = (volatile unsigned int *)
 		XBOW_PRIO_LINKREGS_PTR(NODE_SWIN_BASE(nasid, 0),
 		pcibr_soft->bs_xid);
-	} else {
-		/*
-		 * Accessing Xbridge and Xbow register when SHUB swapoper is on!.
-		 */
-		device_sysdata->dma_buf_sync = (volatile unsigned int *)
-			((uint64_t)&(bridge->b_wr_req_buf[pciio_slot].reg)^4);
-		device_sysdata->xbow_buf_sync = (volatile unsigned int *)
-			((uint64_t)(XBOW_PRIO_LINKREGS_PTR(
-			NODE_SWIN_BASE(nasid, 0), pcibr_soft->bs_xid)) ^ 4);
-	}
-
 #ifdef DEBUG
 	printk("set_flush_addresses: dma_buf_sync %p xbow_buf_sync %p\n", 
 		device_sysdata->dma_buf_sync, device_sysdata->xbow_buf_sync);
@@ -501,7 +477,6 @@ sn_pci_fixup(int arg)
 		device_vertex = device_sysdata->vhdl;
 
 		device_dev->sysdata = (void *) device_sysdata;
-		set_isPIC(device_sysdata);
 
 		/*
 		 * Set the xbridge Device(X) Write Buffer Flush and Xbow Flush 
@@ -521,7 +496,7 @@ sn_pci_fixup(int arg)
 			size = device_dev->resource[idx].end -
 				device_dev->resource[idx].start;
 			if (size) {
-				device_dev->resource[idx].start = (unsigned long)pciio_pio_addr(device_vertex, 0, PCIIO_SPACE_WIN(idx), 0, size, 0, (IS_PIC_DEVICE(device_dev)) ? 0 : PCIIO_BYTE_STREAM);
+				device_dev->resource[idx].start = (unsigned long)pciio_pio_addr(device_vertex, 0, PCIIO_SPACE_WIN(idx), 0, size, 0, 0);
 				device_dev->resource[idx].start |= __IA64_UNCACHED_OFFSET;
 			}
 			else
@@ -824,10 +799,8 @@ pci_bus_to_hcl_cvlink(void)
 				
 	devfs_hdl = hwgraph_path_to_vertex("hw/module");
 	for (i = 0; i < nummodules ; i++) {
-	    for ( j = 0; j < 3; j++ ) {
+	    for ( j = 0; j < 2; j++ ) {
 		if ( j == 0 )
-			brick_name = EDGE_LBL_PBRICK;
-		else if ( j == 1 )
 			brick_name = EDGE_LBL_PXBRICK;
 		else
 			brick_name = EDGE_LBL_IXBRICK;

arch/ia64/sn/io/machvec/pci_dma.c

@@ -175,7 +175,6 @@ sn_pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_hand
 	 * attributes or to a different memory region.
 	 */
 	*dma_handle = pcibr_dmatrans_addr(vhdl, NULL, phys_addr, size,
-			((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
 							PCIIO_DMA_CMD);
 
         /*
@@ -193,9 +192,7 @@ sn_pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_hand
 	 * so we try to use an ATE.
 	 */
 	if (!(*dma_handle)) {
-		dma_map = pcibr_dmamap_alloc(vhdl, NULL, size,
-				((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
-					     PCIIO_DMA_CMD);
+		dma_map = pcibr_dmamap_alloc(vhdl, NULL, size, PCIIO_DMA_CMD);
 		if (!dma_map) {
 			printk(KERN_ERR "sn_pci_alloc_consistent: Unable to "
 			       "allocate anymore 32 bit page map entries.\n");
@@ -286,9 +283,7 @@ sn_pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int dire
 		if (IS_PCIA64(hwdev)) {
 			sg->dma_address = pcibr_dmatrans_addr(vhdl, NULL, phys_addr,
 						       sg->length,
-			       ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
-						       PCIIO_DMA_DATA |
-						       PCIIO_DMA_A64);
+						       PCIIO_DMA_DATA | PCIIO_DMA_A64);
 			sg->dma_length = sg->length;
 			continue;
 		}
@@ -298,9 +293,7 @@ sn_pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int dire
 		 */
 		if (IS_PCI32G(hwdev)) {
 			sg->dma_address = pcibr_dmatrans_addr(vhdl, NULL, phys_addr,
-						       sg->length,
-					((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
-						       PCIIO_DMA_DATA);
+						       sg->length, PCIIO_DMA_DATA);
 			sg->dma_length = sg->length;
 			/*
 			 * See if we got a direct map entry
@@ -315,9 +308,7 @@ sn_pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int dire
 		 * It is a 32 bit card and we cannot do direct mapping,
 		 * so we use an ATE.
 		 */
-		dma_map = pcibr_dmamap_alloc(vhdl, NULL, sg->length,
-				((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
-					     PCIIO_DMA_DATA);
+		dma_map = pcibr_dmamap_alloc(vhdl, NULL, sg->length, PCIIO_DMA_DATA);
 		if (!dma_map) {
 			printk(KERN_ERR "sn_pci_map_sg: Unable to allocate "
 			       "anymore 32 bit page map entries.\n");
@@ -427,9 +418,7 @@ sn_pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction)
 	if (IS_PCIA64(hwdev)) {
 		/* This device supports 64 bit DMA addresses. */
 		dma_addr = pcibr_dmatrans_addr(vhdl, NULL, phys_addr, size,
-		       ((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
-					       PCIIO_DMA_DATA |
-					       PCIIO_DMA_A64);
+					       PCIIO_DMA_DATA | PCIIO_DMA_A64);
 		return dma_addr;
 	}
 
@@ -441,7 +430,6 @@ sn_pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction)
 	 */
 	if (IS_PCI32G(hwdev)) {
 		dma_addr = pcibr_dmatrans_addr(vhdl, NULL, phys_addr, size,
-			((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
 					       PCIIO_DMA_DATA);
 		if (dma_addr)
 			return dma_addr;
@@ -452,9 +440,7 @@ sn_pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction)
 	 * let's use the PMU instead.
 	 */
 	dma_map = NULL;
-	dma_map = pcibr_dmamap_alloc(vhdl, NULL, size, 
-			((IS_PIC_DEVICE(hwdev)) ? 0 : PCIIO_BYTE_STREAM) |
-			PCIIO_DMA_DATA);
+	dma_map = pcibr_dmamap_alloc(vhdl, NULL, size, PCIIO_DMA_DATA);
 
 	if (!dma_map) {
 		printk(KERN_ERR "pci_map_single: Unable to allocate anymore "

arch/ia64/sn/io/sgi_io_sim.c

@@ -31,11 +31,8 @@ is_specified(char *s)
 /*
  * Routines provided by ml/SN/promif.c.
  */
-static __psunsigned_t master_bridge_base;
 nasid_t console_nasid = (nasid_t)-1;
 char master_baseio_wid;
-static char console_wid;
-static char console_pcislot;
 
 int
 check_nasid_equiv(nasid_t nasida, nasid_t nasidb)

arch/ia64/sn/io/sn2/klconflib.c

@@ -268,14 +268,6 @@ board_to_path(lboard_t *brd, char *path)
 				board_name = EDGE_LBL_PXBRICK;
 			else if (brd->brd_type == KLTYPE_IXBRICK)
 				board_name = EDGE_LBL_IXBRICK;
-			else if (brd->brd_type == KLTYPE_PBRICK)
-				board_name = EDGE_LBL_PBRICK;
-			else if (brd->brd_type == KLTYPE_IBRICK)
-				board_name = EDGE_LBL_IBRICK;
-			else if (brd->brd_type == KLTYPE_XBRICK)
-				board_name = EDGE_LBL_XBRICK;
-			else if (brd->brd_type == KLTYPE_PEBRICK)
-				board_name = EDGE_LBL_PEBRICK;
 			else if (brd->brd_type == KLTYPE_CGBRICK)
 				board_name = EDGE_LBL_CGBRICK;
 			else
@@ -438,51 +430,6 @@ board_serial_number_get(lboard_t *board,char *serial_number)
 		break;
 	}
 	case KLCLASS_IO: {	/* IO board */
-		if (KLTYPE(board->brd_type) == KLTYPE_TPU) {
-		/* Special case for TPU boards */
-			kltpu_t *tpu;	
-		
-			/* Get the tpu component information */
-			tpu = (kltpu_t *)find_first_component(board,
-						      KLSTRUCT_TPU);
-			/* If we don't have a tpu component on a tpu board
-			 * then we have a weird klconfig.
-			 */
-			if (!tpu)
-				return(1);
-			/* Get the serial number information from
-			 * the tpu's manufacturing nic info
-			 */
-			if (component_serial_number_get(board,
-						tpu->tpu_mfg_nic,
-						serial_number,
-						""))
-				return(1);
-			break;
-		} else  if ((KLTYPE(board->brd_type) == KLTYPE_GSN_A) ||
-		            (KLTYPE(board->brd_type) == KLTYPE_GSN_B)) {
-		/* Special case for GSN boards */
-			klgsn_t *gsn;	
-		
-			/* Get the gsn component information */
-			gsn = (klgsn_t *)find_first_component(board,
-			      ((KLTYPE(board->brd_type) == KLTYPE_GSN_A) ?
-					KLSTRUCT_GSN_A : KLSTRUCT_GSN_B));
-			/* If we don't have a gsn component on a gsn board
-			 * then we have a weird klconfig.
-			 */
-			if (!gsn)
-				return(1);
-			/* Get the serial number information from
-			 * the gsn's manufacturing nic info
-			 */
-			if (component_serial_number_get(board,
-						gsn->gsn_mfg_nic,
-						serial_number,
-						""))
-				return(1);
-			break;
-		} else {
 	     	klbri_t	*bridge;
 		
 		/* Get the bridge component information */
@@ -498,12 +445,10 @@ board_serial_number_get(lboard_t *board,char *serial_number)
 		 */
 		if (component_serial_number_get(board,
 					bridge->bri_mfg_nic,
-						serial_number,
-						""))
+					serial_number, ""))
 			return(1);
 		break;
 	}
-	}
 	case KLCLASS_ROUTER: {	/* Router board */
 		klrou_t *router;	
 		

arch/ia64/sn/io/sn2/l1_command.c

@@ -111,12 +111,6 @@ int iobrick_module_get(nasid_t nasid)
 	brick_type = MODULE_IXBRICK; break;
       case L1_BRICKTYPE_PX: 
 	brick_type = MODULE_PXBRICK; break;
-      case L1_BRICKTYPE_I: 
-	brick_type = MODULE_IBRICK; break;
-      case L1_BRICKTYPE_P:
-	brick_type = MODULE_PBRICK; break;
-      case L1_BRICKTYPE_X:
-	brick_type = MODULE_XBRICK; break;
     }
 
     ret = RBT_TO_MODULE(rack, bay, brick_type);
@@ -176,15 +170,6 @@ iobrick_L1bricktype_to_name(int type)
     default:
         return("Unknown");
 
-    case L1_BRICKTYPE_X:
-        return("Xbrick");
-
-    case L1_BRICKTYPE_I:
-        return("Ibrick");
-
-    case L1_BRICKTYPE_P:
-        return("Pbrick");
-
     case L1_BRICKTYPE_PX:
         return("PXbrick");
 
@@ -196,6 +181,9 @@ iobrick_L1bricktype_to_name(int type)
 
     case L1_BRICKTYPE_R:
         return("Rbrick");
+
+    case L1_BRICKTYPE_CHI_CG:
+        return(EDGE_LBL_CGBRICK);
     }
 }
 

arch/ia64/sn/io/sn2/ml_iograph.c

@@ -394,11 +394,8 @@ io_xswitch_widget_init(vertex_hdl_t  	xswitchv,
 		sprintf(pathname, EDGE_LBL_MODULE "/%s/" EDGE_LBL_SLAB "/%d" "/%s" "/%s/%d",
 			buffer,
 			geo_slab(board->brd_geoid),
-			(board->brd_type == KLTYPE_IBRICK) ? EDGE_LBL_IBRICK :
-			(board->brd_type == KLTYPE_PBRICK) ? EDGE_LBL_PBRICK :
 			(board->brd_type == KLTYPE_PXBRICK) ? EDGE_LBL_PXBRICK :
-			(board->brd_type == KLTYPE_IXBRICK) ? EDGE_LBL_IXBRICK :
-			(board->brd_type == KLTYPE_XBRICK) ? EDGE_LBL_XBRICK : "?brick",
+			(board->brd_type == KLTYPE_IXBRICK) ? EDGE_LBL_IXBRICK : "?brick",
 			EDGE_LBL_XTALK, widgetnum);
 		
 		DBG("io_xswitch_widget_init: path= %s\n", pathname);
@@ -587,7 +584,6 @@ io_init_node(cnodeid_t cnodeid)
 	nodepda_t	*npdap;
 	struct semaphore *peer_sema = 0;
 	uint32_t	widget_partnum;
-	cpu_cookie_t	c = 0;
 
 	npdap = NODEPDA(cnodeid);
 
@@ -808,34 +804,6 @@ init_all_devices(void)
 static
 struct io_brick_map_s io_brick_tab[] = {
 
-/* Ibrick widget number to PCI bus number map */
- {      MODULE_IBRICK,                          /* Ibrick type    */ 
-    /*  PCI Bus #                                  Widget #       */
-    {   0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7      */
-        0,                                      /* 0x8            */
-        0,                                      /* 0x9            */
-        0, 0,                                   /* 0xa - 0xb      */
-        0,                                      /* 0xc            */
-        0,                                      /* 0xd            */
-        2,                                      /* 0xe            */
-        1                                       /* 0xf            */
-     }
- },
-
-/* Pbrick widget number to PCI bus number map */
- {      MODULE_PBRICK,                          /* Pbrick type    */ 
-    /*  PCI Bus #                                  Widget #       */
-    {   0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7      */
-        2,                                      /* 0x8            */
-        1,                                      /* 0x9            */
-        0, 0,                                   /* 0xa - 0xb      */
-        4,                                      /* 0xc            */
-        6,                                      /* 0xd            */
-        3,                                      /* 0xe            */
-        5                                       /* 0xf            */
-    }
- },
-
 /* PXbrick widget number to PCI bus number map */
  {      MODULE_PXBRICK,                         /* PXbrick type   */ 
     /*  PCI Bus #                                  Widget #       */
@@ -863,20 +831,6 @@ struct io_brick_map_s io_brick_tab[] = {
         3                                       /* 0xf            */
     }
  },
-
-/* Xbrick widget to XIO slot map */
- {      MODULE_XBRICK,                          /* Xbrick type    */ 
-    /*  XIO Slot #                                 Widget #       */
-    {   0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7      */
-        1,                                      /* 0x8            */
-        3,                                      /* 0x9            */
-        0, 0,                                   /* 0xa - 0xb      */
-        2,                                      /* 0xc            */
-        4,                                      /* 0xd            */
-        0,                                      /* 0xe            */
-        0                                       /* 0xf            */
-    }
- }
 };
 
 /*

arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c

@@ -380,26 +380,10 @@ ate_write(pcibr_soft_t pcibr_soft,
 	  int ate_count,
 	  bridge_ate_t ate)
 {
-	if (IS_PIC_SOFT(pcibr_soft) ) {
   	while (ate_count-- > 0) {
 		*ate_ptr++ = ate;
 		ate += IOPGSIZE;
 	}
-	}
-	else {
-		if (io_get_sh_swapper(NASID_GET(ate_ptr))) {
-    			while (ate_count-- > 0) {
-				*ate_ptr++ = __swab64(ate);
-				ate += IOPGSIZE;
-			}
-		}
-		else {
-    			while (ate_count-- > 0) {
-				*ate_ptr++ = ate;
-				ate += IOPGSIZE;
-			}
-		}
-	}
 }
 
 #if PCIBR_FREEZE_TIME
@@ -440,21 +424,9 @@ ate_thaw(pcibr_dmamap_t pcibr_dmamap,
     for (slot = pcibr_soft->bs_min_slot; 
 		slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) {
 	if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER) {
-		if ( IS_PIC_SOFT(pcibr_soft) ) {
-			pcibr_slot_config_set(bridge, slot, PCI_CFG_COMMAND/4, cmd_reg);
-		}
-		else {
-			if (io_get_sh_swapper(NASID_GET(bridge))) {
-				bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = __swab32(cmd_reg);
-			}
-			else {
-//				BUG(); /* Does this really work if called when io_get_sh_swapper = 0? */
-//				bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg;
 		pcibr_slot_config_set(bridge, slot, PCI_CFG_COMMAND/4, cmd_reg);
 	}
     }
-	}
-    }
     pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_BUSY;
     atomic_inc(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
 

arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c

@@ -281,11 +281,9 @@ pcibr_force_interrupt(pcibr_intr_t intr)
 			PCIBR_DEBUG((PCIBR_DEBUG_INTR, pcibr_soft->bs_vhdl,
 		    		"pcibr_force_interrupt: bit=0x%x\n", bit));
 
-			if (IS_XBRIDGE_OR_PIC_SOFT(pcibr_soft)) {
     			bridge->b_force_pin[bit].intr = 1;
 		}
 	}
-	}
 }
 
 /*ARGSUSED */
@@ -651,10 +649,7 @@ pcibr_intr_connect(pcibr_intr_t pcibr_intr, intr_func_t intr_func, intr_arg_t in
 	     * Use the pcibr wrapper function to handle all Bridge interrupts
 	     * regardless of whether the interrupt line is shared or not.
 	     */
-	    if (IS_PIC_SOFT(pcibr_soft)) 
 	    int_addr = (void *)&(bridge->p_int_addr_64[pcibr_int_bit]);
-	    else
-		int_addr = (void *)&(bridge->b_int_addr[pcibr_int_bit].addr);
 
 	    xtalk_intr_connect(xtalk_intr, pcibr_intr_func, (intr_arg_t) intr_wrap,
 					(xtalk_intr_setfunc_t) pcibr_setpciint,
@@ -673,8 +668,7 @@ pcibr_intr_connect(pcibr_intr_t pcibr_intr, intr_func_t intr_func, intr_arg_t in
 	 * On PIC we must write 64-bit MMRs with 64-bit stores
 	 */
 	s = pcibr_lock(pcibr_soft);
-	if (IS_PIC_SOFT(pcibr_soft) &&
-			PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) {
+	if (PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) {
 	    int_enable = bridge->p_int_enable_64;
 	    int_enable |= pcibr_int_bits;
 	    bridge->p_int_enable_64 = int_enable;
@@ -728,7 +722,7 @@ pcibr_intr_disconnect(pcibr_intr_t pcibr_intr)
      * On PIC we must write 64-bit MMRs with 64-bit stores
      */
     s = pcibr_lock(pcibr_soft);
-    if (IS_PIC_SOFT(pcibr_soft) && PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) {
+    if (PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) {
 	int_enable = bridge->p_int_enable_64;
 	int_enable &= ~pcibr_int_bits;
 	bridge->p_int_enable_64 = int_enable;
@@ -773,10 +767,7 @@ pcibr_intr_disconnect(pcibr_intr_t pcibr_intr)
             if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
                 continue;
 
-            if (IS_PIC_SOFT(pcibr_soft))
             int_addr = (void *)&(bridge->p_int_addr_64[pcibr_int_bit]);
-            else
-                int_addr = (void *)&(bridge->b_int_addr[pcibr_int_bit].addr);
 
 	    xtalk_intr_connect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr,
 				pcibr_intr_func, (intr_arg_t) intr_wrap,
@@ -948,8 +939,7 @@ pcibr_intr_func(intr_arg_t arg)
 	 * interrupt problem.   Briefly disable the enable bit for
 	 * this device.
 	 */
-	if (IS_PIC_SOFT(pcibr_soft) &&
-			PCIBR_WAR_ENABLED(PV855272, pcibr_soft)) {
+	if (PCIBR_WAR_ENABLED(PV855272, pcibr_soft)) {
 		unsigned s;
 
 		/* disable-enable interrupts for this bridge pin */
@@ -1059,8 +1049,7 @@ pcibr_intr_func(intr_arg_t arg)
 	     * On PIC we must write 64-bit MMRs with 64-bit stores
 	     */
 	    s = pcibr_lock(pcibr_soft);
-	    if (IS_PIC_SOFT(pcibr_soft) &&
-				PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) {
+	    if (PCIBR_WAR_ENABLED(PV854697, pcibr_soft)) {
 		int_enable = bridge->p_int_enable_64;
 		int_enable &= ~mask;
 		bridge->p_int_enable_64 = int_enable;

arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c

@@ -401,18 +401,8 @@ pcibr_wrb_flush(vertex_hdl_t pconn_vhdl)
     volatile bridgereg_t   *wrb_flush;
 
     wrb_flush = &(bridge->b_wr_req_buf[pciio_slot].reg);
-    if ( IS_PIC_SOFT(pcibr_soft) ) {
     while (*wrb_flush)
 	;
-    }
-    else {
-	if (io_get_sh_swapper(NASID_GET(bridge))) {
-		while (BRIDGE_REG_GET32((wrb_flush)));
-	} else {
-		while (*wrb_flush)
-			;
-	}
-    }
     return(0);
 }
 
@@ -710,24 +700,17 @@ pcibr_slot_initial_rrb_alloc(vertex_hdl_t pcibr_vhdl,
     for (vchan = 0; vchan < vchan_total; vchan++) 
         chan[vchan] = do_pcibr_rrb_count_valid(bridge, slot, vchan);
 
-    if (IS_PIC_SOFT(pcibr_soft)) {
     PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_vhdl,
 	    "pcibr_slot_initial_rrb_alloc: slot %d started with %d+%d+%d+%d\n",
 	    PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), 
 	    chan[VCHAN0], chan[VCHAN1], chan[VCHAN2], chan[VCHAN3]));
-    } else {
-	PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_vhdl,
-	    "pcibr_slot_initial_rrb_alloc: slot %d started with %d+%d\n",
-	    PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), 
-	    chan[VCHAN0], chan[VCHAN1]));
-    }
 
     /* Do we really need any?
      */
     pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
     pcibr_info = pcibr_infoh[0];
 
-    if (PCIBR_WAR_ENABLED(PV856866, pcibr_soft) && IS_PIC_SOFT(pcibr_soft) &&
+    if (PCIBR_WAR_ENABLED(PV856866, pcibr_soft) &&
                         (slot == 2 || slot == 3) &&
                         (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) &&
                         !pcibr_soft->bs_slot[slot].has_host) {
@@ -867,13 +850,8 @@ pcibr_rrb_debug(char *calling_func, pcibr_soft_t pcibr_soft)
                     "%s: rrbs available, even=%d, odd=%d\n", calling_func,
                     pcibr_soft->bs_rrb_avail[0], pcibr_soft->bs_rrb_avail[1]));
 
-        if (IS_PIC_SOFT(pcibr_soft)) {
         PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl,
                         "\tslot\tvchan0\tvchan1\tvchan2\tvchan3\treserved\n"));
-        } else {
-	    PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl,
-		        "\tslot\tvchan0\tvchan1\treserved\n"));
-        }
 
         for (slot=0; slot < PCIBR_NUM_SLOTS(pcibr_soft); slot++) {
 	    /*
@@ -881,7 +859,6 @@ pcibr_rrb_debug(char *calling_func, pcibr_soft_t pcibr_soft)
              * attempting to call PCIBR_DEBUG_ALWAYS() with more than 5 printf
              * arguments fails so sprintf() it into a temporary string.
              */
-	    if (IS_PIC_SOFT(pcibr_soft)) {
             sprintf(tmp_str, "\t %d\t  %d\t  %d\t  %d\t  %d\t  %d\n", 
 		        PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot),
                         0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN0],
@@ -889,14 +866,6 @@ pcibr_rrb_debug(char *calling_func, pcibr_soft_t pcibr_soft)
                         0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN2],
                         0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN3],
                         pcibr_soft->bs_rrb_res[slot]);
-	    } else {
-	        sprintf(tmp_str, "\t %d\t  %d\t  %d\t  %d\n", 
-		        PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot),
-		        0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN0],
-		        0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN1],
-		        pcibr_soft->bs_rrb_res[slot]);
-	    }
-    
             PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl,
                         "%s", tmp_str));
         }

arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c

@@ -380,13 +380,8 @@ pcibr_slot_info_return(pcibr_soft_t             pcibr_soft,
 
     slotp->resp_b_int_device = bridge->b_int_device;
 
-    if (IS_PIC_SOFT(pcibr_soft)) {
     slotp->resp_p_int_enable = bridge->p_int_enable_64;
     slotp->resp_p_int_host = bridge->p_int_addr_64[slot];
-    } else {
-	slotp->resp_b_int_enable = bridge->b_int_enable;
-	slotp->resp_b_int_host = bridge->b_int_addr[slot].addr;
-    }
 
     if (COPYOUT(slotp, respp, sizeof(*respp))) {
         return(EFAULT);
@@ -1364,7 +1359,7 @@ pcibr_slot_device_init(vertex_hdl_t pcibr_vhdl,
      * for 64-bit devices).  We set the bit in pcibr_try_set_device()
      * if we're 64-bit and requesting virtual channels.
      */
-    if (IS_PIC_SOFT(pcibr_soft) && PCIBR_WAR_ENABLED(PV855271, pcibr_soft))
+    if (PCIBR_WAR_ENABLED(PV855271, pcibr_soft))
 	devreg |= BRIDGE_DEV_COH;
     else
 	devreg |= BRIDGE_DEV_COH | BRIDGE_DEV_VIRTUAL_EN;

arch/ia64/sn/io/sn2/shub.c

@@ -6,8 +6,6 @@
  * Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc.  All Rights Reserved.
  */
 
-#ident  "$Revision: 1.167 $"
-
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <linux/interrupt.h>
@@ -35,43 +33,6 @@
 #include <asm/sn/sn2/shubio.h>
 #include <asm/sn/sn2/shub_mmr.h>
 
-/*
- * Shub WAR for Xbridge Little Endian problem:
- *	Xbridge has to run in BIG ENDIAN even with Shub.
- */
-
-
-/*
- * io_sh_swapper: Turn on Shub byte swapping.
- *	All data destined to and from Shub to XIO are byte-swapped.
- */
-void
-io_sh_swapper(nasid_t nasid, int onoff)
-{
-    ii_iwc_u_t      ii_iwc;
-
-    ii_iwc.ii_iwc_regval = REMOTE_HUB_L(nasid, IIO_IWC);
-
-    ii_iwc.ii_iwc_fld_s.i_dma_byte_swap = onoff;
-    REMOTE_HUB_S(nasid, IIO_IWC, ii_iwc.ii_iwc_regval);
-    ii_iwc.ii_iwc_regval = REMOTE_HUB_L(nasid, IIO_IWC);
-
-}
-
-/*
- * io_get_sh_swapper: Return current Swap mode.
- *	1 = Swap on, 0 = Swap off.
- */
-int
-io_get_sh_swapper(nasid_t nasid)
-{
-    ii_iwc_u_t      ii_iwc;
-
-    ii_iwc.ii_iwc_regval = REMOTE_HUB_L(nasid, IIO_IWC);
-    return(ii_iwc.ii_iwc_fld_s.i_dma_byte_swap);
-
-}
-
 #define SHUB_NUM_ECF_REGISTERS 8
 
 static uint32_t	shub_perf_counts[SHUB_NUM_ECF_REGISTERS];

arch/ia64/sn/kernel/setup.c

@@ -216,7 +216,6 @@ sn_setup(char **cmdline_p)
 	long status, ticks_per_sec, drift;
 	int pxm;
 	int major = sn_sal_rev_major(), minor = sn_sal_rev_minor();
-	extern void io_sh_swapper(int, int);
 	extern nasid_t get_master_baseio_nasid(void);
 	extern void sn_cpu_init(void);
 
@@ -239,8 +238,6 @@ sn_setup(char **cmdline_p)
 		panic("PROM version too old\n");
 	}
 
-	io_sh_swapper(get_nasid(), 0);
-
 	master_nasid = get_nasid();
 	(void)get_console_nasid();
 	(void)get_master_baseio_nasid();

include/asm-ia64/sn/iograph.h

@@ -18,13 +18,10 @@
 /* edges names */
 #define EDGE_LBL_BUS			"bus"
 #define EDGE_LBL_CONN			".connection"
-#define EDGE_LBL_ECP			"ecp"		/* EPP/ECP plp */
-#define EDGE_LBL_ECPP			"ecpp"
 #define EDGE_LBL_GUEST			".guest"	/* For IOC3 */
 #define EDGE_LBL_HOST			".host"		/* For IOC3 */
 #define EDGE_LBL_PERFMON		"mon"
 #define EDGE_LBL_USRPCI			"usrpci"
-#define EDGE_LBL_VME			"vmebus"
 #define EDGE_LBL_BLOCK			"block"
 #define EDGE_LBL_BOARD			"board"
 #define EDGE_LBL_CHAR			"char"
@@ -34,50 +31,13 @@
 #define EDGE_LBL_DIRECT			"direct"
 #define EDGE_LBL_DISABLED		"disabled"
 #define EDGE_LBL_DISK			"disk"
-#define EDGE_LBL_DMA_ENGINE             "dma_engine"    /* Only available on
-							   VMEbus now        */
-#define EDGE_LBL_NET			"net"		/* all nw. devs */
-#define EDGE_LBL_EF			"ef"		/* For if_ef ethernet */
-#define EDGE_LBL_ET			"et"		/* For if_ee ethernet */
-#define EDGE_LBL_EC			"ec"		/* For if_ec2 ether */
-#define EDGE_LBL_ECF			"ec"		/* For if_ecf enet */
-#define EDGE_LBL_EM			"ec"		/* For O2 ether */
-#define EDGE_LBL_IPG			"ipg"		/* For IPG FDDI */
-#define EDGE_LBL_XPI			"xpi"		/* For IPG FDDI */
-#define EDGE_LBL_HIP			"hip"		/* For HIPPI */
-#define EDGE_LBL_GSN                    "gsn"           /* For GSN */
-#define EDGE_LBL_ATM			"atm"		/* For ATM */
-#define EDGE_LBL_FXP			"fxp"		/* For FXP ether */
-#define EDGE_LBL_EP			"ep"		/* For eplex ether */
-#define EDGE_LBL_VFE			"vfe"		/* For VFE ether */
-#define EDGE_LBL_GFE			"gfe"		/* For GFE ether */
-#define EDGE_LBL_RNS			"rns"		/* RNS PCI FDDI card */
-#define EDGE_LBL_MTR			"mtr"		/* MTR PCI 802.5 card */
-#define EDGE_LBL_FV			"fv"		/* FV VME 802.5 card */
-#define EDGE_LBL_GTR			"gtr"		/* GTR GIO 802.5 card */
-#define EDGE_LBL_ISDN                   "isdn"		/* Digi PCI ISDN-BRI card */
-
-#define EDGE_LBL_EISA			"eisa"
-#define EDGE_LBL_ENET			"ethernet"
-#define EDGE_LBL_FLOPPY			"floppy"
-#define EDGE_LBL_PFD			"pfd"		/* For O2 pfd floppy */
-#define EDGE_LBL_FOP                    "fop"           /* Fetchop pseudo device */
-#define EDGE_LBL_GIO			"gio"
-#define EDGE_LBL_HEART			"heart"		/* For RACER */
-#define EDGE_LBL_HPC			"hpc"
-#define EDGE_LBL_GFX			"gfx"
 #define EDGE_LBL_HUB			"hub"		/* For SN0 */
 #define EDGE_LBL_HW			"hw"
-#define EDGE_LBL_SYNERGY		"synergy"	/* For SNIA only */
-#define EDGE_LBL_IBUS			"ibus"		/* For EVEREST */
 #define EDGE_LBL_INTERCONNECT		"link"
 #define EDGE_LBL_IO			"io"
-#define EDGE_LBL_IO4			"io4"		/* For EVEREST */
-#define EDGE_LBL_IOC3			"ioc3"
 #define EDGE_LBL_LUN                    "lun"
 #define EDGE_LBL_LINUX                  "linux"
 #define EDGE_LBL_LINUX_BUS              EDGE_LBL_LINUX "/bus/pci-x"
-#define EDGE_LBL_MACE                   "mace" 		/* O2 mace */
 #define EDGE_LBL_MACHDEP                "machdep"       /* Platform depedent devices */
 #define EDGE_LBL_MASTER			".master"
 #define EDGE_LBL_MEMORY			"memory"
@@ -102,11 +62,8 @@
 #define EDGE_LBL_SCSI			"scsi"
 #define EDGE_LBL_SCSI_CTLR		"scsi_ctlr"
 #define EDGE_LBL_SLOT			"slot"
-#define EDGE_LBL_TAPE			"tape"
 #define EDGE_LBL_TARGET                 "target"
 #define EDGE_LBL_UNKNOWN		"unknown"
-#define EDGE_LBL_VOLUME			"volume"
-#define EDGE_LBL_VOLUME_HEADER		"volume_header"
 #define EDGE_LBL_XBOW			"xbow"
 #define	EDGE_LBL_XIO			"xio"
 #define EDGE_LBL_XSWITCH		".xswitch"
@@ -114,23 +71,15 @@
 #define EDGE_LBL_XWIDGET		"xwidget"
 #define EDGE_LBL_ELSC			"elsc"
 #define EDGE_LBL_L1			"L1"
-#define EDGE_LBL_MADGE_TR               "Madge-tokenring"
 #define EDGE_LBL_XPLINK			"xplink" 	/* Cross partition */
 #define	EDGE_LBL_XPLINK_NET		"net" 		/* XP network devs */
 #define	EDGE_LBL_XPLINK_RAW		"raw"		/* XP Raw devs */
 #define EDGE_LBL_SLAB			"slab"		/* Slab of a module */
 #define	EDGE_LBL_XPLINK_KERNEL		"kernel"	/* XP kernel devs */
 #define	EDGE_LBL_XPLINK_ADMIN		"admin"	   	/* Partition admin */
-#define	EDGE_LBL_KAIO			"kaio"	   	/* Kernel async i/o poll */
-#define EDGE_LBL_RPS                    "rps"           /* redundant power supply */ 
-#define EDGE_LBL_XBOX_RPS               "xbox_rps"      /* redundant power supply for xbox unit */ 
 #define EDGE_LBL_IOBRICK		"iobrick"
-#define EDGE_LBL_PBRICK			"Pbrick"
-#define EDGE_LBL_PEBRICK		"PEbrick"
 #define EDGE_LBL_PXBRICK		"PXbrick"
 #define EDGE_LBL_IXBRICK		"IXbrick"
-#define EDGE_LBL_IBRICK			"Ibrick"
-#define EDGE_LBL_XBRICK			"Xbrick"
 #define EDGE_LBL_CGBRICK		"CGbrick"
 #define EDGE_LBL_CPUBUS			"cpubus"	/* CPU Interfaces (SysAd) */
 
@@ -147,19 +96,11 @@
 #define INFO_LBL_DRIVER			"_driver"	/* points to attached device_driver_t */
 #define INFO_LBL_ELSC			"_elsc"
 #define	INFO_LBL_SUBCH			"_subch"	/* system controller subchannel */
-#define INFO_LBL_L1SCP			"_l1scp"	/* points to l1sc_t */
-#define INFO_LBL_FC_PORTNAME		"_fc_portname"
-#define INFO_LBL_GIOIO			"_gioio"
-#define INFO_LBL_GFUNCS			"_gioio_ops"	/* ops vector for gio providers */
 #define INFO_LBL_HUB_INFO		"_hubinfo"
 #define INFO_LBL_HWGFSLIST		"_hwgfs_list"
 #define INFO_LBL_TRAVERSE		"_hwg_traverse" /* hwgraph traverse function */
-#define INFO_LBL_INVENT 		"_invent"	/* inventory data */
-#define INFO_LBL_MLRESET		"_mlreset"	/* present if device preinitialized */
 #define INFO_LBL_MODULE_INFO		"_module"	/* module data ptr */
-#define INFO_LBL_MONDATA		"_mon"		/* monitor data ptr */
 #define INFO_LBL_MDPERF_DATA		"_mdperf"	/* mdperf monitoring*/
-#define INFO_LBL_NIC			"_nic"
 #define INFO_LBL_NODE_INFO		"_node"
 #define	INFO_LBL_PCIBR_HINTS		"_pcibr_hints"
 #define INFO_LBL_PCIIO			"_pciio"
@@ -167,15 +108,11 @@
 #define INFO_LBL_PERMISSIONS		"_permissions"	/* owner, uid, gid */
 #define INFO_LBL_ROUTER_INFO		"_router"
 #define INFO_LBL_SUBDEVS		"_subdevs"	/* subdevice enable bits */
-#define INFO_LBL_VME_FUNCS		"_vmeio_ops"	/* ops vector for VME providers */
 #define INFO_LBL_XSWITCH		"_xswitch"
 #define INFO_LBL_XSWITCH_ID		"_xswitch_id"
 #define INFO_LBL_XSWITCH_VOL		"_xswitch_volunteer"
 #define INFO_LBL_XFUNCS			"_xtalk_ops"	/* ops vector for gio providers */
 #define INFO_LBL_XWIDGET		"_xwidget"
-#define INFO_LBL_GRIO_DSK		"_grio_disk"	/* guaranteed rate I/O */
-#define INFO_LBL_ASYNC_ATTACH           "_async_attach"	/* parallel attachment */
-#define INFO_LBL_GFXID			"_gfxid"	/* gfx pipe ID #s */
 /* Device/Driver  Admin directive labels  */
 #define ADMIN_LBL_INTR_TARGET		"INTR_TARGET"	/* Target cpu for device interrupts*/
 #define ADMIN_LBL_INTR_SWLEVEL		"INTR_SWLEVEL"	/* Priority level of the ithread */

include/asm-ia64/sn/klconfig.h

@@ -73,9 +73,7 @@ typedef s32 klconf_off_t;
                                    	   are discovered twice. Use one of them */
 #define VISITED_BOARD		0x08	/* Used for compact hub numbering. */
 #define LOCAL_MASTER_IO6	0x10    /* master io6 for that node */
-#define GLOBAL_MASTER_IO6	0x20
-#define GLOBAL_MASTER_EXT 	0x40  	/* extend master io6 to other bus on ibrick */
-#define SECOND_NIC_PRESENT 	0x80 	/* addons like MIO are present */
+#define KLTYPE_IOBRICK_XBOW	(KLCLASS_MIDPLANE | 0x2)
 
 /* klinfo->flags fields */
 
@@ -347,47 +345,18 @@ typedef struct kl_config_hdr {
 
 #define KLTYPE_WEIRDIO	(KLCLASS_IOBRICK  | 0x0)
 #define KLTYPE_BASEIO	(KLCLASS_IO  | 0x1) /* IOC3, SuperIO, Bridge, SCSI */
-#define KLTYPE_IO6	KLTYPE_BASEIO       /* Additional name */
-#define KLTYPE_4CHSCSI	(KLCLASS_IO  | 0x2)
-#define KLTYPE_MSCSI	KLTYPE_4CHSCSI      /* Additional name */
 #define KLTYPE_ETHERNET	(KLCLASS_IO  | 0x3)
-#define KLTYPE_MENET	KLTYPE_ETHERNET     /* Additional name */
 #define KLTYPE_FDDI  	(KLCLASS_IO  | 0x4)
-#define KLTYPE_UNUSED	(KLCLASS_IO  | 0x5) /* XXX UNUSED */
-#define KLTYPE_HAROLD   (KLCLASS_IO  | 0x6) /* PCI SHOE BOX */
-#define KLTYPE_PCI	KLTYPE_HAROLD
-#define KLTYPE_VME      (KLCLASS_IO  | 0x7) /* Any 3rd party VME card */
-#define KLTYPE_MIO   	(KLCLASS_IO  | 0x8)
 #define KLTYPE_FC    	(KLCLASS_IO  | 0x9)
-#define KLTYPE_LINC    	(KLCLASS_IO  | 0xA)
-#define KLTYPE_TPU    	(KLCLASS_IO  | 0xB) /* Tensor Processing Unit */
 #define KLTYPE_GSN_A   	(KLCLASS_IO  | 0xC) /* Main GSN board */
 #define KLTYPE_GSN_B   	(KLCLASS_IO  | 0xD) /* Auxiliary GSN board */
-#define KLTYPE_SHOEHORN (KLCLASS_IO  | 0xE)
-#define KLTYPE_SERIAL_HIPPI (KLCLASS_IO  | 0xF)
-
-#define KLTYPE_GFX	(KLCLASS_GFX | 0x0) /* unknown graphics type */
-#define KLTYPE_GFX_KONA (KLCLASS_GFX | 0x1) /* KONA graphics on IP27 */
-#define KLTYPE_GFX_MGRA (KLCLASS_GFX | 0x3) /* MGRAS graphics on IP27 */
 
-#define KLTYPE_WEIRDROUTER (KLCLASS_ROUTER | 0x0)
 #define KLTYPE_ROUTER     (KLCLASS_ROUTER | 0x1)
-#define KLTYPE_ROUTER2    KLTYPE_ROUTER		/* Obsolete! */
-#define KLTYPE_NULL_ROUTER (KLCLASS_ROUTER | 0x2)
 #define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
 #define KLTYPE_REPEATER_ROUTER (KLCLASS_ROUTER | 0x4)
 
-#define KLTYPE_WEIRDMIDPLANE (KLCLASS_MIDPLANE | 0x0)
-#define KLTYPE_MIDPLANE8  (KLCLASS_MIDPLANE | 0x1) /* 8 slot backplane */
-#define KLTYPE_MIDPLANE    KLTYPE_MIDPLANE8
-#define KLTYPE_IOBRICK_XBOW	(KLCLASS_MIDPLANE | 0x2)
-
 #define KLTYPE_IOBRICK		(KLCLASS_IOBRICK | 0x0)
-#define KLTYPE_IBRICK		(KLCLASS_IOBRICK | 0x1)
-#define KLTYPE_PBRICK		(KLCLASS_IOBRICK | 0x2)
-#define KLTYPE_XBRICK		(KLCLASS_IOBRICK | 0x3)
 #define KLTYPE_NBRICK		(KLCLASS_IOBRICK | 0x4)
-#define KLTYPE_PEBRICK		(KLCLASS_IOBRICK | 0x5)
 #define KLTYPE_PXBRICK		(KLCLASS_IOBRICK | 0x6)
 #define KLTYPE_IXBRICK		(KLCLASS_IOBRICK | 0x7)
 #define KLTYPE_CGBRICK		(KLCLASS_IOBRICK | 0x8)
@@ -406,9 +375,6 @@ typedef struct kl_config_hdr {
 #define KLTYPE_UNKNOWN	(KLCLASS_UNKNOWN | 0xf)
 
 #define KLTYPE(_x) 	((_x) & KLTYPE_MASK)
-#define IS_MIO_PRESENT(l)	((l->brd_type == KLTYPE_BASEIO) && \
-				 (l->brd_flags & SECOND_NIC_PRESENT))
-#define IS_MIO_IOC3(l,n)	(IS_MIO_PRESENT(l) && (n > 2))
 
 /* 
  * board structures

include/asm-ia64/sn/ksys/l1.h

@@ -89,13 +89,8 @@
 /* brick type response codes */
 #define L1_BRICKTYPE_IP45       0x34            /* 4 */
 #define L1_BRICKTYPE_C          0x43            /* C */
-#define L1_BRICKTYPE_I          0x49            /* I */
-#define L1_BRICKTYPE_P          0x50            /* P */
 #define L1_BRICKTYPE_R          0x52            /* R */
-#define L1_BRICKTYPE_X          0x58            /* X */
-#define L1_BRICKTYPE_X2         0x59            /* Y */
 #define L1_BRICKTYPE_N          0x4e            /* N */
-#define L1_BRICKTYPE_PE		0x25		/* % */
 #define L1_BRICKTYPE_PX		0x23		/* # */
 #define L1_BRICKTYPE_IX		0x3d		/* = */
 

include/asm-ia64/sn/pci/pci_bus_cvlink.h

@@ -38,8 +38,6 @@
 #define IS_PCI32G(dev)	((dev)->dma_mask >= 0xffffffff)
 #define IS_PCI32L(dev)	((dev)->dma_mask < 0xffffffff)
 
-#define IS_PIC_DEVICE(dev) ((struct sn_device_sysdata *)dev->sysdata)->isPIC
-
 #define PCIDEV_VERTEX(pci_dev) \
 	(((struct sn_device_sysdata *)((pci_dev)->sysdata))->vhdl)
 
@@ -53,7 +51,6 @@ struct sn_widget_sysdata {
 struct sn_device_sysdata {
         vertex_hdl_t  vhdl;
 	int		isa64;
-	int		isPIC;
 	volatile unsigned int *dma_buf_sync;
 	volatile unsigned int *xbow_buf_sync;
 };

include/asm-ia64/sn/pci/pcibr_private.h

@@ -199,14 +199,10 @@ struct pcibr_intr_s {
 #define PCIBR_INFO_SLOT_GET_INT(info)	    (((pcibr_info_t)info)->f_dev)
 
 #define PCIBR_DEVICE_TO_SLOT(pcibr_soft, dev_num) \
-	(((dev_num) != PCIIO_SLOT_NONE) ? \
-	    (IS_PIC_SOFT((pcibr_soft)) ? ((dev_num) + 1) : (dev_num)) : \
-	    PCIIO_SLOT_NONE)
+	(((dev_num) != PCIIO_SLOT_NONE) ? ((dev_num) + 1) : PCIIO_SLOT_NONE)
 
 #define PCIBR_SLOT_TO_DEVICE(pcibr_soft, slot) \
-        (((slot) != PCIIO_SLOT_NONE) ? \
-            (IS_PIC_SOFT((pcibr_soft)) ? ((slot) - 1) : (slot)) : \
-            PCIIO_SLOT_NONE)
+        (((slot) != PCIIO_SLOT_NONE) ? ((slot) - 1) : PCIIO_SLOT_NONE)
 
 /*
  * per-connect point pcibr data, including standard pciio data in-line:
@@ -287,12 +283,7 @@ struct pcibr_intr_wrap_s {
 #define PCIBR_BRIDGETYPE_BRIDGE		0
 #define PCIBR_BRIDGETYPE_XBRIDGE	1
 #define PCIBR_BRIDGETYPE_PIC		2
-#define IS_XBRIDGE_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_XBRIDGE)
-#define IS_PIC_SOFT(ps)     (ps->bs_bridge_type == PCIBR_BRIDGETYPE_PIC)
-#define IS_PIC_BUSNUM_SOFT(ps, bus)	\
-		(IS_PIC_SOFT(ps) && ((ps)->bs_busnum == (bus)))
-#define IS_BRIDGE_SOFT(ps)  (ps->bs_bridge_type == PCIBR_BRIDGETYPE_BRIDGE)
-#define IS_XBRIDGE_OR_PIC_SOFT(ps) (IS_XBRIDGE_SOFT(ps) || IS_PIC_SOFT(ps))
+#define IS_PIC_BUSNUM_SOFT(ps, bus)	((ps)->bs_busnum == (bus))
 
 /*
  * Runtime checks for workarounds.