Commit 7e257003 authored by Stephen Boyd's avatar Stephen Boyd

Merge branches 'clk-of-refcount', 'clk-mmio-fixed-clock', 'clk-remove-clps',...

Merge branches 'clk-of-refcount', 'clk-mmio-fixed-clock', 'clk-remove-clps', 'clk-socfpga-parent' and 'clk-struct-size' into clk-next

 - Various DT of_node refcount fixes
 - Support for fixed rate clks populated from an MMIO register
 - Remove clps711x driver as the board support is gone

* clk-of-refcount:
  clk: dove: fix refcount leak in dove_clk_init()
  clk: mv98dx3236: fix refcount leak in mv98dx3236_clk_init()
  clk: armada-xp: fix refcount leak in axp_clk_init()
  clk: kirkwood: fix refcount leak in kirkwood_clk_init()
  clk: armada-370: fix refcount leak in a370_clk_init()
  clk: vf610: fix refcount leak in vf610_clocks_init()
  clk: imx7d: fix refcount leak in imx7d_clocks_init()
  clk: imx6sx: fix refcount leak in imx6sx_clocks_init()
  clk: imx6q: fix refcount leak in imx6q_clocks_init()
  clk: samsung: exynos4: fix refcount leak in exynos4_get_xom()
  clk: socfpga: fix refcount leak
  clk: ti: fix refcount leak in ti_dt_clocks_register()
  clk: qoriq: fix refcount leak in clockgen_init()
  clk: highbank: fix refcount leak in hb_clk_init()

* clk-mmio-fixed-clock:
  clk: Add Fixed MMIO clock driver
  dt-bindings: clk: Add bindings for Fixed MMIO clock

* clk-remove-clps:
  clk: clps711x: Remove board support

* clk-socfpga-parent:
  clk: socfpga: Don't have get_parent for single parent ops

* clk-struct-size:
  clk: imx: imx7ulp: use struct_size() in kzalloc()
Binding for simple memory mapped io fixed-rate clock sources.
The driver reads a clock frequency value from a single 32-bit memory mapped
I/O register and registers it as a fixed rate clock.
It was designed for test systems, like FPGA, not for complete, finished SoCs.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "fixed-mmio-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- reg : Address and length of the clock value register set.
Optional properties:
- clock-output-names : From common clock binding.
Example:
sysclock: sysclock@fd020004 {
#clock-cells = <0>;
compatible = "fixed-mmio-clock";
reg = <0xfd020004 0x4>;
};
...@@ -290,6 +290,12 @@ config COMMON_CLK_BD718XX ...@@ -290,6 +290,12 @@ config COMMON_CLK_BD718XX
This driver supports ROHM BD71837 and ROHM BD71847 This driver supports ROHM BD71837 and ROHM BD71847
PMICs clock gates. PMICs clock gates.
config COMMON_CLK_FIXED_MMIO
bool "Clock driver for Memory Mapped Fixed values"
depends on COMMON_CLK && OF
help
Support for Memory Mapped IO Fixed clocks
source "drivers/clk/actions/Kconfig" source "drivers/clk/actions/Kconfig"
source "drivers/clk/bcm/Kconfig" source "drivers/clk/bcm/Kconfig"
source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/hisilicon/Kconfig"
......
...@@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o ...@@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
......
...@@ -44,21 +44,21 @@ struct clps711x_clk { ...@@ -44,21 +44,21 @@ struct clps711x_clk {
struct clk_hw_onecell_data clk_data; struct clk_hw_onecell_data clk_data;
}; };
static struct clps711x_clk * __init _clps711x_clk_init(void __iomem *base, static void __init clps711x_clk_init_dt(struct device_node *np)
u32 fref)
{ {
u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi; u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi, fref = 0;
struct clps711x_clk *clps711x_clk; struct clps711x_clk *clps711x_clk;
unsigned i; void __iomem *base;
WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));
if (!base) base = of_iomap(np, 0);
return ERR_PTR(-ENOMEM); BUG_ON(!base);
clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws, clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws,
CLPS711X_CLK_MAX), CLPS711X_CLK_MAX),
GFP_KERNEL); GFP_KERNEL);
if (!clps711x_clk) BUG_ON(!clps711x_clk);
return ERR_PTR(-ENOMEM);
spin_lock_init(&clps711x_clk->lock); spin_lock_init(&clps711x_clk->lock);
...@@ -137,52 +137,13 @@ static struct clps711x_clk * __init _clps711x_clk_init(void __iomem *base, ...@@ -137,52 +137,13 @@ static struct clps711x_clk * __init _clps711x_clk_init(void __iomem *base,
clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10); clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10);
clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] = clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] =
clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64); clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64);
for (i = 0; i < CLPS711X_CLK_MAX; i++) for (tmp = 0; tmp < CLPS711X_CLK_MAX; tmp++)
if (IS_ERR(clps711x_clk->clk_data.hws[i])) if (IS_ERR(clps711x_clk->clk_data.hws[tmp]))
pr_err("clk %i: register failed with %ld\n", pr_err("clk %i: register failed with %ld\n",
i, PTR_ERR(clps711x_clk->clk_data.hws[i])); tmp, PTR_ERR(clps711x_clk->clk_data.hws[tmp]));
return clps711x_clk;
}
void __init clps711x_clk_init(void __iomem *base)
{
struct clps711x_clk *clps711x_clk;
clps711x_clk = _clps711x_clk_init(base, 73728000);
BUG_ON(IS_ERR(clps711x_clk));
/* Clocksource */
clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1],
NULL, "clps711x-timer.0");
clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2],
NULL, "clps711x-timer.1");
/* Drivers */
clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM],
NULL, "clps711x-pwm");
clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_UART],
NULL, "clps711x-uart.0");
clk_hw_register_clkdev(clps711x_clk->clk_data.hws[CLPS711X_CLK_UART],
NULL, "clps711x-uart.1");
}
#ifdef CONFIG_OF
static void __init clps711x_clk_init_dt(struct device_node *np)
{
void __iomem *base = of_iomap(np, 0);
struct clps711x_clk *clps711x_clk;
u32 fref = 0;
WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));
clps711x_clk = _clps711x_clk_init(base, fref);
BUG_ON(IS_ERR(clps711x_clk));
clps711x_clk->clk_data.num = CLPS711X_CLK_MAX; clps711x_clk->clk_data.num = CLPS711X_CLK_MAX;
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
&clps711x_clk->clk_data); &clps711x_clk->clk_data);
} }
CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt); CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt);
#endif
// SPDX-License-Identifier: GPL-2.0
/*
* Memory Mapped IO Fixed clock driver
*
* Copyright (C) 2018 Cadence Design Systems, Inc.
*
* Authors:
* Jan Kotas <jank@cadence.com>
*/
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/module.h>
#include <linux/platform_device.h>
static struct clk_hw *fixed_mmio_clk_setup(struct device_node *node)
{
struct clk_hw *clk;
const char *clk_name = node->name;
void __iomem *base;
u32 freq;
int ret;
base = of_iomap(node, 0);
if (!base) {
pr_err("%pOFn: failed to map address\n", node);
return ERR_PTR(-EIO);
}
freq = readl(base);
iounmap(base);
of_property_read_string(node, "clock-output-names", &clk_name);
clk = clk_hw_register_fixed_rate(NULL, clk_name, NULL, 0, freq);
if (IS_ERR(clk)) {
pr_err("%pOFn: failed to register fixed rate clock\n", node);
return clk;
}
ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, clk);
if (ret) {
pr_err("%pOFn: failed to add clock provider\n", node);
clk_hw_unregister(clk);
clk = ERR_PTR(ret);
}
return clk;
}
static void __init of_fixed_mmio_clk_setup(struct device_node *node)
{
fixed_mmio_clk_setup(node);
}
CLK_OF_DECLARE(fixed_mmio_clk, "fixed-mmio-clock", of_fixed_mmio_clk_setup);
/**
* This is not executed when of_fixed_mmio_clk_setup succeeded.
*/
static int of_fixed_mmio_clk_probe(struct platform_device *pdev)
{
struct clk_hw *clk;
clk = fixed_mmio_clk_setup(pdev->dev.of_node);
if (IS_ERR(clk))
return PTR_ERR(clk);
platform_set_drvdata(pdev, clk);
return 0;
}
static int of_fixed_mmio_clk_remove(struct platform_device *pdev)
{
struct clk_hw *clk = platform_get_drvdata(pdev);
of_clk_del_provider(pdev->dev.of_node);
clk_hw_unregister_fixed_rate(clk);
return 0;
}
static const struct of_device_id of_fixed_mmio_clk_ids[] = {
{ .compatible = "fixed-mmio-clock" },
{ }
};
MODULE_DEVICE_TABLE(of, of_fixed_mmio_clk_ids);
static struct platform_driver of_fixed_mmio_clk_driver = {
.driver = {
.name = "of_fixed_mmio_clk",
.of_match_table = of_fixed_mmio_clk_ids,
},
.probe = of_fixed_mmio_clk_probe,
.remove = of_fixed_mmio_clk_remove,
};
module_platform_driver(of_fixed_mmio_clk_driver);
MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
MODULE_DESCRIPTION("Memory Mapped IO Fixed clock driver");
MODULE_LICENSE("GPL v2");
...@@ -293,6 +293,7 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk ...@@ -293,6 +293,7 @@ static __init struct clk *hb_clk_init(struct device_node *node, const struct clk
/* Map system registers */ /* Map system registers */
srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
hb_clk->reg = of_iomap(srnp, 0); hb_clk->reg = of_iomap(srnp, 0);
of_node_put(srnp);
BUG_ON(!hb_clk->reg); BUG_ON(!hb_clk->reg);
hb_clk->reg += reg; hb_clk->reg += reg;
......
...@@ -1389,6 +1389,7 @@ static void __init clockgen_init(struct device_node *np) ...@@ -1389,6 +1389,7 @@ static void __init clockgen_init(struct device_node *np)
pr_err("%s: Couldn't map %pOF regs\n", __func__, pr_err("%s: Couldn't map %pOF regs\n", __func__,
guts); guts);
} }
of_node_put(guts);
} }
} }
......
...@@ -471,6 +471,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -471,6 +471,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
anatop_base = base = of_iomap(np, 0); anatop_base = base = of_iomap(np, 0);
WARN_ON(!base); WARN_ON(!base);
of_node_put(np);
/* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
......
...@@ -151,6 +151,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) ...@@ -151,6 +151,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
base = of_iomap(np, 0); base = of_iomap(np, 0);
WARN_ON(!base); WARN_ON(!base);
of_node_put(np);
clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
......
...@@ -404,6 +404,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) ...@@ -404,6 +404,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop"); np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop");
base = of_iomap(np, 0); base = of_iomap(np, 0);
WARN_ON(!base); WARN_ON(!base);
of_node_put(np);
clks[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); clks[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
clks[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); clks[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
......
...@@ -48,8 +48,8 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) ...@@ -48,8 +48,8 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
struct clk_hw **clks; struct clk_hw **clks;
void __iomem *base; void __iomem *base;
clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws) * clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_SCG1_END),
IMX7ULP_CLK_SCG1_END, GFP_KERNEL); GFP_KERNEL);
if (!clk_data) if (!clk_data)
return; return;
...@@ -136,8 +136,8 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np) ...@@ -136,8 +136,8 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
struct clk_hw **clks; struct clk_hw **clks;
void __iomem *base; void __iomem *base;
clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws) * clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END),
IMX7ULP_CLK_PCC2_END, GFP_KERNEL); GFP_KERNEL);
if (!clk_data) if (!clk_data)
return; return;
...@@ -183,8 +183,8 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np) ...@@ -183,8 +183,8 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
struct clk_hw **clks; struct clk_hw **clks;
void __iomem *base; void __iomem *base;
clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws) * clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END),
IMX7ULP_CLK_PCC3_END, GFP_KERNEL); GFP_KERNEL);
if (!clk_data) if (!clk_data)
return; return;
...@@ -228,8 +228,8 @@ static void __init imx7ulp_clk_smc1_init(struct device_node *np) ...@@ -228,8 +228,8 @@ static void __init imx7ulp_clk_smc1_init(struct device_node *np)
struct clk_hw **clks; struct clk_hw **clks;
void __iomem *base; void __iomem *base;
clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws) * clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_SMC1_END),
IMX7ULP_CLK_SMC1_END, GFP_KERNEL); GFP_KERNEL);
if (!clk_data) if (!clk_data)
return; return;
......
...@@ -203,6 +203,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) ...@@ -203,6 +203,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop"); np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop");
anatop_base = of_iomap(np, 0); anatop_base = of_iomap(np, 0);
BUG_ON(!anatop_base); BUG_ON(!anatop_base);
of_node_put(np);
np = ccm_node; np = ccm_node;
ccm_base = of_iomap(np, 0); ccm_base = of_iomap(np, 0);
......
...@@ -175,8 +175,10 @@ static void __init a370_clk_init(struct device_node *np) ...@@ -175,8 +175,10 @@ static void __init a370_clk_init(struct device_node *np)
mvebu_coreclk_setup(np, &a370_coreclks); mvebu_coreclk_setup(np, &a370_coreclks);
if (cgnp) if (cgnp) {
mvebu_clk_gating_setup(cgnp, a370_gating_desc); mvebu_clk_gating_setup(cgnp, a370_gating_desc);
of_node_put(cgnp);
}
} }
CLK_OF_DECLARE(a370_clk, "marvell,armada-370-core-clock", a370_clk_init); CLK_OF_DECLARE(a370_clk, "marvell,armada-370-core-clock", a370_clk_init);
...@@ -226,7 +226,9 @@ static void __init axp_clk_init(struct device_node *np) ...@@ -226,7 +226,9 @@ static void __init axp_clk_init(struct device_node *np)
mvebu_coreclk_setup(np, &axp_coreclks); mvebu_coreclk_setup(np, &axp_coreclks);
if (cgnp) if (cgnp) {
mvebu_clk_gating_setup(cgnp, axp_gating_desc); mvebu_clk_gating_setup(cgnp, axp_gating_desc);
of_node_put(cgnp);
}
} }
CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init); CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);
...@@ -188,10 +188,14 @@ static void __init dove_clk_init(struct device_node *np) ...@@ -188,10 +188,14 @@ static void __init dove_clk_init(struct device_node *np)
mvebu_coreclk_setup(np, &dove_coreclks); mvebu_coreclk_setup(np, &dove_coreclks);
if (ddnp) if (ddnp) {
dove_divider_clk_init(ddnp); dove_divider_clk_init(ddnp);
of_node_put(ddnp);
}
if (cgnp) if (cgnp) {
mvebu_clk_gating_setup(cgnp, dove_gating_desc); mvebu_clk_gating_setup(cgnp, dove_gating_desc);
of_node_put(cgnp);
}
} }
CLK_OF_DECLARE(dove_clk, "marvell,dove-core-clock", dove_clk_init); CLK_OF_DECLARE(dove_clk, "marvell,dove-core-clock", dove_clk_init);
...@@ -331,6 +331,8 @@ static void __init kirkwood_clk_init(struct device_node *np) ...@@ -331,6 +331,8 @@ static void __init kirkwood_clk_init(struct device_node *np)
if (cgnp) { if (cgnp) {
mvebu_clk_gating_setup(cgnp, kirkwood_gating_desc); mvebu_clk_gating_setup(cgnp, kirkwood_gating_desc);
kirkwood_clk_muxing_setup(cgnp, kirkwood_mux_desc); kirkwood_clk_muxing_setup(cgnp, kirkwood_mux_desc);
of_node_put(cgnp);
} }
} }
CLK_OF_DECLARE(kirkwood_clk, "marvell,kirkwood-core-clock", CLK_OF_DECLARE(kirkwood_clk, "marvell,kirkwood-core-clock",
......
...@@ -172,7 +172,9 @@ static void __init mv98dx3236_clk_init(struct device_node *np) ...@@ -172,7 +172,9 @@ static void __init mv98dx3236_clk_init(struct device_node *np)
mvebu_coreclk_setup(np, &mv98dx3236_core_clocks); mvebu_coreclk_setup(np, &mv98dx3236_core_clocks);
if (cgnp) if (cgnp) {
mvebu_clk_gating_setup(cgnp, mv98dx3236_gating_desc); mvebu_clk_gating_setup(cgnp, mv98dx3236_gating_desc);
of_node_put(cgnp);
}
} }
CLK_OF_DECLARE(mv98dx3236_clk, "marvell,mv98dx3236-core-clock", mv98dx3236_clk_init); CLK_OF_DECLARE(mv98dx3236_clk, "marvell,mv98dx3236-core-clock", mv98dx3236_clk_init);
...@@ -1028,6 +1028,7 @@ static unsigned long __init exynos4_get_xom(void) ...@@ -1028,6 +1028,7 @@ static unsigned long __init exynos4_get_xom(void)
xom = readl(chipid_base + 8); xom = readl(chipid_base + 8);
iounmap(chipid_base); iounmap(chipid_base);
of_node_put(np);
} }
return xom; return xom;
......
...@@ -176,8 +176,7 @@ static struct clk_ops gateclk_ops = { ...@@ -176,8 +176,7 @@ static struct clk_ops gateclk_ops = {
.set_parent = socfpga_clk_set_parent, .set_parent = socfpga_clk_set_parent,
}; };
static void __init __socfpga_gate_init(struct device_node *node, void __init socfpga_gate_init(struct device_node *node)
const struct clk_ops *ops)
{ {
u32 clk_gate[2]; u32 clk_gate[2];
u32 div_reg[3]; u32 div_reg[3];
...@@ -188,12 +187,17 @@ static void __init __socfpga_gate_init(struct device_node *node, ...@@ -188,12 +187,17 @@ static void __init __socfpga_gate_init(struct device_node *node,
const char *clk_name = node->name; const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS]; const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init; struct clk_init_data init;
struct clk_ops *ops;
int rc; int rc;
socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
if (WARN_ON(!socfpga_clk)) if (WARN_ON(!socfpga_clk))
return; return;
ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
if (WARN_ON(!ops))
return;
rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
if (rc) if (rc)
clk_gate[0] = 0; clk_gate[0] = 0;
...@@ -202,8 +206,8 @@ static void __init __socfpga_gate_init(struct device_node *node, ...@@ -202,8 +206,8 @@ static void __init __socfpga_gate_init(struct device_node *node,
socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0]; socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
socfpga_clk->hw.bit_idx = clk_gate[1]; socfpga_clk->hw.bit_idx = clk_gate[1];
gateclk_ops.enable = clk_gate_ops.enable; ops->enable = clk_gate_ops.enable;
gateclk_ops.disable = clk_gate_ops.disable; ops->disable = clk_gate_ops.disable;
} }
rc = of_property_read_u32(node, "fixed-divider", &fixed_div); rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
...@@ -234,6 +238,11 @@ static void __init __socfpga_gate_init(struct device_node *node, ...@@ -234,6 +238,11 @@ static void __init __socfpga_gate_init(struct device_node *node,
init.flags = 0; init.flags = 0;
init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
if (init.num_parents < 2) {
ops->get_parent = NULL;
ops->set_parent = NULL;
}
init.parent_names = parent_name; init.parent_names = parent_name;
socfpga_clk->hw.hw.init = &init; socfpga_clk->hw.hw.init = &init;
...@@ -246,8 +255,3 @@ static void __init __socfpga_gate_init(struct device_node *node, ...@@ -246,8 +255,3 @@ static void __init __socfpga_gate_init(struct device_node *node,
if (WARN_ON(rc)) if (WARN_ON(rc))
return; return;
} }
void __init socfpga_gate_init(struct device_node *node)
{
__socfpga_gate_init(node, &gateclk_ops);
}
...@@ -95,6 +95,7 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node, ...@@ -95,6 +95,7 @@ static struct clk * __init __socfpga_pll_init(struct device_node *node,
clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
clk_mgr_a10_base_addr = of_iomap(clkmgr_np, 0); clk_mgr_a10_base_addr = of_iomap(clkmgr_np, 0);
of_node_put(clkmgr_np);
BUG_ON(!clk_mgr_a10_base_addr); BUG_ON(!clk_mgr_a10_base_addr);
pll_clk->hw.reg = clk_mgr_a10_base_addr + reg; pll_clk->hw.reg = clk_mgr_a10_base_addr + reg;
......
...@@ -100,6 +100,7 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node, ...@@ -100,6 +100,7 @@ static __init struct clk *__socfpga_pll_init(struct device_node *node,
clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
clk_mgr_base_addr = of_iomap(clkmgr_np, 0); clk_mgr_base_addr = of_iomap(clkmgr_np, 0);
of_node_put(clkmgr_np);
BUG_ON(!clk_mgr_base_addr); BUG_ON(!clk_mgr_base_addr);
pll_clk->hw.reg = clk_mgr_base_addr + reg; pll_clk->hw.reg = clk_mgr_base_addr + reg;
......
...@@ -191,9 +191,13 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[]) ...@@ -191,9 +191,13 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
clkdev_add(&c->lk); clkdev_add(&c->lk);
} else { } else {
if (num_args && !has_clkctrl_data) { if (num_args && !has_clkctrl_data) {
if (of_find_compatible_node(NULL, NULL, struct device_node *np;
"ti,clkctrl")) {
np = of_find_compatible_node(NULL, NULL,
"ti,clkctrl");
if (np) {
has_clkctrl_data = true; has_clkctrl_data = true;
of_node_put(np);
} else { } else {
clkctrl_nodes_missing = true; clkctrl_nodes_missing = true;
......
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