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Commit 7f9768a5 authored by Jerome Brunet's avatar Jerome Brunet Committed by Neil Armstrong
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clk: meson: migrate gates to clk_regmap 

Move meson8b, gxbb and axg clocks using clk_gate to clk_regmap
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
parent 161f6e5b
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Showing with 206 additions and 195 deletions
drivers/clk/meson/Kconfig
View file @ 7f9768a5
......@@ -11,7 +11,7 @@ config COMMON_CLK_MESON8B
bool
depends on COMMON_CLK_AMLOGIC
select RESET_CONTROLLER
select REGMAP
select COMMON_CLK_REGMAP_MESON
help
Support for the clock controller on AmLogic S802 (Meson8),
S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
......@@ -30,7 +30,7 @@ config COMMON_CLK_AXG
bool
depends on COMMON_CLK_AMLOGIC
select RESET_CONTROLLER
select REGMAP
select COMMON_CLK_REGMAP_MESON
help
Support for the clock controller on AmLogic A113D devices, aka axg.
Say Y if you want peripherals and CPU frequency scaling to work.
drivers/clk/meson/axg.c
View file @ 7f9768a5
......@@ -447,13 +447,14 @@ static struct clk_divider axg_mpeg_clk_div = {
},
};
static struct clk_gate axg_clk81 = {
.reg = (void *)HHI_MPEG_CLK_CNTL,
static struct clk_regmap axg_clk81 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_MPEG_CLK_CNTL,
.bit_idx = 7,
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "clk81",
.ops = &clk_gate_ops,
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpeg_clk_div" },
.num_parents = 1,
.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
......@@ -501,13 +502,14 @@ static struct clk_divider axg_sd_emmc_b_clk0_div = {
},
};
static struct clk_gate axg_sd_emmc_b_clk0 = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
static struct clk_regmap axg_sd_emmc_b_clk0 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_SD_EMMC_CLK_CNTL,
.bit_idx = 23,
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "sd_emmc_b_clk0",
.ops = &clk_gate_ops,
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -544,13 +546,14 @@ static struct clk_divider axg_sd_emmc_c_clk0_div = {
},
};
static struct clk_gate axg_sd_emmc_c_clk0 = {
.reg = (void *)HHI_NAND_CLK_CNTL,
static struct clk_regmap axg_sd_emmc_c_clk0 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_NAND_CLK_CNTL,
.bit_idx = 7,
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "sd_emmc_c_clk0",
.ops = &clk_gate_ops,
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -697,7 +700,19 @@ static struct meson_clk_mpll *const axg_clk_mplls[] = {
&axg_mpll3,
};
static struct clk_gate *const axg_clk_gates[] = {
static struct clk_mux *const axg_clk_muxes[] = {
&axg_mpeg_clk_sel,
&axg_sd_emmc_b_clk0_sel,
&axg_sd_emmc_c_clk0_sel,
};
static struct clk_divider *const axg_clk_dividers[] = {
&axg_mpeg_clk_div,
&axg_sd_emmc_b_clk0_div,
&axg_sd_emmc_c_clk0_div,
};
static struct clk_regmap *const axg_clk_regmaps[] = {
&axg_clk81,
&axg_ddr,
&axg_audio_locker,
......@@ -747,21 +762,7 @@ static struct clk_gate *const axg_clk_gates[] = {
&axg_sd_emmc_c_clk0,
};
static struct clk_mux *const axg_clk_muxes[] = {
&axg_mpeg_clk_sel,
&axg_sd_emmc_b_clk0_sel,
&axg_sd_emmc_c_clk0_sel,
};
static struct clk_divider *const axg_clk_dividers[] = {
&axg_mpeg_clk_div,
&axg_sd_emmc_b_clk0_div,
&axg_sd_emmc_c_clk0_div,
};
struct clkc_data {
struct clk_gate *const *clk_gates;
unsigned int clk_gates_count;
struct meson_clk_mpll *const *clk_mplls;
unsigned int clk_mplls_count;
struct meson_clk_pll *const *clk_plls;
......@@ -774,8 +775,6 @@ struct clkc_data {
};
static const struct clkc_data axg_clkc_data = {
.clk_gates = axg_clk_gates,
.clk_gates_count = ARRAY_SIZE(axg_clk_gates),
.clk_mplls = axg_clk_mplls,
.clk_mplls_count = ARRAY_SIZE(axg_clk_mplls),
.clk_plls = axg_clk_plls,
......@@ -834,11 +833,6 @@ static int axg_clkc_probe(struct platform_device *pdev)
for (i = 0; i < clkc_data->clk_mplls_count; i++)
clkc_data->clk_mplls[i]->base = clk_base;
/* Populate base address for gates */
for (i = 0; i < clkc_data->clk_gates_count; i++)
clkc_data->clk_gates[i]->reg = clk_base +
(u64)clkc_data->clk_gates[i]->reg;
/* Populate base address for muxes */
for (i = 0; i < clkc_data->clk_muxes_count; i++)
clkc_data->clk_muxes[i]->reg = clk_base +
......@@ -849,6 +843,10 @@ static int axg_clkc_probe(struct platform_device *pdev)
clkc_data->clk_dividers[i]->reg = clk_base +
(u64)clkc_data->clk_dividers[i]->reg;
/* Populate regmap for the regmap backed clocks */
for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++)
axg_clk_regmaps[i]->map = map;
for (i = 0; i < clkc_data->hw_onecell_data->num; i++) {
/* array might be sparse */
if (!clkc_data->hw_onecell_data->hws[i])
......
drivers/clk/meson/clkc.h
View file @ 7f9768a5
......@@ -18,6 +18,9 @@
#ifndef __CLKC_H
#define __CLKC_H
#include <linux/clk-provider.h>
#include "clk-regmap.h"
#define PMASK(width) GENMASK(width - 1, 0)
#define SETPMASK(width, shift) GENMASK(shift + width - 1, shift)
#define CLRPMASK(width, shift) (~SETPMASK(width, shift))
......@@ -134,13 +137,14 @@ struct meson_clk_audio_divider {
};
#define MESON_GATE(_name, _reg, _bit) \
struct clk_gate _name = { \
.reg = (void __iomem *) _reg, \
struct clk_regmap _name = { \
.data = &(struct clk_regmap_gate_data){ \
.offset = (_reg), \
.bit_idx = (_bit), \
.lock = &meson_clk_lock, \
}, \
.hw.init = &(struct clk_init_data) { \
.name = #_name, \
.ops = &clk_gate_ops, \
.ops = &clk_regmap_gate_ops, \
.parent_names = (const char *[]){ "clk81" }, \
.num_parents = 1, \
.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
......
drivers/clk/meson/gxbb.c
View file @ 7f9768a5
This diff is collapsed.
drivers/clk/meson/meson8b.c
View file @ 7f9768a5
......@@ -32,6 +32,7 @@
#include "clkc.h"
#include "meson8b.h"
#include "clk-regmap.h"
static DEFINE_SPINLOCK(meson_clk_lock);
......@@ -406,13 +407,14 @@ struct clk_divider meson8b_mpeg_clk_div = {
},
};
struct clk_gate meson8b_clk81 = {
.reg = (void *)HHI_MPEG_CLK_CNTL,
struct clk_regmap meson8b_clk81 = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_MPEG_CLK_CNTL,
.bit_idx = 7,
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){
.name = "clk81",
.ops = &clk_gate_ops,
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpeg_clk_div" },
.num_parents = 1,
.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
......@@ -617,7 +619,15 @@ static struct meson_clk_mpll *const meson8b_clk_mplls[] = {
&meson8b_mpll2,
};
static struct clk_gate *const meson8b_clk_gates[] = {
static struct clk_mux *const meson8b_clk_muxes[] = {
&meson8b_mpeg_clk_sel,
};
static struct clk_divider *const meson8b_clk_dividers[] = {
&meson8b_mpeg_clk_div,
};
static struct clk_regmap *const meson8b_clk_regmaps[] = {
&meson8b_clk81,
&meson8b_ddr,
&meson8b_dos,
......@@ -698,14 +708,6 @@ static struct clk_gate *const meson8b_clk_gates[] = {
&meson8b_ao_iface,
};
static struct clk_mux *const meson8b_clk_muxes[] = {
&meson8b_mpeg_clk_sel,
};
static struct clk_divider *const meson8b_clk_dividers[] = {
&meson8b_mpeg_clk_div,
};
static const struct meson8b_clk_reset_line {
u32 reg;
u8 bit_idx;
......@@ -837,11 +839,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
/* Populate the base address for CPU clk */
meson8b_cpu_clk.base = clk_base;
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
meson8b_clk_gates[i]->reg = clk_base +
(u32)meson8b_clk_gates[i]->reg;
/* Populate base address for muxes */
for (i = 0; i < ARRAY_SIZE(meson8b_clk_muxes); i++)
meson8b_clk_muxes[i]->reg = clk_base +
......@@ -852,6 +849,10 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
meson8b_clk_dividers[i]->reg = clk_base +
(u32)meson8b_clk_dividers[i]->reg;
/* Populate regmap for the regmap backed clocks */
for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
meson8b_clk_regmaps[i]->map = map;
/*
* register all clks
* CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
......
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