Commit 8151ad57 authored by Michael Chan's avatar Michael Chan Committed by David S. Miller

tg3: Request APE_LOCK_PHY before PHY access

to prevent PHY access conflict with APE firmware.
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 8253947e
...@@ -672,6 +672,12 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum) ...@@ -672,6 +672,12 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
else else
bit = 1 << tp->pci_fn; bit = 1 << tp->pci_fn;
break; break;
case TG3_APE_LOCK_PHY0:
case TG3_APE_LOCK_PHY1:
case TG3_APE_LOCK_PHY2:
case TG3_APE_LOCK_PHY3:
bit = APE_LOCK_REQ_DRIVER;
break;
default: default:
return -EINVAL; return -EINVAL;
} }
...@@ -723,6 +729,12 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum) ...@@ -723,6 +729,12 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum)
else else
bit = 1 << tp->pci_fn; bit = 1 << tp->pci_fn;
break; break;
case TG3_APE_LOCK_PHY0:
case TG3_APE_LOCK_PHY1:
case TG3_APE_LOCK_PHY2:
case TG3_APE_LOCK_PHY3:
bit = APE_LOCK_GRANT_DRIVER;
break;
default: default:
return; return;
} }
...@@ -1052,6 +1064,8 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) ...@@ -1052,6 +1064,8 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
udelay(80); udelay(80);
} }
tg3_ape_lock(tp, tp->phy_ape_lock);
*val = 0x0; *val = 0x0;
frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
...@@ -1086,6 +1100,8 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) ...@@ -1086,6 +1100,8 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
udelay(80); udelay(80);
} }
tg3_ape_unlock(tp, tp->phy_ape_lock);
return ret; return ret;
} }
...@@ -1105,6 +1121,8 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val) ...@@ -1105,6 +1121,8 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
udelay(80); udelay(80);
} }
tg3_ape_lock(tp, tp->phy_ape_lock);
frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
MI_COM_PHY_ADDR_MASK); MI_COM_PHY_ADDR_MASK);
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
...@@ -1135,6 +1153,8 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val) ...@@ -1135,6 +1153,8 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
udelay(80); udelay(80);
} }
tg3_ape_unlock(tp, tp->phy_ape_lock);
return ret; return ret;
} }
...@@ -13648,6 +13668,23 @@ static int __devinit tg3_phy_probe(struct tg3 *tp) ...@@ -13648,6 +13668,23 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
tg3_flag_set(tp, PAUSE_AUTONEG); tg3_flag_set(tp, PAUSE_AUTONEG);
tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
if (tg3_flag(tp, ENABLE_APE)) {
switch (tp->pci_fn) {
case 0:
tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
break;
case 1:
tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
break;
case 2:
tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
break;
case 3:
tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
break;
}
}
if (tg3_flag(tp, USE_PHYLIB)) if (tg3_flag(tp, USE_PHYLIB))
return tg3_phy_init(tp); return tg3_phy_init(tp);
......
...@@ -3107,6 +3107,7 @@ struct tg3 { ...@@ -3107,6 +3107,7 @@ struct tg3 {
int old_link; int old_link;
u8 phy_addr; u8 phy_addr;
u8 phy_ape_lock;
/* PHY info */ /* PHY info */
u32 phy_id; u32 phy_id;
......
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