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Commit 81924ec7 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Bjorn Andersson
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ARM: dts: qcom: use defines for interrupts 

Replace hard-coded interrupt parts (GIC, flags) with standard defines
for readability.  No changes in resulting DTBs.
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231205153317.346109-1-krzysztof.kozlowski@linaro.orgSigned-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent ffb05e91
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Showing with 61 additions and 61 deletions
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
View file @ 81924ec7
...@@ -190,7 +190,7 @@ cpu_crit3: trip1 { ...@@ -190,7 +190,7 @@ cpu_crit3: trip1 {
cpu-pmu { cpu-pmu {
compatible = "qcom,krait-pmu"; compatible = "qcom,krait-pmu";
interrupts = <1 10 0x304>; interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
}; };
clocks { clocks {
...@@ -244,7 +244,7 @@ apps_smsm: apps@0 { ...@@ -244,7 +244,7 @@ apps_smsm: apps@0 {
modem_smsm: modem@1 { modem_smsm: modem@1 {
reg = <1>; reg = <1>;
interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
...@@ -252,7 +252,7 @@ modem_smsm: modem@1 { ...@@ -252,7 +252,7 @@ modem_smsm: modem@1 {
q6_smsm: q6@2 { q6_smsm: q6@2 {
reg = <2>; reg = <2>;
interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
...@@ -260,7 +260,7 @@ q6_smsm: q6@2 { ...@@ -260,7 +260,7 @@ q6_smsm: q6@2 {
wcnss_smsm: wcnss@3 { wcnss_smsm: wcnss@3 {
reg = <3>; reg = <3>;
interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
...@@ -268,7 +268,7 @@ wcnss_smsm: wcnss@3 { ...@@ -268,7 +268,7 @@ wcnss_smsm: wcnss@3 {
dsps_smsm: dsps@4 { dsps_smsm: dsps@4 {
reg = <4>; reg = <4>;
interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
...@@ -299,7 +299,7 @@ tlmm_pinmux: pinctrl@800000 { ...@@ -299,7 +299,7 @@ tlmm_pinmux: pinctrl@800000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&ps_hold>; pinctrl-0 = <&ps_hold>;
...@@ -321,9 +321,9 @@ intc: interrupt-controller@2000000 { ...@@ -321,9 +321,9 @@ intc: interrupt-controller@2000000 {
timer@200a000 { timer@200a000 {
compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer", compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
"qcom,msm-timer"; "qcom,msm-timer";
interrupts = <1 1 0x301>, interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<1 2 0x301>, <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<1 3 0x301>; <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
reg = <0x0200a000 0x100>; reg = <0x0200a000 0x100>;
clock-frequency = <27000000>; clock-frequency = <27000000>;
cpu-offset = <0x80000>; cpu-offset = <0x80000>;
...@@ -411,7 +411,7 @@ gsbi1_serial: serial@12450000 { ...@@ -411,7 +411,7 @@ gsbi1_serial: serial@12450000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x12450000 0x100>, reg = <0x12450000 0x100>,
<0x12400000 0x03>; <0x12400000 0x03>;
interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
clock-names = "core", "iface"; clock-names = "core", "iface";
status = "disabled"; status = "disabled";
...@@ -423,7 +423,7 @@ gsbi1_i2c: i2c@12460000 { ...@@ -423,7 +423,7 @@ gsbi1_i2c: i2c@12460000 {
pinctrl-1 = <&i2c1_pins_sleep>; pinctrl-1 = <&i2c1_pins_sleep>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
reg = <0x12460000 0x1000>; reg = <0x12460000 0x1000>;
interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
clock-names = "core", "iface"; clock-names = "core", "iface";
#address-cells = <1>; #address-cells = <1>;
...@@ -452,7 +452,7 @@ gsbi2_i2c: i2c@124a0000 { ...@@ -452,7 +452,7 @@ gsbi2_i2c: i2c@124a0000 {
pinctrl-0 = <&i2c2_pins>; pinctrl-0 = <&i2c2_pins>;
pinctrl-1 = <&i2c2_pins_sleep>; pinctrl-1 = <&i2c2_pins_sleep>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
clock-names = "core", "iface"; clock-names = "core", "iface";
#address-cells = <1>; #address-cells = <1>;
...@@ -539,7 +539,7 @@ gsbi5_serial: serial@1a240000 { ...@@ -539,7 +539,7 @@ gsbi5_serial: serial@1a240000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x1a240000 0x100>, reg = <0x1a240000 0x100>,
<0x1a200000 0x03>; <0x1a200000 0x03>;
interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface"; clock-names = "core", "iface";
status = "disabled"; status = "disabled";
...@@ -548,7 +548,7 @@ gsbi5_serial: serial@1a240000 { ...@@ -548,7 +548,7 @@ gsbi5_serial: serial@1a240000 {
gsbi5_spi: spi@1a280000 { gsbi5_spi: spi@1a280000 {
compatible = "qcom,spi-qup-v1.1.1"; compatible = "qcom,spi-qup-v1.1.1";
reg = <0x1a280000 0x1000>; reg = <0x1a280000 0x1000>;
interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&spi5_default>; pinctrl-0 = <&spi5_default>;
pinctrl-1 = <&spi5_sleep>; pinctrl-1 = <&spi5_sleep>;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
...@@ -575,7 +575,7 @@ gsbi6_serial: serial@16540000 { ...@@ -575,7 +575,7 @@ gsbi6_serial: serial@16540000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16540000 0x100>, reg = <0x16540000 0x100>,
<0x16500000 0x03>; <0x16500000 0x03>;
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
clock-names = "core", "iface"; clock-names = "core", "iface";
status = "disabled"; status = "disabled";
...@@ -611,7 +611,7 @@ gsbi7_serial: serial@16640000 { ...@@ -611,7 +611,7 @@ gsbi7_serial: serial@16640000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16640000 0x1000>, reg = <0x16640000 0x1000>,
<0x16600000 0x1000>; <0x16600000 0x1000>;
interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
clock-names = "core", "iface"; clock-names = "core", "iface";
status = "disabled"; status = "disabled";
...@@ -908,7 +908,7 @@ sdcc3: mmc@12180000 { ...@@ -908,7 +908,7 @@ sdcc3: mmc@12180000 {
sdcc3bam: dma-controller@12182000 { sdcc3bam: dma-controller@12182000 {
compatible = "qcom,bam-v1.3.0"; compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x8000>; reg = <0x12182000 0x8000>;
interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC3_H_CLK>; clocks = <&gcc SDC3_H_CLK>;
clock-names = "bam_clk"; clock-names = "bam_clk";
#dma-cells = <1>; #dma-cells = <1>;
...@@ -936,7 +936,7 @@ sdcc4: mmc@121c0000 { ...@@ -936,7 +936,7 @@ sdcc4: mmc@121c0000 {
sdcc4bam: dma-controller@121c2000 { sdcc4bam: dma-controller@121c2000 {
compatible = "qcom,bam-v1.3.0"; compatible = "qcom,bam-v1.3.0";
reg = <0x121c2000 0x8000>; reg = <0x121c2000 0x8000>;
interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC4_H_CLK>; clocks = <&gcc SDC4_H_CLK>;
clock-names = "bam_clk"; clock-names = "bam_clk";
#dma-cells = <1>; #dma-cells = <1>;
...@@ -965,7 +965,7 @@ sdcc1: mmc@12400000 { ...@@ -965,7 +965,7 @@ sdcc1: mmc@12400000 {
sdcc1bam: dma-controller@12402000 { sdcc1bam: dma-controller@12402000 {
compatible = "qcom,bam-v1.3.0"; compatible = "qcom,bam-v1.3.0";
reg = <0x12402000 0x8000>; reg = <0x12402000 0x8000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC1_H_CLK>; clocks = <&gcc SDC1_H_CLK>;
clock-names = "bam_clk"; clock-names = "bam_clk";
#dma-cells = <1>; #dma-cells = <1>;
......
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
View file @ 81924ec7
...@@ -162,10 +162,10 @@ scm { ...@@ -162,10 +162,10 @@ scm {
timer { timer {
compatible = "arm,armv7-timer"; compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>, interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 3 0xf08>, <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 4 0xf08>, <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 1 0xf08>; <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <48000000>; clock-frequency = <48000000>;
always-on; always-on;
}; };
......
arch/arm/boot/dts/qcom/qcom-msm8660.dtsi
View file @ 81924ec7
...@@ -47,7 +47,7 @@ memory { ...@@ -47,7 +47,7 @@ memory {
cpu-pmu { cpu-pmu {
compatible = "qcom,scorpion-mp-pmu"; compatible = "qcom,scorpion-mp-pmu";
interrupts = <1 9 0x304>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
}; };
clocks { clocks {
...@@ -89,9 +89,9 @@ intc: interrupt-controller@2080000 { ...@@ -89,9 +89,9 @@ intc: interrupt-controller@2080000 {
timer@2000000 { timer@2000000 {
compatible = "qcom,scss-timer", "qcom,msm-timer"; compatible = "qcom,scss-timer", "qcom,msm-timer";
interrupts = <1 0 0x301>, interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<1 1 0x301>, <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<1 2 0x301>; <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
reg = <0x02000000 0x100>; reg = <0x02000000 0x100>;
clock-frequency = <27000000>, clock-frequency = <27000000>,
<32768>; <32768>;
...@@ -105,7 +105,7 @@ tlmm: pinctrl@800000 { ...@@ -105,7 +105,7 @@ tlmm: pinctrl@800000 {
gpio-controller; gpio-controller;
gpio-ranges = <&tlmm 0 0 173>; gpio-ranges = <&tlmm 0 0 173>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupts = <0 16 0x4>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
...@@ -283,7 +283,7 @@ gsbi12_serial: serial@19c40000 { ...@@ -283,7 +283,7 @@ gsbi12_serial: serial@19c40000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x19c40000 0x1000>, reg = <0x19c40000 0x1000>,
<0x19c00000 0x1000>; <0x19c00000 0x1000>;
interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
clock-names = "core", "iface"; clock-names = "core", "iface";
status = "disabled"; status = "disabled";
...@@ -292,7 +292,7 @@ gsbi12_serial: serial@19c40000 { ...@@ -292,7 +292,7 @@ gsbi12_serial: serial@19c40000 {
gsbi12_i2c: i2c@19c80000 { gsbi12_i2c: i2c@19c80000 {
compatible = "qcom,i2c-qup-v1.1.1"; compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x19c80000 0x1000>; reg = <0x19c80000 0x1000>;
interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
clock-names = "core", "iface"; clock-names = "core", "iface";
#address-cells = <1>; #address-cells = <1>;
......
arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
View file @ 81924ec7
...@@ -31,7 +31,7 @@ sleep_clk: sleep_clk { ...@@ -31,7 +31,7 @@ sleep_clk: sleep_clk {
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <GIC_PPI 9 0xf04>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
CPU0: cpu@0 { CPU0: cpu@0 {
compatible = "qcom,krait"; compatible = "qcom,krait";
...@@ -110,7 +110,7 @@ memory { ...@@ -110,7 +110,7 @@ memory {
pmu { pmu {
compatible = "qcom,krait-pmu"; compatible = "qcom,krait-pmu";
interrupts = <GIC_PPI 7 0xf04>; interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
}; };
rpm: remoteproc { rpm: remoteproc {
...@@ -538,7 +538,7 @@ blsp1_i2c1: i2c@f9923000 { ...@@ -538,7 +538,7 @@ blsp1_i2c1: i2c@f9923000 {
status = "disabled"; status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1"; compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9923000 0x1000>; reg = <0xf9923000 0x1000>;
interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface"; clock-names = "core", "iface";
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
...@@ -566,7 +566,7 @@ blsp1_i2c3: i2c@f9925000 { ...@@ -566,7 +566,7 @@ blsp1_i2c3: i2c@f9925000 {
status = "disabled"; status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1"; compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9925000 0x1000>; reg = <0xf9925000 0x1000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface"; clock-names = "core", "iface";
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
...@@ -666,7 +666,7 @@ blsp2_i2c6: i2c@f9968000 { ...@@ -666,7 +666,7 @@ blsp2_i2c6: i2c@f9968000 {
status = "disabled"; status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1"; compatible = "qcom,i2c-qup-v2.1.1";
reg = <0xf9968000 0x1000>; reg = <0xf9968000 0x1000>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface"; clock-names = "core", "iface";
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
...@@ -2403,10 +2403,10 @@ gpu2_alert0: trip-point0 { ...@@ -2403,10 +2403,10 @@ gpu2_alert0: trip-point0 {
timer { timer {
compatible = "arm,armv7-timer"; compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 2 0xf08>, interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 0xf08>, <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 0xf08>, <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 0xf08>; <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>; clock-frequency = <19200000>;
}; };
}; };
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
View file @ 81924ec7
...@@ -727,57 +727,57 @@ timer@17820000 { ...@@ -727,57 +727,57 @@ timer@17820000 {
frame@17821000 { frame@17821000 {
frame-number = <0>; frame-number = <0>;
interrupts = <GIC_SPI 7 0x4>, interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 0x4>; <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17821000 0x1000>, reg = <0x17821000 0x1000>,
<0x17822000 0x1000>; <0x17822000 0x1000>;
}; };
frame@17823000 { frame@17823000 {
frame-number = <1>; frame-number = <1>;
interrupts = <GIC_SPI 8 0x4>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17823000 0x1000>; reg = <0x17823000 0x1000>;
status = "disabled"; status = "disabled";
}; };
frame@17824000 { frame@17824000 {
frame-number = <2>; frame-number = <2>;
interrupts = <GIC_SPI 9 0x4>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17824000 0x1000>; reg = <0x17824000 0x1000>;
status = "disabled"; status = "disabled";
}; };
frame@17825000 { frame@17825000 {
frame-number = <3>; frame-number = <3>;
interrupts = <GIC_SPI 10 0x4>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17825000 0x1000>; reg = <0x17825000 0x1000>;
status = "disabled"; status = "disabled";
}; };
frame@17826000 { frame@17826000 {
frame-number = <4>; frame-number = <4>;
interrupts = <GIC_SPI 11 0x4>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17826000 0x1000>; reg = <0x17826000 0x1000>;
status = "disabled"; status = "disabled";
}; };
frame@17827000 { frame@17827000 {
frame-number = <5>; frame-number = <5>;
interrupts = <GIC_SPI 12 0x4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17827000 0x1000>; reg = <0x17827000 0x1000>;
status = "disabled"; status = "disabled";
}; };
frame@17828000 { frame@17828000 {
frame-number = <6>; frame-number = <6>;
interrupts = <GIC_SPI 13 0x4>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17828000 0x1000>; reg = <0x17828000 0x1000>;
status = "disabled"; status = "disabled";
}; };
frame@17829000 { frame@17829000 {
frame-number = <7>; frame-number = <7>;
interrupts = <GIC_SPI 14 0x4>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17829000 0x1000>; reg = <0x17829000 0x1000>;
status = "disabled"; status = "disabled";
}; };
......
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
View file @ 81924ec7
...@@ -667,57 +667,57 @@ timer@17820000 { ...@@ -667,57 +667,57 @@ timer@17820000 {
frame@17821000 { frame@17821000 {
frame-number = <0>; frame-number = <0>;
interrupts = <GIC_SPI 7 0x4>, interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 0x4>; <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17821000 0x1000>, reg = <0x17821000 0x1000>,
<0x17822000 0x1000>; <0x17822000 0x1000>;
}; };
frame@17823000 { frame@17823000 {
frame-number = <1>; frame-number = <1>;
interrupts = <GIC_SPI 8 0x4>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17823000 0x1000>; reg = <0x17823000 0x1000>;
status = "disabled"; status = "disabled";
}; };
frame@17824000 { frame@17824000 {
frame-number = <2>; frame-number = <2>;
interrupts = <GIC_SPI 9 0x4>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17824000 0x1000>; reg = <0x17824000 0x1000>;
status = "disabled"; status = "disabled";
}; };
frame@17825000 { frame@17825000 {
frame-number = <3>; frame-number = <3>;
interrupts = <GIC_SPI 10 0x4>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17825000 0x1000>; reg = <0x17825000 0x1000>;
status = "disabled"; status = "disabled";
}; };
frame@17826000 { frame@17826000 {
frame-number = <4>; frame-number = <4>;
interrupts = <GIC_SPI 11 0x4>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17826000 0x1000>; reg = <0x17826000 0x1000>;
status = "disabled"; status = "disabled";
}; };
frame@17827000 { frame@17827000 {
frame-number = <5>; frame-number = <5>;
interrupts = <GIC_SPI 12 0x4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17827000 0x1000>; reg = <0x17827000 0x1000>;
status = "disabled"; status = "disabled";
}; };
frame@17828000 { frame@17828000 {
frame-number = <6>; frame-number = <6>;
interrupts = <GIC_SPI 13 0x4>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17828000 0x1000>; reg = <0x17828000 0x1000>;
status = "disabled"; status = "disabled";
}; };
frame@17829000 { frame@17829000 {
frame-number = <7>; frame-number = <7>;
interrupts = <GIC_SPI 14 0x4>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17829000 0x1000>; reg = <0x17829000 0x1000>;
status = "disabled"; status = "disabled";
}; };
...@@ -804,10 +804,10 @@ apps_bcm_voter: bcm-voter { ...@@ -804,10 +804,10 @@ apps_bcm_voter: bcm-voter {
timer { timer {
compatible = "arm,armv7-timer"; compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>, interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 12 0xf08>, <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 10 0xf08>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 11 0xf08>; <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>; clock-frequency = <19200000>;
}; };
}; };
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