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Commit 83691d6f authored by David S. Miller's avatar David S. Miller
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Merge branch 'net-at803x-cleanups' 

Christian Marangi says:

====================
net: phy: at803x: cleanup

The intention of this big series is to try to cleanup the big
at803x PHY driver.

It currently have 3 different family of PHY in it. at803x, qca83xx
and qca808x.

The current codebase required lots of cleanup and reworking to
make the split possible as currently there is a greater use of
adding special function matching the phy_id.

This has been reworked to make the function actually generic
and make the change only in more specific one. The result
is the addition of micro additional function but that is for good
as it massively simplify splitting the driver later.

Consider that this is all in preparation for the addition of
qca807x PHY driver that will also uso some of the functions of
at803x.

Subsequent series will come with the actual PHY split and other
required cleanup. This is only to start the process with minor
changes.

Changes v4:
- Improve at8031_probe function
Changes v3:
- Add Reviewed-by tag from Andrew
- Split patch 10 (at8031 rename) to rename and move
Changes v2:
- Drop split part due to series too big
- Split changes even more
- Fix problem pointed out by Russell (flawed reworked function logic)
- Add Reviewed-by tag from Andrew
- Minor rework to prevent further code duplication for cdt
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 4f7aa122 ef9df47b
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Showing with 426 additions and 349 deletions
drivers/net/phy/at803x.c
View file @ 83691d6f
......@@ -295,7 +295,7 @@ struct at803x_hw_stat {
enum stat_access_type access_type;
};
static struct at803x_hw_stat at803x_hw_stats[] = {
static struct at803x_hw_stat qca83xx_hw_stats[] = {
{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
{ "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
......@@ -311,7 +311,7 @@ struct at803x_priv {
bool is_1000basex;
struct regulator_dev *vddio_rdev;
struct regulator_dev *vddh_rdev;
u64 stats[ARRAY_SIZE(at803x_hw_stats)];
u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
};
struct at803x_context {
......@@ -466,27 +466,11 @@ static int at803x_set_wol(struct phy_device *phydev,
phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
/* Enable WOL function for 1588 */
if (phydev->drv->phy_id == ATH8031_PHY_ID) {
ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
AT803X_PHY_MMD3_WOL_CTRL,
0, AT803X_WOL_EN);
if (ret)
return ret;
}
/* Enable WOL interrupt */
ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
if (ret)
return ret;
} else {
/* Disable WoL function for 1588 */
if (phydev->drv->phy_id == ATH8031_PHY_ID) {
ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
AT803X_PHY_MMD3_WOL_CTRL,
AT803X_WOL_EN, 0);
if (ret)
return ret;
}
/* Disable WOL interrupt */
ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
if (ret)
......@@ -529,24 +513,24 @@ static void at803x_get_wol(struct phy_device *phydev,
wol->wolopts |= WAKE_MAGIC;
}
static int at803x_get_sset_count(struct phy_device *phydev)
static int qca83xx_get_sset_count(struct phy_device *phydev)
{
return ARRAY_SIZE(at803x_hw_stats);
return ARRAY_SIZE(qca83xx_hw_stats);
}
static void at803x_get_strings(struct phy_device *phydev, u8 *data)
static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)
{
int i;
for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) {
for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) {
strscpy(data + i * ETH_GSTRING_LEN,
at803x_hw_stats[i].string, ETH_GSTRING_LEN);
qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);
}
}
static u64 at803x_get_stat(struct phy_device *phydev, int i)
static u64 qca83xx_get_stat(struct phy_device *phydev, int i)
{
struct at803x_hw_stat stat = at803x_hw_stats[i];
struct at803x_hw_stat stat = qca83xx_hw_stats[i];
struct at803x_priv *priv = phydev->priv;
int val;
u64 ret;
......@@ -567,13 +551,13 @@ static u64 at803x_get_stat(struct phy_device *phydev, int i)
return ret;
}
static void at803x_get_stats(struct phy_device *phydev,
struct ethtool_stats *stats, u64 *data)
static void qca83xx_get_stats(struct phy_device *phydev,
struct ethtool_stats *stats, u64 *data)
{
int i;
for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++)
data[i] = at803x_get_stat(phydev, i);
for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++)
data[i] = qca83xx_get_stat(phydev, i);
}
static int at803x_suspend(struct phy_device *phydev)
......@@ -599,139 +583,6 @@ static int at803x_resume(struct phy_device *phydev)
return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
}
static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
unsigned int selector)
{
struct phy_device *phydev = rdev_get_drvdata(rdev);
if (selector)
return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
0, AT803X_DEBUG_RGMII_1V8);
else
return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
AT803X_DEBUG_RGMII_1V8, 0);
}
static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
{
struct phy_device *phydev = rdev_get_drvdata(rdev);
int val;
val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
if (val < 0)
return val;
return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
}
static const struct regulator_ops vddio_regulator_ops = {
.list_voltage = regulator_list_voltage_table,
.set_voltage_sel = at803x_rgmii_reg_set_voltage_sel,
.get_voltage_sel = at803x_rgmii_reg_get_voltage_sel,
};
static const unsigned int vddio_voltage_table[] = {
1500000,
1800000,
};
static const struct regulator_desc vddio_desc = {
.name = "vddio",
.of_match = of_match_ptr("vddio-regulator"),
.n_voltages = ARRAY_SIZE(vddio_voltage_table),
.volt_table = vddio_voltage_table,
.ops = &vddio_regulator_ops,
.type = REGULATOR_VOLTAGE,
.owner = THIS_MODULE,
};
static const struct regulator_ops vddh_regulator_ops = {
};
static const struct regulator_desc vddh_desc = {
.name = "vddh",
.of_match = of_match_ptr("vddh-regulator"),
.n_voltages = 1,
.fixed_uV = 2500000,
.ops = &vddh_regulator_ops,
.type = REGULATOR_VOLTAGE,
.owner = THIS_MODULE,
};
static int at8031_register_regulators(struct phy_device *phydev)
{
struct at803x_priv *priv = phydev->priv;
struct device *dev = &phydev->mdio.dev;
struct regulator_config config = { };
config.dev = dev;
config.driver_data = phydev;
priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
if (IS_ERR(priv->vddio_rdev)) {
phydev_err(phydev, "failed to register VDDIO regulator\n");
return PTR_ERR(priv->vddio_rdev);
}
priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
if (IS_ERR(priv->vddh_rdev)) {
phydev_err(phydev, "failed to register VDDH regulator\n");
return PTR_ERR(priv->vddh_rdev);
}
return 0;
}
static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
{
struct phy_device *phydev = upstream;
__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
__ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
DECLARE_PHY_INTERFACE_MASK(interfaces);
phy_interface_t iface;
linkmode_zero(phy_support);
phylink_set(phy_support, 1000baseX_Full);
phylink_set(phy_support, 1000baseT_Full);
phylink_set(phy_support, Autoneg);
phylink_set(phy_support, Pause);
phylink_set(phy_support, Asym_Pause);
linkmode_zero(sfp_support);
sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces);
/* Some modules support 10G modes as well as others we support.
* Mask out non-supported modes so the correct interface is picked.
*/
linkmode_and(sfp_support, phy_support, sfp_support);
if (linkmode_empty(sfp_support)) {
dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
return -EINVAL;
}
iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
/* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
* interface for use with SFP modules.
* However, some copper modules detected as having a preferred SGMII
* interface do default to and function in 1000Base-X mode, so just
* print a warning and allow such modules, as they may have some chance
* of working.
*/
if (iface == PHY_INTERFACE_MODE_SGMII)
dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
else if (iface != PHY_INTERFACE_MODE_1000BASEX)
return -EINVAL;
return 0;
}
static const struct sfp_upstream_ops at803x_sfp_ops = {
.attach = phy_sfp_attach,
.detach = phy_sfp_detach,
.module_insert = at803x_sfp_insert,
};
static int at803x_parse_dt(struct phy_device *phydev)
{
struct device_node *node = phydev->mdio.dev.of_node;
......@@ -787,23 +638,6 @@ static int at803x_parse_dt(struct phy_device *phydev)
priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
/* Fixup for the AR8030/AR8035. This chip has another mask and
* doesn't support the DSP reference. Eg. the lowest bit of the
* mask. The upper two bits select the same frequencies. Mask
* the lowest bit here.
*
* Warning:
* There was no datasheet for the AR8030 available so this is
* just a guess. But the AR8035 is listed as pin compatible
* to the AR8030 so there might be a good chance it works on
* the AR8030 too.
*/
if (phydev->drv->phy_id == ATH8030_PHY_ID ||
phydev->drv->phy_id == ATH8035_PHY_ID) {
priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
}
}
ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
......@@ -825,30 +659,6 @@ static int at803x_parse_dt(struct phy_device *phydev)
}
}
/* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
* options.
*/
if (phydev->drv->phy_id == ATH8031_PHY_ID) {
if (of_property_read_bool(node, "qca,keep-pll-enabled"))
priv->flags |= AT803X_KEEP_PLL_ENABLED;
ret = at8031_register_regulators(phydev);
if (ret < 0)
return ret;
ret = devm_regulator_get_enable_optional(&phydev->mdio.dev,
"vddio");
if (ret) {
phydev_err(phydev, "failed to get VDDIO regulator\n");
return ret;
}
/* Only AR8031/8033 support 1000Base-X for SFP modules */
ret = phy_sfp_probe(phydev, &at803x_sfp_ops);
if (ret < 0)
return ret;
}
return 0;
}
......@@ -868,35 +678,6 @@ static int at803x_probe(struct phy_device *phydev)
if (ret)
return ret;
if (phydev->drv->phy_id == ATH8031_PHY_ID) {
int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
int mode_cfg;
if (ccr < 0)
return ccr;
mode_cfg = ccr & AT803X_MODE_CFG_MASK;
switch (mode_cfg) {
case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
priv->is_1000basex = true;
fallthrough;
case AT803X_MODE_CFG_FX100_RGMII_50OHM:
case AT803X_MODE_CFG_FX100_RGMII_75OHM:
priv->is_fiber = true;
break;
}
/* Disable WoL in 1588 register which is enabled
* by default
*/
ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
AT803X_PHY_MMD3_WOL_CTRL,
AT803X_WOL_EN, 0);
if (ret)
return ret;
}
return 0;
}
......@@ -1004,27 +785,8 @@ static int at803x_hibernation_mode_config(struct phy_device *phydev)
static int at803x_config_init(struct phy_device *phydev)
{
struct at803x_priv *priv = phydev->priv;
int ret;
if (phydev->drv->phy_id == ATH8031_PHY_ID) {
/* Some bootloaders leave the fiber page selected.
* Switch to the appropriate page (fiber or copper), as otherwise we
* read the PHY capabilities from the wrong page.
*/
phy_lock_mdio_bus(phydev);
ret = at803x_write_page(phydev,
priv->is_fiber ? AT803X_PAGE_FIBER :
AT803X_PAGE_COPPER);
phy_unlock_mdio_bus(phydev);
if (ret)
return ret;
ret = at8031_pll_config(phydev);
if (ret < 0)
return ret;
}
/* The RX and TX delay default is:
* after HW reset: RX delay enabled and TX delay disabled
* after SW reset: RX delay enabled, while TX delay retains the
......@@ -1078,7 +840,6 @@ static int at803x_ack_interrupt(struct phy_device *phydev)
static int at803x_config_intr(struct phy_device *phydev)
{
struct at803x_priv *priv = phydev->priv;
int err;
int value;
......@@ -1095,10 +856,6 @@ static int at803x_config_intr(struct phy_device *phydev)
value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
value |= AT803X_INTR_ENABLE_LINK_FAIL;
value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
if (priv->is_fiber) {
value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
}
err = phy_write(phydev, AT803X_INTR_ENABLE, value);
} else {
......@@ -1465,31 +1222,16 @@ static int at803x_cdt_fault_length(u16 status)
return (dt * 824) / 10;
}
static int at803x_cdt_start(struct phy_device *phydev, int pair)
static int at803x_cdt_start(struct phy_device *phydev,
u32 cdt_start)
{
u16 cdt;
/* qca8081 takes the different bit 15 to enable CDT test */
if (phydev->drv->phy_id == QCA8081_PHY_ID)
cdt = QCA808X_CDT_ENABLE_TEST |
QCA808X_CDT_LENGTH_UNIT |
QCA808X_CDT_INTER_CHECK_DIS;
else
cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
AT803X_CDT_ENABLE_TEST;
return phy_write(phydev, AT803X_CDT, cdt);
return phy_write(phydev, AT803X_CDT, cdt_start);
}
static int at803x_cdt_wait_for_completion(struct phy_device *phydev)
static int at803x_cdt_wait_for_completion(struct phy_device *phydev,
u32 cdt_en)
{
int val, ret;
u16 cdt_en;
if (phydev->drv->phy_id == QCA8081_PHY_ID)
cdt_en = QCA808X_CDT_ENABLE_TEST;
else
cdt_en = AT803X_CDT_ENABLE_TEST;
/* One test run takes about 25ms */
ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
......@@ -1509,11 +1251,13 @@ static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
};
int ret, val;
ret = at803x_cdt_start(phydev, pair);
val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
AT803X_CDT_ENABLE_TEST;
ret = at803x_cdt_start(phydev, val);
if (ret)
return ret;
ret = at803x_cdt_wait_for_completion(phydev);
ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);
if (ret)
return ret;
......@@ -1535,19 +1279,11 @@ static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
}
static int at803x_cable_test_get_status(struct phy_device *phydev,
bool *finished)
bool *finished, unsigned long pair_mask)
{
unsigned long pair_mask;
int retries = 20;
int pair, ret;
if (phydev->phy_id == ATH9331_PHY_ID ||
phydev->phy_id == ATH8032_PHY_ID ||
phydev->phy_id == QCA9561_PHY_ID)
pair_mask = 0x3;
else
pair_mask = 0xf;
*finished = false;
/* According to the datasheet the CDT can be performed when
......@@ -1574,7 +1310,7 @@ static int at803x_cable_test_get_status(struct phy_device *phydev,
return 0;
}
static int at803x_cable_test_start(struct phy_device *phydev)
static void at803x_cable_test_autoneg(struct phy_device *phydev)
{
/* Enable auto-negotiation, but advertise no capabilities, no link
* will be established. A restart of the auto-negotiation is not
......@@ -1582,15 +1318,347 @@ static int at803x_cable_test_start(struct phy_device *phydev)
*/
phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
if (phydev->phy_id != ATH9331_PHY_ID &&
phydev->phy_id != ATH8032_PHY_ID &&
phydev->phy_id != QCA9561_PHY_ID)
phy_write(phydev, MII_CTRL1000, 0);
}
static int at803x_cable_test_start(struct phy_device *phydev)
{
at803x_cable_test_autoneg(phydev);
/* we do all the (time consuming) work later */
return 0;
}
static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
unsigned int selector)
{
struct phy_device *phydev = rdev_get_drvdata(rdev);
if (selector)
return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
0, AT803X_DEBUG_RGMII_1V8);
else
return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
AT803X_DEBUG_RGMII_1V8, 0);
}
static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
{
struct phy_device *phydev = rdev_get_drvdata(rdev);
int val;
val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
if (val < 0)
return val;
return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
}
static const struct regulator_ops vddio_regulator_ops = {
.list_voltage = regulator_list_voltage_table,
.set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,
.get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,
};
static const unsigned int vddio_voltage_table[] = {
1500000,
1800000,
};
static const struct regulator_desc vddio_desc = {
.name = "vddio",
.of_match = of_match_ptr("vddio-regulator"),
.n_voltages = ARRAY_SIZE(vddio_voltage_table),
.volt_table = vddio_voltage_table,
.ops = &vddio_regulator_ops,
.type = REGULATOR_VOLTAGE,
.owner = THIS_MODULE,
};
static const struct regulator_ops vddh_regulator_ops = {
};
static const struct regulator_desc vddh_desc = {
.name = "vddh",
.of_match = of_match_ptr("vddh-regulator"),
.n_voltages = 1,
.fixed_uV = 2500000,
.ops = &vddh_regulator_ops,
.type = REGULATOR_VOLTAGE,
.owner = THIS_MODULE,
};
static int at8031_register_regulators(struct phy_device *phydev)
{
struct at803x_priv *priv = phydev->priv;
struct device *dev = &phydev->mdio.dev;
struct regulator_config config = { };
config.dev = dev;
config.driver_data = phydev;
priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
if (IS_ERR(priv->vddio_rdev)) {
phydev_err(phydev, "failed to register VDDIO regulator\n");
return PTR_ERR(priv->vddio_rdev);
}
priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
if (IS_ERR(priv->vddh_rdev)) {
phydev_err(phydev, "failed to register VDDH regulator\n");
return PTR_ERR(priv->vddh_rdev);
}
return 0;
}
static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
{
struct phy_device *phydev = upstream;
__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
__ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
DECLARE_PHY_INTERFACE_MASK(interfaces);
phy_interface_t iface;
linkmode_zero(phy_support);
phylink_set(phy_support, 1000baseX_Full);
phylink_set(phy_support, 1000baseT_Full);
phylink_set(phy_support, Autoneg);
phylink_set(phy_support, Pause);
phylink_set(phy_support, Asym_Pause);
linkmode_zero(sfp_support);
sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces);
/* Some modules support 10G modes as well as others we support.
* Mask out non-supported modes so the correct interface is picked.
*/
linkmode_and(sfp_support, phy_support, sfp_support);
if (linkmode_empty(sfp_support)) {
dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
return -EINVAL;
}
iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
/* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
* interface for use with SFP modules.
* However, some copper modules detected as having a preferred SGMII
* interface do default to and function in 1000Base-X mode, so just
* print a warning and allow such modules, as they may have some chance
* of working.
*/
if (iface == PHY_INTERFACE_MODE_SGMII)
dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
else if (iface != PHY_INTERFACE_MODE_1000BASEX)
return -EINVAL;
return 0;
}
static const struct sfp_upstream_ops at8031_sfp_ops = {
.attach = phy_sfp_attach,
.detach = phy_sfp_detach,
.module_insert = at8031_sfp_insert,
};
static int at8031_parse_dt(struct phy_device *phydev)
{
struct device_node *node = phydev->mdio.dev.of_node;
struct at803x_priv *priv = phydev->priv;
int ret;
if (of_property_read_bool(node, "qca,keep-pll-enabled"))
priv->flags |= AT803X_KEEP_PLL_ENABLED;
ret = at8031_register_regulators(phydev);
if (ret < 0)
return ret;
ret = devm_regulator_get_enable_optional(&phydev->mdio.dev,
"vddio");
if (ret) {
phydev_err(phydev, "failed to get VDDIO regulator\n");
return ret;
}
/* Only AR8031/8033 support 1000Base-X for SFP modules */
return phy_sfp_probe(phydev, &at8031_sfp_ops);
}
static int at8031_probe(struct phy_device *phydev)
{
struct at803x_priv *priv = phydev->priv;
int mode_cfg;
int ccr;
int ret;
ret = at803x_probe(phydev);
if (ret)
return ret;
/* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
* options.
*/
ret = at8031_parse_dt(phydev);
if (ret)
return ret;
ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
if (ccr < 0)
return ccr;
mode_cfg = ccr & AT803X_MODE_CFG_MASK;
switch (mode_cfg) {
case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
priv->is_1000basex = true;
fallthrough;
case AT803X_MODE_CFG_FX100_RGMII_50OHM:
case AT803X_MODE_CFG_FX100_RGMII_75OHM:
priv->is_fiber = true;
break;
}
/* Disable WoL in 1588 register which is enabled
* by default
*/
return phy_modify_mmd(phydev, MDIO_MMD_PCS,
AT803X_PHY_MMD3_WOL_CTRL,
AT803X_WOL_EN, 0);
}
static int at8031_config_init(struct phy_device *phydev)
{
struct at803x_priv *priv = phydev->priv;
int ret;
/* Some bootloaders leave the fiber page selected.
* Switch to the appropriate page (fiber or copper), as otherwise we
* read the PHY capabilities from the wrong page.
*/
phy_lock_mdio_bus(phydev);
ret = at803x_write_page(phydev,
priv->is_fiber ? AT803X_PAGE_FIBER :
AT803X_PAGE_COPPER);
phy_unlock_mdio_bus(phydev);
if (ret)
return ret;
ret = at8031_pll_config(phydev);
if (ret < 0)
return ret;
return at803x_config_init(phydev);
}
static int at8031_set_wol(struct phy_device *phydev,
struct ethtool_wolinfo *wol)
{
int ret;
/* First setup MAC address and enable WOL interrupt */
ret = at803x_set_wol(phydev, wol);
if (ret)
return ret;
if (wol->wolopts & WAKE_MAGIC)
/* Enable WOL function for 1588 */
ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
AT803X_PHY_MMD3_WOL_CTRL,
0, AT803X_WOL_EN);
else
/* Disable WoL function for 1588 */
ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
AT803X_PHY_MMD3_WOL_CTRL,
AT803X_WOL_EN, 0);
return ret;
}
static int at8031_config_intr(struct phy_device *phydev)
{
struct at803x_priv *priv = phydev->priv;
int err, value = 0;
if (phydev->interrupts == PHY_INTERRUPT_ENABLED &&
priv->is_fiber) {
/* Clear any pending interrupts */
err = at803x_ack_interrupt(phydev);
if (err)
return err;
value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value);
if (err)
return err;
}
return at803x_config_intr(phydev);
}
/* AR8031 and AR8035 share the same cable test get status reg */
static int at8031_cable_test_get_status(struct phy_device *phydev,
bool *finished)
{
return at803x_cable_test_get_status(phydev, finished, 0xf);
}
/* AR8031 and AR8035 share the same cable test start logic */
static int at8031_cable_test_start(struct phy_device *phydev)
{
at803x_cable_test_autoneg(phydev);
phy_write(phydev, MII_CTRL1000, 0);
/* we do all the (time consuming) work later */
return 0;
}
/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */
static int at8032_cable_test_get_status(struct phy_device *phydev,
bool *finished)
{
return at803x_cable_test_get_status(phydev, finished, 0x3);
}
static int at8035_parse_dt(struct phy_device *phydev)
{
struct at803x_priv *priv = phydev->priv;
/* Mask is set by the generic at803x_parse_dt
* if property is set. Assume property is set
* with the mask not zero.
*/
if (priv->clk_25m_mask) {
/* Fixup for the AR8030/AR8035. This chip has another mask and
* doesn't support the DSP reference. Eg. the lowest bit of the
* mask. The upper two bits select the same frequencies. Mask
* the lowest bit here.
*
* Warning:
* There was no datasheet for the AR8030 available so this is
* just a guess. But the AR8035 is listed as pin compatible
* to the AR8030 so there might be a good chance it works on
* the AR8030 too.
*/
priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
}
return 0;
}
/* AR8030 and AR8035 shared the same special mask for clk_25m */
static int at8035_probe(struct phy_device *phydev)
{
int ret;
ret = at803x_probe(phydev);
if (ret)
return ret;
return at8035_parse_dt(phydev);
}
static int qca83xx_config_init(struct phy_device *phydev)
{
u8 switch_revision;
......@@ -1616,27 +1684,26 @@ static int qca83xx_config_init(struct phy_device *phydev)
break;
}
/* Following original QCA sourcecode set port to prefer master */
phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
return 0;
}
static int qca8327_config_init(struct phy_device *phydev)
{
/* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
* Disable on init and enable only with 100m speed following
* qca original source code.
*/
if (phydev->drv->phy_id == QCA8327_A_PHY_ID ||
phydev->drv->phy_id == QCA8327_B_PHY_ID)
at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
QCA8327_DEBUG_MANU_CTRL_EN, 0);
at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
QCA8327_DEBUG_MANU_CTRL_EN, 0);
/* Following original QCA sourcecode set port to prefer master */
phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
return 0;
return qca83xx_config_init(phydev);
}
static void qca83xx_link_change_notify(struct phy_device *phydev)
{
/* QCA8337 doesn't require DAC Amplitude adjustement */
if (phydev->drv->phy_id == QCA8337_PHY_ID)
return;
/* Set DAC Amplitude adjustment to +6% for 100m on link running */
if (phydev->state == PHY_RUNNING) {
if (phydev->speed == SPEED_100)
......@@ -1679,19 +1746,6 @@ static int qca83xx_resume(struct phy_device *phydev)
static int qca83xx_suspend(struct phy_device *phydev)
{
u16 mask = 0;
/* Only QCA8337 support actual suspend.
* QCA8327 cause port unreliability when phy suspend
* is set.
*/
if (phydev->drv->phy_id == QCA8337_PHY_ID) {
genphy_suspend(phydev);
} else {
mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
phy_modify(phydev, MII_BMCR, mask, 0);
}
at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
AT803X_DEBUG_GATE_CLK_IN1000, 0);
......@@ -1702,6 +1756,27 @@ static int qca83xx_suspend(struct phy_device *phydev)
return 0;
}
static int qca8337_suspend(struct phy_device *phydev)
{
/* Only QCA8337 support actual suspend. */
genphy_suspend(phydev);
return qca83xx_suspend(phydev);
}
static int qca8327_suspend(struct phy_device *phydev)
{
u16 mask = 0;
/* QCA8327 cause port unreliability when phy suspend
* is set.
*/
mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
phy_modify(phydev, MII_BMCR, mask, 0);
return qca83xx_suspend(phydev);
}
static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
{
int ret;
......@@ -1968,11 +2043,14 @@ static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finish
*finished = false;
ret = at803x_cdt_start(phydev, 0);
val = QCA808X_CDT_ENABLE_TEST |
QCA808X_CDT_LENGTH_UNIT |
QCA808X_CDT_INTER_CHECK_DIS;
ret = at803x_cdt_start(phydev, val);
if (ret)
return ret;
ret = at803x_cdt_wait_for_completion(phydev);
ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
if (ret)
return ret;
......@@ -2056,7 +2134,7 @@ static struct phy_driver at803x_driver[] = {
PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
.name = "Qualcomm Atheros AR8035",
.flags = PHY_POLL_CABLE_TEST,
.probe = at803x_probe,
.probe = at8035_probe,
.config_aneg = at803x_config_aneg,
.config_init = at803x_config_init,
.soft_reset = genphy_soft_reset,
......@@ -2070,14 +2148,14 @@ static struct phy_driver at803x_driver[] = {
.handle_interrupt = at803x_handle_interrupt,
.get_tunable = at803x_get_tunable,
.set_tunable = at803x_set_tunable,
.cable_test_start = at803x_cable_test_start,
.cable_test_get_status = at803x_cable_test_get_status,
.cable_test_start = at8031_cable_test_start,
.cable_test_get_status = at8031_cable_test_get_status,
}, {
/* Qualcomm Atheros AR8030 */
.phy_id = ATH8030_PHY_ID,
.name = "Qualcomm Atheros AR8030",
.phy_id_mask = AT8030_PHY_ID_MASK,
.probe = at803x_probe,
.probe = at8035_probe,
.config_init = at803x_config_init,
.link_change_notify = at803x_link_change_notify,
.set_wol = at803x_set_wol,
......@@ -2092,11 +2170,11 @@ static struct phy_driver at803x_driver[] = {
PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
.name = "Qualcomm Atheros AR8031/AR8033",
.flags = PHY_POLL_CABLE_TEST,
.probe = at803x_probe,
.config_init = at803x_config_init,
.probe = at8031_probe,
.config_init = at8031_config_init,
.config_aneg = at803x_config_aneg,
.soft_reset = genphy_soft_reset,
.set_wol = at803x_set_wol,
.set_wol = at8031_set_wol,
.get_wol = at803x_get_wol,
.suspend = at803x_suspend,
.resume = at803x_resume,
......@@ -2104,12 +2182,12 @@ static struct phy_driver at803x_driver[] = {
.write_page = at803x_write_page,
.get_features = at803x_get_features,
.read_status = at803x_read_status,
.config_intr = &at803x_config_intr,
.config_intr = at8031_config_intr,
.handle_interrupt = at803x_handle_interrupt,
.get_tunable = at803x_get_tunable,
.set_tunable = at803x_set_tunable,
.cable_test_start = at803x_cable_test_start,
.cable_test_get_status = at803x_cable_test_get_status,
.cable_test_start = at8031_cable_test_start,
.cable_test_get_status = at8031_cable_test_get_status,
}, {
/* Qualcomm Atheros AR8032 */
PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
......@@ -2124,7 +2202,7 @@ static struct phy_driver at803x_driver[] = {
.config_intr = at803x_config_intr,
.handle_interrupt = at803x_handle_interrupt,
.cable_test_start = at803x_cable_test_start,
.cable_test_get_status = at803x_cable_test_get_status,
.cable_test_get_status = at8032_cable_test_get_status,
}, {
/* ATHEROS AR9331 */
PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
......@@ -2134,10 +2212,10 @@ static struct phy_driver at803x_driver[] = {
.resume = at803x_resume,
.flags = PHY_POLL_CABLE_TEST,
/* PHY_BASIC_FEATURES */
.config_intr = &at803x_config_intr,
.config_intr = at803x_config_intr,
.handle_interrupt = at803x_handle_interrupt,
.cable_test_start = at803x_cable_test_start,
.cable_test_get_status = at803x_cable_test_get_status,
.cable_test_get_status = at8032_cable_test_get_status,
.read_status = at803x_read_status,
.soft_reset = genphy_soft_reset,
.config_aneg = at803x_config_aneg,
......@@ -2150,10 +2228,10 @@ static struct phy_driver at803x_driver[] = {
.resume = at803x_resume,
.flags = PHY_POLL_CABLE_TEST,
/* PHY_BASIC_FEATURES */
.config_intr = &at803x_config_intr,
.config_intr = at803x_config_intr,
.handle_interrupt = at803x_handle_interrupt,
.cable_test_start = at803x_cable_test_start,
.cable_test_get_status = at803x_cable_test_get_status,
.cable_test_get_status = at8032_cable_test_get_status,
.read_status = at803x_read_status,
.soft_reset = genphy_soft_reset,
.config_aneg = at803x_config_aneg,
......@@ -2163,15 +2241,14 @@ static struct phy_driver at803x_driver[] = {
.phy_id_mask = QCA8K_PHY_ID_MASK,
.name = "Qualcomm Atheros 8337 internal PHY",
/* PHY_GBIT_FEATURES */
.link_change_notify = qca83xx_link_change_notify,
.probe = at803x_probe,
.flags = PHY_IS_INTERNAL,
.config_init = qca83xx_config_init,
.soft_reset = genphy_soft_reset,
.get_sset_count = at803x_get_sset_count,
.get_strings = at803x_get_strings,
.get_stats = at803x_get_stats,
.suspend = qca83xx_suspend,
.get_sset_count = qca83xx_get_sset_count,
.get_strings = qca83xx_get_strings,
.get_stats = qca83xx_get_stats,
.suspend = qca8337_suspend,
.resume = qca83xx_resume,
}, {
/* QCA8327-A from switch QCA8327-AL1A */
......@@ -2182,12 +2259,12 @@ static struct phy_driver at803x_driver[] = {
.link_change_notify = qca83xx_link_change_notify,
.probe = at803x_probe,
.flags = PHY_IS_INTERNAL,
.config_init = qca83xx_config_init,
.config_init = qca8327_config_init,
.soft_reset = genphy_soft_reset,
.get_sset_count = at803x_get_sset_count,
.get_strings = at803x_get_strings,
.get_stats = at803x_get_stats,
.suspend = qca83xx_suspend,
.get_sset_count = qca83xx_get_sset_count,
.get_strings = qca83xx_get_strings,
.get_stats = qca83xx_get_stats,
.suspend = qca8327_suspend,
.resume = qca83xx_resume,
}, {
/* QCA8327-B from switch QCA8327-BL1A */
......@@ -2198,12 +2275,12 @@ static struct phy_driver at803x_driver[] = {
.link_change_notify = qca83xx_link_change_notify,
.probe = at803x_probe,
.flags = PHY_IS_INTERNAL,
.config_init = qca83xx_config_init,
.config_init = qca8327_config_init,
.soft_reset = genphy_soft_reset,
.get_sset_count = at803x_get_sset_count,
.get_strings = at803x_get_strings,
.get_stats = at803x_get_stats,
.suspend = qca83xx_suspend,
.get_sset_count = qca83xx_get_sset_count,
.get_strings = qca83xx_get_strings,
.get_stats = qca83xx_get_stats,
.suspend = qca8327_suspend,
.resume = qca83xx_resume,
}, {
/* Qualcomm QCA8081 */
......
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