Commit 83cd8397 authored by Christian König's avatar Christian König Committed by Alex Deucher

drm/amdgpu: rework shadow handling during PD clear v3

This way we only deal with the real BO in here.

v2: use a do { ... } while loop instead
v3: fix NULL pointer in v2
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent db65e887
...@@ -788,16 +788,29 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, ...@@ -788,16 +788,29 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
if (r) if (r)
goto error; return r;
r = amdgpu_ttm_alloc_gart(&bo->tbo); r = amdgpu_ttm_alloc_gart(&bo->tbo);
if (r) if (r)
return r; return r;
if (bo->shadow) {
r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement,
&ctx);
if (r)
return r;
r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo);
if (r)
return r;
}
r = amdgpu_job_alloc_with_ib(adev, 64, &job); r = amdgpu_job_alloc_with_ib(adev, 64, &job);
if (r) if (r)
goto error; return r;
do {
addr = amdgpu_bo_gpu_offset(bo); addr = amdgpu_bo_gpu_offset(bo);
if (ats_entries) { if (ats_entries) {
uint64_t ats_value; uint64_t ats_value;
...@@ -815,17 +828,21 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, ...@@ -815,17 +828,21 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
uint64_t value = 0; uint64_t value = 0;
/* Workaround for fault priority problem on GMC9 */ /* Workaround for fault priority problem on GMC9 */
if (level == AMDGPU_VM_PTB && adev->asic_type >= CHIP_VEGA10) if (level == AMDGPU_VM_PTB &&
adev->asic_type >= CHIP_VEGA10)
value = AMDGPU_PTE_EXECUTABLE; value = AMDGPU_PTE_EXECUTABLE;
amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0, amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
entries, 0, value); entries, 0, value);
} }
bo = bo->shadow;
} while (bo);
amdgpu_ring_pad_ib(ring, &job->ibs[0]); amdgpu_ring_pad_ib(ring, &job->ibs[0]);
WARN_ON(job->ibs[0].length_dw > 64); WARN_ON(job->ibs[0].length_dw > 64);
r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv, r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
AMDGPU_FENCE_OWNER_KFD, false); AMDGPU_FENCE_OWNER_KFD, false);
if (r) if (r)
goto error_free; goto error_free;
...@@ -835,19 +852,13 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, ...@@ -835,19 +852,13 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
if (r) if (r)
goto error_free; goto error_free;
amdgpu_bo_fence(bo, fence, true); amdgpu_bo_fence(vm->root.base.bo, fence, true);
dma_fence_put(fence); dma_fence_put(fence);
if (bo->shadow)
return amdgpu_vm_clear_bo(adev, vm, bo->shadow,
level, pte_support_ats);
return 0; return 0;
error_free: error_free:
amdgpu_job_free(job); amdgpu_job_free(job);
error:
return r; return r;
} }
......
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