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Commit 840a20d3 authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
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drm/amdgpu/gfx7: Reduce linecount in table init 

Replaces switch statements with direct assignments to
reduce line count significantly.
Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fa9e6991
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Showing with 525 additions and 820 deletions
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
View file @ 840a20d3
...@@ -1006,9 +1006,15 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) ...@@ -1006,9 +1006,15 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
*/ */
static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
{ {
const u32 num_tile_mode_states = 32; const u32 num_tile_mode_states =
const u32 num_secondary_tile_mode_states = 16; ARRAY_SIZE(adev->gfx.config.tile_mode_array);
u32 reg_offset, gb_tile_moden, split_equal_to_row_size; const u32 num_secondary_tile_mode_states =
ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
u32 reg_offset, split_equal_to_row_size;
uint32_t *tile, *macrotile;
tile = adev->gfx.config.tile_mode_array;
macrotile = adev->gfx.config.macrotile_mode_array;
switch (adev->gfx.config.mem_row_size_in_kb) { switch (adev->gfx.config.mem_row_size_in_kb) {
case 1: case 1:
...@@ -1023,832 +1029,531 @@ static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) ...@@ -1023,832 +1029,531 @@ static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
break; break;
} }
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
tile[reg_offset] = 0;
for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
macrotile[reg_offset] = 0;
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_BONAIRE: case CHIP_BONAIRE:
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
switch (reg_offset) { PIPE_CONFIG(ADDR_SURF_P4_16x16) |
case 0: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
PIPE_CONFIG(ADDR_SURF_P4_16x16) | tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
case 1: tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; PIPE_CONFIG(ADDR_SURF_P4_16x16) |
case 2: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
PIPE_CONFIG(ADDR_SURF_P4_16x16) | tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
break; TILE_SPLIT(split_equal_to_row_size));
case 3: tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); PIPE_CONFIG(ADDR_SURF_P4_16x16) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
case 4: TILE_SPLIT(split_equal_to_row_size));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[7] = (TILE_SPLIT(split_equal_to_row_size));
PIPE_CONFIG(ADDR_SURF_P4_16x16) | tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_16x16));
TILE_SPLIT(split_equal_to_row_size)); tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
break; PIPE_CONFIG(ADDR_SURF_P4_16x16) |
case 5: MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
case 6: tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
TILE_SPLIT(split_equal_to_row_size)); tile[12] = (TILE_SPLIT(split_equal_to_row_size));
break; tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 7: PIPE_CONFIG(ADDR_SURF_P4_16x16) |
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
break; tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) |
case 8: MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
PIPE_CONFIG(ADDR_SURF_P4_16x16)); tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
break; PIPE_CONFIG(ADDR_SURF_P4_16x16) |
case 9: MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
PIPE_CONFIG(ADDR_SURF_P4_16x16) | tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); PIPE_CONFIG(ADDR_SURF_P4_16x16) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
case 10: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[17] = (TILE_SPLIT(split_equal_to_row_size));
PIPE_CONFIG(ADDR_SURF_P4_16x16) | tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
case 11: tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); PIPE_CONFIG(ADDR_SURF_P4_16x16) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
case 12: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
break; PIPE_CONFIG(ADDR_SURF_P4_16x16) |
case 13: MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
PIPE_CONFIG(ADDR_SURF_P4_16x16) | tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); PIPE_CONFIG(ADDR_SURF_P4_16x16) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
case 14: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[23] = (TILE_SPLIT(split_equal_to_row_size));
PIPE_CONFIG(ADDR_SURF_P4_16x16) | tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
case 15: tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
break; PIPE_CONFIG(ADDR_SURF_P4_16x16) |
case 16: MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
PIPE_CONFIG(ADDR_SURF_P4_16x16) | tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
break; tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 17: PIPE_CONFIG(ADDR_SURF_P4_16x16) |
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
case 18: tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); tile[30] = (TILE_SPLIT(split_equal_to_row_size));
break;
case 19: macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 20: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | NUM_BANKS(ADDR_SURF_16_BANK));
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
case 21: NUM_BANKS(ADDR_SURF_16_BANK));
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 22: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | NUM_BANKS(ADDR_SURF_16_BANK));
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
case 23: NUM_BANKS(ADDR_SURF_8_BANK));
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
case 24: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | NUM_BANKS(ADDR_SURF_4_BANK));
PIPE_CONFIG(ADDR_SURF_P4_16x16) | macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
break; NUM_BANKS(ADDR_SURF_16_BANK));
case 25: macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | NUM_BANKS(ADDR_SURF_16_BANK));
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
case 26: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | NUM_BANKS(ADDR_SURF_16_BANK));
PIPE_CONFIG(ADDR_SURF_P4_16x16) | macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
break; NUM_BANKS(ADDR_SURF_16_BANK));
case 27: macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 28: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | NUM_BANKS(ADDR_SURF_8_BANK));
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
case 29: NUM_BANKS(ADDR_SURF_4_BANK));
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
break; if (reg_offset != 7)
case 30: WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
break;
default:
gb_tile_moden = 0;
break;
}
adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
}
for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
switch (reg_offset) {
case 0:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 1:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 2:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 3:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 4:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 5:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 6:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 8:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 9:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 10:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 11:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 12:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 13:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 14:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
default:
gb_tile_moden = 0;
break;
}
adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
}
break; break;
case CHIP_HAWAII: case CHIP_HAWAII:
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
switch (reg_offset) { PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
case 0: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
case 1: tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
case 2: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
break; TILE_SPLIT(split_equal_to_row_size));
case 3: tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | TILE_SPLIT(split_equal_to_row_size));
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
break; PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
case 4: MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | TILE_SPLIT(split_equal_to_row_size));
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
TILE_SPLIT(split_equal_to_row_size)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
break; TILE_SPLIT(split_equal_to_row_size));
case 5: tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
TILE_SPLIT(split_equal_to_row_size)); MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
break; tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 6: PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
TILE_SPLIT(split_equal_to_row_size)); PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
case 7: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
TILE_SPLIT(split_equal_to_row_size)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break; tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
case 8: MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
case 9: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
case 10: tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
break; PIPE_CONFIG(ADDR_SURF_P4_16x16) |
case 11: MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
case 12: tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
case 13: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
case 14: tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
break; PIPE_CONFIG(ADDR_SURF_P4_16x16) |
case 15: MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
case 16: tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
break; PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
case 17: MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
PIPE_CONFIG(ADDR_SURF_P4_16x16) | tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
break; tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 18: PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
case 19: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
case 20:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 21: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | NUM_BANKS(ADDR_SURF_16_BANK));
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
case 22: NUM_BANKS(ADDR_SURF_16_BANK));
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 23: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | NUM_BANKS(ADDR_SURF_8_BANK));
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
case 24: NUM_BANKS(ADDR_SURF_4_BANK));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); NUM_BANKS(ADDR_SURF_4_BANK));
break; macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 25: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | NUM_BANKS(ADDR_SURF_16_BANK));
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
case 26: NUM_BANKS(ADDR_SURF_16_BANK));
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 27: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | NUM_BANKS(ADDR_SURF_8_BANK));
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
case 28: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | NUM_BANKS(ADDR_SURF_16_BANK));
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
break; NUM_BANKS(ADDR_SURF_8_BANK));
case 29: macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | NUM_BANKS(ADDR_SURF_4_BANK));
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break; for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
case 30: WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
PIPE_CONFIG(ADDR_SURF_P4_16x16) | if (reg_offset != 7)
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break;
default:
gb_tile_moden = 0;
break;
}
adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
}
for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
switch (reg_offset) {
case 0:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 1:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 2:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 3:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 4:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 5:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 6:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
case 8:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 9:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 10:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 11:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 12:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 13:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 14:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK));
break;
default:
gb_tile_moden = 0;
break;
}
adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
}
break; break;
case CHIP_KABINI: case CHIP_KABINI:
case CHIP_KAVERI: case CHIP_KAVERI:
case CHIP_MULLINS: case CHIP_MULLINS:
default: default:
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
switch (reg_offset) { PIPE_CONFIG(ADDR_SURF_P2) |
case 0: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
PIPE_CONFIG(ADDR_SURF_P2) | tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
case 1: tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P2) |
PIPE_CONFIG(ADDR_SURF_P2) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
break; PIPE_CONFIG(ADDR_SURF_P2) |
case 2: TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
PIPE_CONFIG(ADDR_SURF_P2) | tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
break; TILE_SPLIT(split_equal_to_row_size));
case 3: tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P2) |
PIPE_CONFIG(ADDR_SURF_P2) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); PIPE_CONFIG(ADDR_SURF_P2) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
case 4: TILE_SPLIT(split_equal_to_row_size));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[7] = (TILE_SPLIT(split_equal_to_row_size));
PIPE_CONFIG(ADDR_SURF_P2) | tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P2));
TILE_SPLIT(split_equal_to_row_size)); tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
break; PIPE_CONFIG(ADDR_SURF_P2) |
case 5: MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
case 6: tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P2) |
PIPE_CONFIG(ADDR_SURF_P2) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
TILE_SPLIT(split_equal_to_row_size)); tile[12] = (TILE_SPLIT(split_equal_to_row_size));
break; tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 7: PIPE_CONFIG(ADDR_SURF_P2) |
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
break; tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
case 8: MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
PIPE_CONFIG(ADDR_SURF_P2)); tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
break; PIPE_CONFIG(ADDR_SURF_P2) |
case 9: MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
PIPE_CONFIG(ADDR_SURF_P2) | tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); PIPE_CONFIG(ADDR_SURF_P2) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
case 10: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[17] = (TILE_SPLIT(split_equal_to_row_size));
PIPE_CONFIG(ADDR_SURF_P2) | tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
case 11: tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P2) |
PIPE_CONFIG(ADDR_SURF_P2) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); PIPE_CONFIG(ADDR_SURF_P2) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
case 12: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
break; PIPE_CONFIG(ADDR_SURF_P2) |
case 13: MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
PIPE_CONFIG(ADDR_SURF_P2) | tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); PIPE_CONFIG(ADDR_SURF_P2) |
break; MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
case 14: SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | tile[23] = (TILE_SPLIT(split_equal_to_row_size));
PIPE_CONFIG(ADDR_SURF_P2) | tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
case 15: tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P2) |
PIPE_CONFIG(ADDR_SURF_P2) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
break; PIPE_CONFIG(ADDR_SURF_P2) |
case 16: MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
PIPE_CONFIG(ADDR_SURF_P2) | tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | PIPE_CONFIG(ADDR_SURF_P2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
break; tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 17: PIPE_CONFIG(ADDR_SURF_P2) |
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
break; SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
case 18: tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | PIPE_CONFIG(ADDR_SURF_P2) |
PIPE_CONFIG(ADDR_SURF_P2) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); tile[30] = (TILE_SPLIT(split_equal_to_row_size));
break;
case 19: macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
PIPE_CONFIG(ADDR_SURF_P2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 20: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
PIPE_CONFIG(ADDR_SURF_P2) | NUM_BANKS(ADDR_SURF_8_BANK));
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
case 21: NUM_BANKS(ADDR_SURF_8_BANK));
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
PIPE_CONFIG(ADDR_SURF_P2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 22: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
PIPE_CONFIG(ADDR_SURF_P2) | NUM_BANKS(ADDR_SURF_8_BANK));
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
case 23: NUM_BANKS(ADDR_SURF_8_BANK));
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
case 24: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | NUM_BANKS(ADDR_SURF_8_BANK));
PIPE_CONFIG(ADDR_SURF_P2) | macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
break; NUM_BANKS(ADDR_SURF_16_BANK));
case 25: macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
PIPE_CONFIG(ADDR_SURF_P2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | NUM_BANKS(ADDR_SURF_16_BANK));
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
break; BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
case 26: MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | NUM_BANKS(ADDR_SURF_16_BANK));
PIPE_CONFIG(ADDR_SURF_P2) | macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
break; NUM_BANKS(ADDR_SURF_16_BANK));
case 27: macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
PIPE_CONFIG(ADDR_SURF_P2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 28: BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
PIPE_CONFIG(ADDR_SURF_P2) | NUM_BANKS(ADDR_SURF_16_BANK));
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
break; MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
case 29: NUM_BANKS(ADDR_SURF_8_BANK));
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
break; if (reg_offset != 7)
case 30: WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
break;
default:
gb_tile_moden = 0;
break;
}
adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
}
for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
switch (reg_offset) {
case 0:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 1:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 2:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 3:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 4:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 5:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 6:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
case 8:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 9:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 10:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 11:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 12:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 13:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK));
break;
case 14:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK));
break;
default:
gb_tile_moden = 0;
break;
}
adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
}
break; break;
} }
} }
......
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