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Commit 840a20d3 authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
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drm/amdgpu/gfx7: Reduce linecount in table init 

Replaces switch statements with direct assignments to
reduce line count significantly.
Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fa9e6991
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Showing with 525 additions and 820 deletions
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
View file @ 840a20d3
...@@ -1006,9 +1006,15 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev) ...@@ -1006,9 +1006,15 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
*/ */
static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
{ {
const u32 num_tile_mode_states = 32; const u32 num_tile_mode_states =
const u32 num_secondary_tile_mode_states = 16; ARRAY_SIZE(adev->gfx.config.tile_mode_array);
u32 reg_offset, gb_tile_moden, split_equal_to_row_size; const u32 num_secondary_tile_mode_states =
ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
u32 reg_offset, split_equal_to_row_size;
uint32_t *tile, *macrotile;
tile = adev->gfx.config.tile_mode_array;
macrotile = adev->gfx.config.macrotile_mode_array;
switch (adev->gfx.config.mem_row_size_in_kb) { switch (adev->gfx.config.mem_row_size_in_kb) {
case 1: case 1:
...@@ -1023,832 +1029,531 @@ static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev) ...@@ -1023,832 +1029,531 @@ static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
break; break;
} }
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
tile[reg_offset] = 0;
for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
macrotile[reg_offset] = 0;
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_BONAIRE: case CHIP_BONAIRE:
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
switch (reg_offset) {
case 0:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 1:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 2:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 3:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 4:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(split_equal_to_row_size)); TILE_SPLIT(split_equal_to_row_size));
break; tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 5:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 6:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(split_equal_to_row_size)); TILE_SPLIT(split_equal_to_row_size));
break; tile[7] = (TILE_SPLIT(split_equal_to_row_size));
case 7: tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
break;
case 8:
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
PIPE_CONFIG(ADDR_SURF_P4_16x16)); PIPE_CONFIG(ADDR_SURF_P4_16x16));
break; tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 9:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
break; tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 10:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 11:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break; tile[12] = (TILE_SPLIT(split_equal_to_row_size));
case 12: tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
break;
case 13:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
break; tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 14:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
case 15:
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 16:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break; tile[17] = (TILE_SPLIT(split_equal_to_row_size));
case 17: tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
break;
case 18:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
case 19:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
break; tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
case 20:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
case 21:
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
case 22:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[23] = (TILE_SPLIT(split_equal_to_row_size));
case 23: tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
break;
case 24:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
case 25:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
case 26:
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 27:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
break; tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 28:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 29:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break; tile[30] = (TILE_SPLIT(split_equal_to_row_size));
case 30:
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break;
default:
gb_tile_moden = 0;
break;
}
adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
}
for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
switch (reg_offset) {
case 0:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 1:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 2:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 3:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 4:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 5:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 6:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK)); NUM_BANKS(ADDR_SURF_4_BANK));
break; macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
case 8:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
case 9:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 10:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 11:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 12:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 13:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 14:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK)); NUM_BANKS(ADDR_SURF_4_BANK));
break;
default: for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
gb_tile_moden = 0; WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
break; for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
} if (reg_offset != 7)
adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
}
break; break;
case CHIP_HAWAII: case CHIP_HAWAII:
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
switch (reg_offset) {
case 0:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 1:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 2:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 3:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 4:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(split_equal_to_row_size)); TILE_SPLIT(split_equal_to_row_size));
break; tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 5:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(split_equal_to_row_size)); TILE_SPLIT(split_equal_to_row_size));
break; tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 6:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(split_equal_to_row_size)); TILE_SPLIT(split_equal_to_row_size));
break; tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 7:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(split_equal_to_row_size)); TILE_SPLIT(split_equal_to_row_size));
break; tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
case 8:
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
break; tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 9:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
break; tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 10:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 11:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break; tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
case 12:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break; tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 13:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
break; tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 14:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
case 15:
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 16:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break; tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 17:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break; tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
case 18:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
case 19:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
break; tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
case 20:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
case 21:
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
case 22:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
case 23:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
case 24:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
case 25:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
case 26:
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 27:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
break; tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 28:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 29:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break; tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 30:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_16x16) | PIPE_CONFIG(ADDR_SURF_P4_16x16) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break;
default: macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
gb_tile_moden = 0;
break;
}
adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
}
for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
switch (reg_offset) {
case 0:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 1:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 2:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 3:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 4:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 5:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK)); NUM_BANKS(ADDR_SURF_4_BANK));
break; macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 6:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK)); NUM_BANKS(ADDR_SURF_4_BANK));
break; macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 8:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 9:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 10:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 11:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_8_BANK)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 12:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 13:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 14:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
NUM_BANKS(ADDR_SURF_4_BANK)); NUM_BANKS(ADDR_SURF_4_BANK));
break;
default: for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
gb_tile_moden = 0; WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
break; for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
} if (reg_offset != 7)
adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
}
break; break;
case CHIP_KABINI: case CHIP_KABINI:
case CHIP_KAVERI: case CHIP_KAVERI:
case CHIP_MULLINS: case CHIP_MULLINS:
default: default:
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
switch (reg_offset) {
case 0:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 1:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 2:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 3:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 4:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(split_equal_to_row_size)); TILE_SPLIT(split_equal_to_row_size));
break; tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 5:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
break; tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 6:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
TILE_SPLIT(split_equal_to_row_size)); TILE_SPLIT(split_equal_to_row_size));
break; tile[7] = (TILE_SPLIT(split_equal_to_row_size));
case 7: tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
break;
case 8:
gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
PIPE_CONFIG(ADDR_SURF_P2)); PIPE_CONFIG(ADDR_SURF_P2));
break; tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 9:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
break; tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 10:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 11:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break; tile[12] = (TILE_SPLIT(split_equal_to_row_size));
case 12: tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
break;
case 13:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
break; tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 14:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
case 15:
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 16:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break; tile[17] = (TILE_SPLIT(split_equal_to_row_size));
case 17: tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
break;
case 18:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
case 19:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
break; tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
case 20:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
case 21:
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
case 22:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[23] = (TILE_SPLIT(split_equal_to_row_size));
case 23: tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
break;
case 24:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
case 25:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
case 26:
gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
break; tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
case 27:
gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)); MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
break; tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
case 28:
gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
break; tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
case 29:
gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) | PIPE_CONFIG(ADDR_SURF_P2) |
MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
break; tile[30] = (TILE_SPLIT(split_equal_to_row_size));
case 30:
gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size)); macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
break;
default:
gb_tile_moden = 0;
break;
}
adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
}
for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
switch (reg_offset) {
case 0:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_8_BANK)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 1:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_8_BANK)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 2:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 3:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 4:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 5:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 6:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK)); NUM_BANKS(ADDR_SURF_8_BANK));
break; macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
case 8:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
case 9:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
case 10:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
case 11:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 12:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 13:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
NUM_BANKS(ADDR_SURF_16_BANK)); NUM_BANKS(ADDR_SURF_16_BANK));
break; macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
case 14:
gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
NUM_BANKS(ADDR_SURF_8_BANK)); NUM_BANKS(ADDR_SURF_8_BANK));
break;
default: for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
gb_tile_moden = 0; WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
break; for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
} if (reg_offset != 7)
adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
}
break; break;
} }
} }
......
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