Commit 84a96720 authored by Mark Brown's avatar Mark Brown

Merge series "ASoC: SOF: topology: minor updates" from Pierre-Louis Bossart...

Merge series "ASoC: SOF: topology: minor updates" from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>:

Two patches to visualize settings and override dynamic pipelines + one
correction for errors on connections.

Pierre-Louis Bossart (2):
  ASoC: SOF: topology: show clks_control value in dynamic debug
  ASoC: SOF: topology: allow for dynamic pipelines override for debug

Ranjani Sridharan (1):
  ASoC: SOF: topology: return error if sof_connect_dai_widget() fails

 sound/soc/sof/sof-priv.h |  6 ++++++
 sound/soc/sof/topology.c | 24 +++++++++++++++---------
 2 files changed, 21 insertions(+), 9 deletions(-)

--
2.25.1
parents 7b84fd26 4a230769
...@@ -24,6 +24,12 @@ ...@@ -24,6 +24,12 @@
#define SOF_DBG_ENABLE_TRACE BIT(0) #define SOF_DBG_ENABLE_TRACE BIT(0)
#define SOF_DBG_RETAIN_CTX BIT(1) /* prevent DSP D3 on FW exception */ #define SOF_DBG_RETAIN_CTX BIT(1) /* prevent DSP D3 on FW exception */
#define SOF_DBG_VERIFY_TPLG BIT(2) /* verify topology during load */ #define SOF_DBG_VERIFY_TPLG BIT(2) /* verify topology during load */
#define SOF_DBG_DYNAMIC_PIPELINES_OVERRIDE BIT(3) /* 0: use topology token
* 1: override topology
*/
#define SOF_DBG_DYNAMIC_PIPELINES_ENABLE BIT(4) /* 0: use static pipelines
* 1: use dynamic pipelines
*/
#define SOF_DBG_DUMP_REGS BIT(0) #define SOF_DBG_DUMP_REGS BIT(0)
#define SOF_DBG_DUMP_MBOX BIT(1) #define SOF_DBG_DUMP_MBOX BIT(1)
......
...@@ -1759,9 +1759,14 @@ static int sof_widget_load_pipeline(struct snd_soc_component *scomp, int index, ...@@ -1759,9 +1759,14 @@ static int sof_widget_load_pipeline(struct snd_soc_component *scomp, int index,
goto err; goto err;
} }
dev_dbg(scomp->dev, "pipeline %s: period %d pri %d mips %d core %d frames %d\n", if (sof_core_debug & SOF_DBG_DYNAMIC_PIPELINES_OVERRIDE)
swidget->dynamic_pipeline_widget = sof_core_debug &
SOF_DBG_DYNAMIC_PIPELINES_ENABLE;
dev_dbg(scomp->dev, "pipeline %s: period %d pri %d mips %d core %d frames %d dynamic %d\n",
swidget->widget->name, pipeline->period, pipeline->priority, swidget->widget->name, pipeline->period, pipeline->priority,
pipeline->period_mips, pipeline->core, pipeline->frames_per_sched); pipeline->period_mips, pipeline->core, pipeline->frames_per_sched,
swidget->dynamic_pipeline_widget);
swidget->private = pipeline; swidget->private = pipeline;
...@@ -2374,13 +2379,14 @@ static int sof_widget_ready(struct snd_soc_component *scomp, int index, ...@@ -2374,13 +2379,14 @@ static int sof_widget_ready(struct snd_soc_component *scomp, int index,
} }
ret = sof_widget_load_dai(scomp, index, swidget, tw, dai); ret = sof_widget_load_dai(scomp, index, swidget, tw, dai);
if (ret == 0) { if (!ret)
sof_connect_dai_widget(scomp, w, tw, dai); ret = sof_connect_dai_widget(scomp, w, tw, dai);
list_add(&dai->list, &sdev->dai_list); if (ret < 0) {
swidget->private = dai;
} else {
kfree(dai); kfree(dai);
break;
} }
list_add(&dai->list, &sdev->dai_list);
swidget->private = dai;
break; break;
case snd_soc_dapm_mixer: case snd_soc_dapm_mixer:
ret = sof_widget_load_mixer(scomp, index, swidget, tw); ret = sof_widget_load_mixer(scomp, index, swidget, tw);
...@@ -2825,12 +2831,12 @@ static int sof_link_ssp_load(struct snd_soc_component *scomp, int index, ...@@ -2825,12 +2831,12 @@ static int sof_link_ssp_load(struct snd_soc_component *scomp, int index,
config[i].ssp.rx_slots = le32_to_cpu(hw_config[i].rx_slots); config[i].ssp.rx_slots = le32_to_cpu(hw_config[i].rx_slots);
config[i].ssp.tx_slots = le32_to_cpu(hw_config[i].tx_slots); config[i].ssp.tx_slots = le32_to_cpu(hw_config[i].tx_slots);
dev_dbg(scomp->dev, "tplg: config SSP%d fmt 0x%x mclk %d bclk %d fclk %d width (%d)%d slots %d mclk id %d quirks %d\n", dev_dbg(scomp->dev, "tplg: config SSP%d fmt %#x mclk %d bclk %d fclk %d width (%d)%d slots %d mclk id %d quirks %d clks_control %#x\n",
config[i].dai_index, config[i].format, config[i].dai_index, config[i].format,
config[i].ssp.mclk_rate, config[i].ssp.bclk_rate, config[i].ssp.mclk_rate, config[i].ssp.bclk_rate,
config[i].ssp.fsync_rate, config[i].ssp.sample_valid_bits, config[i].ssp.fsync_rate, config[i].ssp.sample_valid_bits,
config[i].ssp.tdm_slot_width, config[i].ssp.tdm_slots, config[i].ssp.tdm_slot_width, config[i].ssp.tdm_slots,
config[i].ssp.mclk_id, config[i].ssp.quirks); config[i].ssp.mclk_id, config[i].ssp.quirks, config[i].ssp.clks_control);
/* validate SSP fsync rate and channel count */ /* validate SSP fsync rate and channel count */
if (config[i].ssp.fsync_rate < 8000 || config[i].ssp.fsync_rate > 192000) { if (config[i].ssp.fsync_rate < 8000 || config[i].ssp.fsync_rate > 192000) {
......
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