Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk

into ppc970.osdl.org:/home/torvalds/v2.6/linux

Documentation/arm/Booting

@@ -118,6 +118,10 @@ to store page tables.  The recommended placement is 32KiB into RAM.
 
 In either case, the following conditions must be met:
 
+- Quiesce all DMA capable devicess so that memory does not get
+  corrupted by bogus network packets or disk data. This will save
+  you many hours of debug.
+
 - CPU register settings
   r0 = 0,
   r1 = machine type number discovered in (3) above.

Documentation/arm/IXP2000

@@ -18,7 +18,7 @@ http://developer.intel.com/design/network/products/npfamily/ixp2xxx.htm
 
 2. Linux Support
 
-Linux currently supports the following features on the IXP2000 NPUS:
+Linux currently supports the following features on the IXP2000 NPUs:
 
 - On-chip serial
 - PCI
@@ -30,10 +30,10 @@ That is about all we can support under Linux ATM b/c the core networking
 components of the chip are accessed via Intel's closed source SDK. 
 Please contact Intel directly on issues with using those. There is
 also a mailing list run by some folks at Princeton University that might
-be of helpful:  https://lists.cs.princeton.edu/mailman/listinfo/ixp2xxx
+be of help:  https://lists.cs.princeton.edu/mailman/listinfo/ixp2xxx
 
 WHATEVER YOU DO, DO NOT POST EMAIL TO THE LINUX-ARM OR LINUX-ARM-KERNEL
-MAILINNG LISTS REGARDING THE INTEL SDK.
+MAILING LISTS REGARDING THE INTEL SDK.
 
 3. Supported Platforms
 
@@ -47,12 +47,12 @@ MAILINNG LISTS REGARDING THE INTEL SDK.
 
 - The IXP2000 platforms ususally have rather complex PCI bus topologies
   with large memory space requirements. In addition, b/c of the way the
-  Intel SDK is designed, devices are enumerated in a vert specific
+  Intel SDK is designed, devices are enumerated in a very specific
   way. B/c of this this, we use "pci=firmware" option in the kernel
   command line so that we do not re-enumerate the bus.
 
 - IXDP2x01 systems have variable clock tick rates that we cannot determine 
-  via HW registers. The "ixdp2x01_clk=XXX" cmd line options allows you
+  via HW registers. The "ixdp2x01_clk=XXX" cmd line options allow you
   to pass the clock rate to the board port.
 
 5. Thanks

arch/arm/Kconfig.debug

@@ -105,14 +105,14 @@ config DEBUG_S3C2410_PORT
 
 config DEBUG_S3C2410_UART
 	depends on ARCH_S3C2410
-	int "S3C2410 UART to use for low-level messages and debug"
+	int "S3C2410 UART to use for low-level debug"
 	default "0"
 	help
 	  Choice for UART for kernel low-level using S3C2410 UARTS,
 	  should be between zero and two. The port must have been
 	  initalised by the boot-loader before use.
 
-	  This will affect the port that the uncompressor code uses
-	  to send debug information to.
+	  The uncompressor code port configuration is now handled
+	  by CONFIG_S3C2410_LOWLEVEL_UART_PORT.
 
 endmenu

arch/arm/mach-ixp2000/Makefile.boot

+   zreladdr-y	:= 0x00008000
+params_phys-y	:= 0x00000100
+

arch/arm/mach-ixp2000/core.c

@@ -9,7 +9,7 @@
  *
  * Based on work Copyright (C) 2002-2003 Intel Corporation
  * 
- * This file is licensed under  the terms of the GNU General Public 
+ * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any 
  * warranty of any kind, whether express or implied.
  */

arch/arm/mach-ixp2000/ixdp2x00.c

@@ -194,7 +194,7 @@ void __init ixdp2x00_map_io(void)
  * Linux is a common design in telecom systems. The problem is that instead 
  * of all the devices being controlled by a single host, different
  * devices are controlles by different NPUs on the same bus, leading to
- * multiple hosts on the bus.i The exact bus layout looks like:
+ * multiple hosts on the bus. The exact bus layout looks like:
  *
  *                   Bus 0
  *    Master NPU <-------------------+-------------------> Slave NPU
@@ -210,9 +210,9 @@ void __init ixdp2x00_map_io(void)
  *             ... Dev    PMC       Media     Eth0   Eth1 ...
  *
  * The master controlls all but Eth1, which is controlled by the
- * slave. What this measn is that the both the master and the slave
+ * slave. What this means is that the both the master and the slave
  * have to scan the bus, but only one of them can enumerate the bus.
- * In addition, after the bus is scaned, each kernel must remove
+ * In addition, after the bus is scanned, each kernel must remove
  * the device(s) it does not control from the PCI dev list otherwise
  * a driver on each NPU will try to manage it and we will have horrible
  * conflicts. Oh..and the slave NPU needs to see the master NPU

arch/arm/mach-ixp4xx/common-pci.c

@@ -238,9 +238,10 @@ static u32 byte_lane_enable_bits(u32 n, int size)
 	return 0xffffffff;
 }
 
-static int read_config(u8 bus_num, u16 devfn, int where, int size, u32 *value)
+static int ixp4xx_pci_read_config(struct pci_bus *bus, u16 devfn, int where, int size, u32 *value)
 {
 	u32 n, byte_enables, addr, data;
+	u8 bus_num = bus->number;
 
 	pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size,
 		bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
@@ -260,9 +261,10 @@ static int read_config(u8 bus_num, u16 devfn, int where, int size, u32 *value)
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static int write_config(u8 bus_num, u16 devfn, int where, int size, u32 value)
+static int ixp4xx_pci_write_config(struct pci_bus *bus,  u16 devfn, int where, int size, u32 value)
 {
 	u32 n, byte_enables, addr, data;
+	u8 bus_num = bus->number;
 
 	pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where,
 		size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
@@ -280,31 +282,11 @@ static int write_config(u8 bus_num, u16 devfn, int where, int size, u32 value)
 	return PCIBIOS_SUCCESSFUL;
 }
 
-/*
- *	Generalized PCI config access functions.
- */
-static int ixp4xx_read_config(struct pci_bus *bus, unsigned int devfn,
-	int where, int size, u32 *value)
-{
-	if (bus->number && !PCI_SLOT(devfn))
-		return local_read_config(where, size, value);
-	return read_config(bus->number, devfn, where, size, value);
-}
-
-static int ixp4xx_write_config(struct pci_bus *bus, unsigned int devfn,
-	int where, int size, u32 value)
-{
-	if (bus->number && !PCI_SLOT(devfn))
-		return local_write_config(where, size, value);
-	return write_config(bus->number, devfn, where, size, value);
-}
-
 struct pci_ops ixp4xx_ops = {
-	.read =  ixp4xx_read_config,
-	.write = ixp4xx_write_config,
+	.read =  ixp4xx_pci_read_config,
+	.write = ixp4xx_pci_write_config,
 };
 
-
 /*
  * PCI abort handler
  */

arch/arm/mach-ixp4xx/common.c

@@ -229,10 +229,10 @@ static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs
 	/*
 	 * Catch up with the real idea of time
 	 */
-	do {	
+	while ((*IXP4XX_OSTS - last_jiffy_time) > LATCH) {
 		timer_tick(regs);
 		last_jiffy_time += LATCH;
-	} while((*IXP4XX_OSTS - last_jiffy_time) > LATCH);
+	}
 
 	write_sequnlock(&xtime_lock);
 

arch/arm/mach-s3c2410/dma.c

@@ -12,6 +12,7 @@
  * published by the Free Software Foundation.
  *
  * Changelog:
+ *  18-Nov-2004 BJD  Removed error for loading onto stopped channel
  *  10-Nov-2004 BJD  Ensure all external symbols exported for modules
  *  10-Nov-2004 BJD  Use sys_device and sysdev_class for power management
  *  08-Aug-2004 BJD  Apply rmk's suggestions
@@ -493,10 +494,6 @@ int s3c2410_dma_enqueue(unsigned int channel, void *id,
 	} else if (chan->state == S3C2410_DMA_IDLE) {
 		if (chan->flags & S3C2410_DMAF_AUTOSTART) {
 			s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START);
-		} else {
-			printk(KERN_DEBUG "dma%d: cannot load onto stopped channel'n", chan->number);
-			local_irq_restore(flags);
-			return -EINVAL;
 		}
 	}
 
@@ -653,6 +650,9 @@ s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs)
 
 			break;
 
+		case S3C2410_DMALOAD_1LOADED_1RUNNING:
+			goto no_load;
+
 		default:
 			printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
 			       chan->number, chan->load_state);
@@ -673,6 +673,7 @@ s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs)
 		}
 	}
 
+ no_load:
 	return IRQ_HANDLED;
 }
 

include/asm-arm/arch-ixp2000/dma.h

 /*
- * linux/include/asm-arm/arch-ixdp2400/dma.h
+ * linux/include/asm-arm/arch-ixp2000/dma.h
  *
  * Copyright (C) 2002 Intel Corp.
  *

include/asm-arm/arch-ixp2000/io.h

@@ -24,7 +24,7 @@
 #define ___io(p)		((unsigned long)((p)+IXP2000_PCI_IO_VIRT_BASE))
 
 /*
- * IXP200 does not do proper byte-lane conversion for PCI addresses,
+ * IXP2000 does not do proper byte-lane conversion for PCI addresses,
  * so we need to override standard functions.
  */
 #define alignb(addr)		((addr & ~3) + (3 - (addr & 3)))

include/asm-arm/arch-ixp2000/irqs.h

@@ -46,13 +46,12 @@
 #define	IRQ_IXP2000_PCI   		15 /* PCI INTA or INTB */
 #define	IRQ_IXP2000_THDA0   		16 /* thread 0-31A */
 #define	IRQ_IXP2000_THDA1  		17 /* thread 32-63A */
-#define	IRQ_IXP2000_THDA2		18 /* thread 64-95A */
-#define	IRQ_IXP2000_THDA3 		19 /* thread 96-127A */
-#define	IRQ_IXP2000_THDB0		24 /* thread 0-31 B */
+#define	IRQ_IXP2000_THDA2		18 /* thread 64-95A, IXP2800 only */
+#define	IRQ_IXP2000_THDA3 		19 /* thread 96-127A, IXP2800 only */
+#define	IRQ_IXP2000_THDB0		24 /* thread 0-31B */
 #define	IRQ_IXP2000_THDB1		25 /* thread 32-63B */
-/* only 64 threads supported for IXP2400, rest or for IXP2800*/
-#define	IRQ_IXP2000_THDB2		26 /* thread 64-95B */
-#define	IRQ_IXP2000_THDB3		27 /* thread 96-127B */
+#define	IRQ_IXP2000_THDB2		26 /* thread 64-95B, IXP2800 only */
+#define	IRQ_IXP2000_THDB3		27 /* thread 96-127B, IXP2800 only */
 
 /* define generic GPIOs */
 #define IRQ_IXP2000_GPIO0		32

include/asm-arm/arch-ixp2000/ixdp2x00.h

@@ -53,7 +53,7 @@
 
 /*
  * PCI devfns for on-board devices. We need these to be able to
- * properly translte IRQs and for device removal.
+ * properly translate IRQs and for device removal.
  */
 #define	IXDP2400_SLAVE_ENET_DEVFN	0x18	/* Bus 1 */
 #define	IXDP2400_MASTER_ENET_DEVFN	0x20	/* Bus 1 */

include/asm-arm/arch-ixp2000/ixp2000-regs.h

@@ -115,7 +115,7 @@
 
 /*
  * Mask of valid IRQs in the 32-bit IRQ register. We use
- * this to mark certain IRQs as being in-valid.
+ * this to mark certain IRQs as being invalid.
  */
 #define	IXP2000_VALID_IRQ_MASK	0x0f0fffff
 
@@ -251,7 +251,7 @@
 #define	SLOWPORT_CCR_DIV_30		0x0f
 
 /*
- * PCR values.  PCR configure the mode of the interfac3
+ * PCR values.  PCR configure the mode of the interface.
  */
 #define	SLOWPORT_MODE_FLASH		0x00
 #define	SLOWPORT_MODE_LUCENT		0x01
@@ -260,7 +260,7 @@
 #define	SLOWPORT_MODE_MOTOROLA_UP	0x04
 
 /*
- * ADC values.  Defines data and address bus widths
+ * ADC values.  Defines data and address bus widths.
  */
 #define	SLOWPORT_ADDR_WIDTH_8		0x00
 #define	SLOWPORT_ADDR_WIDTH_16		0x01
@@ -272,7 +272,7 @@
 #define	SLOWPORT_DATA_WIDTH_32		0x30
 
 /*
- * Masks and shifts for various fields in the WTC and RTC registers
+ * Masks and shifts for various fields in the WTC and RTC registers.
  */
 #define	SLOWPORT_WRTC_MASK_HD		0x0003
 #define	SLOWPORT_WRTC_MASK_SU		0x003c
@@ -284,7 +284,7 @@
 
 
 /*
- * GPIO registers & GPIO interface
+ * GPIO registers & GPIO interface.
  */
 #define IXP2000_GPIO_REG(x)		((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
 #define IXP2000_GPIO_PLR		IXP2000_GPIO_REG(0x00)

include/asm-arm/arch-ixp2000/platform.h

@@ -16,10 +16,10 @@
 #ifndef __ASSEMBLY__
 
 /*
- * The IXP2400 B0 silicon contains an errata that causes writes to 
- * on-chip I/O register to not complete fully. What this means is
+ * The IXP2400 B0 silicon contains an erratum (#66) that causes writes
+ * to on-chip I/O register to not complete fully. What this means is
  * that if you have a write to on-chip I/O followed by a back-to-back
- * read or write, the first write will happend twice. OR...if it's
+ * read or write, the first write will happen twice. OR...if it's
  * not a back-to-back trasaction, the read or write will generate 
  * incorrect data.
  *

include/asm-arm/arch-ixp2000/system.h

 /*
- * linux/include/asm-arm/arch-ixp2400/system.h
+ * linux/include/asm-arm/arch-ixp2000/system.h
  *
  * Copyright (C) 2002 Intel Corp.
  *

include/asm-arm/arch-ixp4xx/ixp4xx-regs.h

@@ -55,7 +55,7 @@
  * PCI Config registers
  */
 #define IXP4XX_PCI_CFG_BASE_PHYS	(0xC0000000)
-#define	IXP4XX_PCI_CFG_BASE_VIRT	(0xFFBFD000)
+#define	IXP4XX_PCI_CFG_BASE_VIRT	(0xFFBFE000)
 #define IXP4XX_PCI_CFG_REGION_SIZE	(0x00001000)
 
 /*

include/asm-arm/arch-s3c2410/regs-gpio.h

@@ -16,6 +16,8 @@
  *    20-07-2004     BJD     Added GPIO pin numbers, added Port A definitions
  *    04-10-2004     BJD     Fixed number of bugs, added EXT IRQ filter defs
  *    17-10-2004     BJD     Added GSTATUS1 register definitions
+ *    18-11-2004     BJD     Fixed definitions of GPE3, GPE4, GPE5 and GPE6
+ *    18-11-2004     BJD     Added S3C2440 AC97 controls
 */
 
 
@@ -424,12 +426,14 @@
 #define S3C2410_GPE3_INP       (0x00 << 6)
 #define S3C2410_GPE3_OUTP      (0x01 << 6)
 #define S3C2410_GPE3_I2SSDI    (0x02 << 6)
+#define S3C2410_GPE3_nSS0      (0x03 << 6)
 #define S3C2410_GPE3_MASK      (0x03 << 6)
 
 #define S3C2410_GPE4           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
 #define S3C2410_GPE4_INP       (0x00 << 8)
 #define S3C2410_GPE4_OUTP      (0x01 << 8)
 #define S3C2410_GPE4_I2SSDO    (0x02 << 8)
+#define S3C2410_GPE4_I2SSDI    (0x03 << 8)
 #define S3C2410_GPE4_MASK      (0x03 << 8)
 
 #define S3C2410_GPE5           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
@@ -440,12 +444,12 @@
 #define S3C2410_GPE6           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
 #define S3C2410_GPE6_INP       (0x00 << 12)
 #define S3C2410_GPE6_OUTP      (0x01 << 12)
-#define S3C2410_GPE6_SDCLK     (0x02 << 12)
+#define S3C2410_GPE6_SDCMD     (0x02 << 12)
 
 #define S3C2410_GPE7           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
 #define S3C2410_GPE7_INP       (0x00 << 14)
 #define S3C2410_GPE7_OUTP      (0x01 << 14)
-#define S3C2410_GPE7_SDCMD     (0x02 << 14)
+#define S3C2410_GPE7_SDDAT0    (0x02 << 14)
 
 #define S3C2410_GPE8           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
 #define S3C2410_GPE8_INP       (0x00 << 16)
@@ -489,6 +493,12 @@
 #define S3C2410_GPE15_IICSDA   (0x02 << 30)
 #define S3C2410_GPE15_MASK     (0x03 << 30)
 
+#define S3C2440_GPE0_ACSYNC    (0x03 << 0)
+#define S3C2440_GPE1_ACBITCLK  (0x03 << 2)
+#define S3C2440_GPE2_ACRESET   (0x03 << 4)
+#define S3C2440_GPE3_ACIN      (0x03 << 6)
+#define S3C2440_GPE4_ACOUT     (0x03 << 8)
+
 #define S3C2410_GPE_PUPDIS(x)  (1<<(x))
 
 /* Port F consists of 8 GPIO/Special function