Commit 84e3e9d0 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Kevin Hilman:
 "A fairly random colletion of fixes based on -rc1 for OMAP, sunxi and
  prima2 as well as a few arm64-specific DT fixes.

  This series also includes a late to support a new Allwinner (sunxi)
  SoC, but since it's rather simple and isolated to the
  platform-specific code, it's included it for this -rc"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG
  arm: dts: vexpress: add missing CCI PMU device node to TC2
  arm: dts: vexpress: describe all PMUs in TC2 dts
  GICv3: Add ITS entry to THUNDER dts
  arm64: dts: Add poweroff button device node for APM X-Gene platform
  ARM: dts: am4372.dtsi: disable rfbi
  ARM: dts: am57xx-beagle-x15: Provide supply for usb2_phy2
  ARM: dts: am4372: Add emif node
  Revert "ARM: dts: am335x-boneblack: disable RTC-only sleep"
  ARM: sunxi: Enable simplefb in the defconfig
  ARM: Remove deprecated symbol from defconfig files
  ARM: sunxi: Add Machine support for A33
  ARM: sunxi: Introduce Allwinner H3 support
  Documentation: sunxi: Update Allwinner SoC documentation
  ARM: prima2: move to use REGMAP APIs for rtciobrg
  ARM: dts: atlas7: add pinctrl and gpio descriptions
  ARM: OMAP2+: Remove unnessary return statement from the void function, omap2_show_dma_caps
  memory: omap-gpmc: Fix parsing of devices
parents b9243b5a 8dfbc0ab
...@@ -36,7 +36,7 @@ SunXi family ...@@ -36,7 +36,7 @@ SunXi family
+ User Manual + User Manual
http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf
- Allwinner A23 - Allwinner A23 (sun8i)
+ Datasheet + Datasheet
http://dl.linux-sunxi.org/A23/A23%20Datasheet%20V1.0%2020130830.pdf http://dl.linux-sunxi.org/A23/A23%20Datasheet%20V1.0%2020130830.pdf
+ User Manual + User Manual
...@@ -55,7 +55,23 @@ SunXi family ...@@ -55,7 +55,23 @@ SunXi family
+ User Manual + User Manual
http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20User%20Manual%20%20V1.0%2020130322.pdf http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20User%20Manual%20%20V1.0%2020130322.pdf
- Allwinner A33 (sun8i)
+ Datasheet
http://dl.linux-sunxi.org/A33/A33%20Datasheet%20release%201.1.pdf
+ User Manual
http://dl.linux-sunxi.org/A33/A33%20user%20manual%20release%201.1.pdf
- Allwinner H3 (sun8i)
+ Datasheet
http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf
* Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
- Allwinner A80 - Allwinner A80
+ Datasheet + Datasheet
http://dl.linux-sunxi.org/A80/A80_Datasheet_Revision_1.0_0404.pdf http://dl.linux-sunxi.org/A80/A80_Datasheet_Revision_1.0_0404.pdf
* Octa ARM Cortex-A7 based SoCs
- Allwinner A83T
+ Not Supported
+ Datasheet
http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf
...@@ -9,4 +9,6 @@ using one of the following compatible strings: ...@@ -9,4 +9,6 @@ using one of the following compatible strings:
allwinner,sun6i-a31 allwinner,sun6i-a31
allwinner,sun7i-a20 allwinner,sun7i-a20
allwinner,sun8i-a23 allwinner,sun8i-a23
allwinner,sun8i-a33
allwinner,sun8i-h3
allwinner,sun9i-a80 allwinner,sun9i-a80
...@@ -8,6 +8,7 @@ of the EMIF IP and memory parts attached to it. ...@@ -8,6 +8,7 @@ of the EMIF IP and memory parts attached to it.
Required properties: Required properties:
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev> - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
is the IP revision of the specific EMIF instance. is the IP revision of the specific EMIF instance.
For am437x should be ti,emif-am4372.
- phy-type : <u32> indicating the DDR phy type. Following are the - phy-type : <u32> indicating the DDR phy type. Following are the
allowed values allowed values
......
...@@ -1614,6 +1614,7 @@ M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> ...@@ -1614,6 +1614,7 @@ M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained S: Maintained
F: arch/arm/boot/dts/vexpress* F: arch/arm/boot/dts/vexpress*
F: arch/arm64/boot/dts/arm/vexpress*
F: arch/arm/mach-vexpress/ F: arch/arm/mach-vexpress/
F: */*/vexpress* F: */*/vexpress*
F: */*/*/vexpress* F: */*/*/vexpress*
......
...@@ -80,3 +80,7 @@ hdmi { ...@@ -80,3 +80,7 @@ hdmi {
status = "okay"; status = "okay";
}; };
}; };
&rtc {
system-power-controller;
};
...@@ -132,6 +132,12 @@ scm_clockdomains: clockdomains { ...@@ -132,6 +132,12 @@ scm_clockdomains: clockdomains {
}; };
}; };
emif: emif@4c000000 {
compatible = "ti,emif-am4372";
reg = <0x4c000000 0x1000000>;
ti,hwmods = "emif";
};
edma: edma@49000000 { edma: edma@49000000 {
compatible = "ti,edma3"; compatible = "ti,edma3";
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
...@@ -941,6 +947,7 @@ rfbi: rfbi@4832a800 { ...@@ -941,6 +947,7 @@ rfbi: rfbi@4832a800 {
ti,hwmods = "dss_rfbi"; ti,hwmods = "dss_rfbi";
clocks = <&disp_clk>; clocks = <&disp_clk>;
clock-names = "fck"; clock-names = "fck";
status = "disabled";
}; };
}; };
......
...@@ -605,6 +605,10 @@ &usb2_phy1 { ...@@ -605,6 +605,10 @@ &usb2_phy1 {
phy-supply = <&ldousb_reg>; phy-supply = <&ldousb_reg>;
}; };
&usb2_phy2 {
phy-supply = <&ldousb_reg>;
};
&usb1 { &usb1 {
dr_mode = "host"; dr_mode = "host";
pinctrl-names = "default"; pinctrl-names = "default";
......
...@@ -135,6 +135,1025 @@ pinctrl: ioc@18880000 { ...@@ -135,6 +135,1025 @@ pinctrl: ioc@18880000 {
compatible = "sirf,atlas7-ioc"; compatible = "sirf,atlas7-ioc";
reg = <0x18880000 0x1000>, reg = <0x18880000 0x1000>,
<0x10E40000 0x1000>; <0x10E40000 0x1000>;
audio_ac97_pmx: audio_ac97@0 {
audio_ac97 {
groups = "audio_ac97_grp";
function = "audio_ac97";
};
};
audio_func_dbg_pmx: audio_func_dbg@0 {
audio_func_dbg {
groups = "audio_func_dbg_grp";
function = "audio_func_dbg";
};
};
audio_i2s_pmx: audio_i2s@0 {
audio_i2s {
groups = "audio_i2s_grp";
function = "audio_i2s";
};
};
audio_i2s_2ch_pmx: audio_i2s_2ch@0 {
audio_i2s_2ch {
groups = "audio_i2s_2ch_grp";
function = "audio_i2s_2ch";
};
};
audio_i2s_extclk_pmx: audio_i2s_extclk@0 {
audio_i2s_extclk {
groups = "audio_i2s_extclk_grp";
function = "audio_i2s_extclk";
};
};
audio_uart0_pmx: audio_uart0@0 {
audio_uart0 {
groups = "audio_uart0_grp";
function = "audio_uart0";
};
};
audio_uart1_pmx: audio_uart1@0 {
audio_uart1 {
groups = "audio_uart1_grp";
function = "audio_uart1";
};
};
audio_uart2_pmx0: audio_uart2@0 {
audio_uart2_0 {
groups = "audio_uart2_grp0";
function = "audio_uart2_m0";
};
};
audio_uart2_pmx1: audio_uart2@1 {
audio_uart2_1 {
groups = "audio_uart2_grp1";
function = "audio_uart2_m1";
};
};
c_can_trnsvr_pmx: c_can_trnsvr@0 {
c_can_trnsvr {
groups = "c_can_trnsvr_grp";
function = "c_can_trnsvr";
};
};
c0_can_pmx0: c0_can@0 {
c0_can_0 {
groups = "c0_can_grp0";
function = "c0_can_m0";
};
};
c0_can_pmx1: c0_can@1 {
c0_can_1 {
groups = "c0_can_grp1";
function = "c0_can_m1";
};
};
c1_can_pmx0: c1_can@0 {
c1_can_0 {
groups = "c1_can_grp0";
function = "c1_can_m0";
};
};
c1_can_pmx1: c1_can@1 {
c1_can_1 {
groups = "c1_can_grp1";
function = "c1_can_m1";
};
};
c1_can_pmx2: c1_can@2 {
c1_can_2 {
groups = "c1_can_grp2";
function = "c1_can_m2";
};
};
ca_audio_lpc_pmx: ca_audio_lpc@0 {
ca_audio_lpc {
groups = "ca_audio_lpc_grp";
function = "ca_audio_lpc";
};
};
ca_bt_lpc_pmx: ca_bt_lpc@0 {
ca_bt_lpc {
groups = "ca_bt_lpc_grp";
function = "ca_bt_lpc";
};
};
ca_coex_pmx: ca_coex@0 {
ca_coex {
groups = "ca_coex_grp";
function = "ca_coex";
};
};
ca_curator_lpc_pmx: ca_curator_lpc@0 {
ca_curator_lpc {
groups = "ca_curator_lpc_grp";
function = "ca_curator_lpc";
};
};
ca_pcm_debug_pmx: ca_pcm_debug@0 {
ca_pcm_debug {
groups = "ca_pcm_debug_grp";
function = "ca_pcm_debug";
};
};
ca_pio_pmx: ca_pio@0 {
ca_pio {
groups = "ca_pio_grp";
function = "ca_pio";
};
};
ca_sdio_debug_pmx: ca_sdio_debug@0 {
ca_sdio_debug {
groups = "ca_sdio_debug_grp";
function = "ca_sdio_debug";
};
};
ca_spi_pmx: ca_spi@0 {
ca_spi {
groups = "ca_spi_grp";
function = "ca_spi";
};
};
ca_trb_pmx: ca_trb@0 {
ca_trb {
groups = "ca_trb_grp";
function = "ca_trb";
};
};
ca_uart_debug_pmx: ca_uart_debug@0 {
ca_uart_debug {
groups = "ca_uart_debug_grp";
function = "ca_uart_debug";
};
};
clkc_pmx0: clkc@0 {
clkc_0 {
groups = "clkc_grp0";
function = "clkc_m0";
};
};
clkc_pmx1: clkc@1 {
clkc_1 {
groups = "clkc_grp1";
function = "clkc_m1";
};
};
gn_gnss_i2c_pmx: gn_gnss_i2c@0 {
gn_gnss_i2c {
groups = "gn_gnss_i2c_grp";
function = "gn_gnss_i2c";
};
};
gn_gnss_uart_nopause_pmx: gn_gnss_uart_nopause@0 {
gn_gnss_uart_nopause {
groups = "gn_gnss_uart_nopause_grp";
function = "gn_gnss_uart_nopause";
};
};
gn_gnss_uart_pmx: gn_gnss_uart@0 {
gn_gnss_uart {
groups = "gn_gnss_uart_grp";
function = "gn_gnss_uart";
};
};
gn_trg_spi_pmx0: gn_trg_spi@0 {
gn_trg_spi_0 {
groups = "gn_trg_spi_grp0";
function = "gn_trg_spi_m0";
};
};
gn_trg_spi_pmx1: gn_trg_spi@1 {
gn_trg_spi_1 {
groups = "gn_trg_spi_grp1";
function = "gn_trg_spi_m1";
};
};
cvbs_dbg_pmx: cvbs_dbg@0 {
cvbs_dbg {
groups = "cvbs_dbg_grp";
function = "cvbs_dbg";
};
};
cvbs_dbg_test_pmx0: cvbs_dbg_test@0 {
cvbs_dbg_test_0 {
groups = "cvbs_dbg_test_grp0";
function = "cvbs_dbg_test_m0";
};
};
cvbs_dbg_test_pmx1: cvbs_dbg_test@1 {
cvbs_dbg_test_1 {
groups = "cvbs_dbg_test_grp1";
function = "cvbs_dbg_test_m1";
};
};
cvbs_dbg_test_pmx2: cvbs_dbg_test@2 {
cvbs_dbg_test_2 {
groups = "cvbs_dbg_test_grp2";
function = "cvbs_dbg_test_m2";
};
};
cvbs_dbg_test_pmx3: cvbs_dbg_test@3 {
cvbs_dbg_test_3 {
groups = "cvbs_dbg_test_grp3";
function = "cvbs_dbg_test_m3";
};
};
cvbs_dbg_test_pmx4: cvbs_dbg_test@4 {
cvbs_dbg_test_4 {
groups = "cvbs_dbg_test_grp4";
function = "cvbs_dbg_test_m4";
};
};
cvbs_dbg_test_pmx5: cvbs_dbg_test@5 {
cvbs_dbg_test_5 {
groups = "cvbs_dbg_test_grp5";
function = "cvbs_dbg_test_m5";
};
};
cvbs_dbg_test_pmx6: cvbs_dbg_test@6 {
cvbs_dbg_test_6 {
groups = "cvbs_dbg_test_grp6";
function = "cvbs_dbg_test_m6";
};
};
cvbs_dbg_test_pmx7: cvbs_dbg_test@7 {
cvbs_dbg_test_7 {
groups = "cvbs_dbg_test_grp7";
function = "cvbs_dbg_test_m7";
};
};
cvbs_dbg_test_pmx8: cvbs_dbg_test@8 {
cvbs_dbg_test_8 {
groups = "cvbs_dbg_test_grp8";
function = "cvbs_dbg_test_m8";
};
};
cvbs_dbg_test_pmx9: cvbs_dbg_test@9 {
cvbs_dbg_test_9 {
groups = "cvbs_dbg_test_grp9";
function = "cvbs_dbg_test_m9";
};
};
cvbs_dbg_test_pmx10: cvbs_dbg_test@10 {
cvbs_dbg_test_10 {
groups = "cvbs_dbg_test_grp10";
function = "cvbs_dbg_test_m10";
};
};
cvbs_dbg_test_pmx11: cvbs_dbg_test@11 {
cvbs_dbg_test_11 {
groups = "cvbs_dbg_test_grp11";
function = "cvbs_dbg_test_m11";
};
};
cvbs_dbg_test_pmx12: cvbs_dbg_test@12 {
cvbs_dbg_test_12 {
groups = "cvbs_dbg_test_grp12";
function = "cvbs_dbg_test_m12";
};
};
cvbs_dbg_test_pmx13: cvbs_dbg_test@13 {
cvbs_dbg_test_13 {
groups = "cvbs_dbg_test_grp13";
function = "cvbs_dbg_test_m13";
};
};
cvbs_dbg_test_pmx14: cvbs_dbg_test@14 {
cvbs_dbg_test_14 {
groups = "cvbs_dbg_test_grp14";
function = "cvbs_dbg_test_m14";
};
};
cvbs_dbg_test_pmx15: cvbs_dbg_test@15 {
cvbs_dbg_test_15 {
groups = "cvbs_dbg_test_grp15";
function = "cvbs_dbg_test_m15";
};
};
gn_gnss_power_pmx: gn_gnss_power@0 {
gn_gnss_power {
groups = "gn_gnss_power_grp";
function = "gn_gnss_power";
};
};
gn_gnss_sw_status_pmx: gn_gnss_sw_status@0 {
gn_gnss_sw_status {
groups = "gn_gnss_sw_status_grp";
function = "gn_gnss_sw_status";
};
};
gn_gnss_eclk_pmx: gn_gnss_eclk@0 {
gn_gnss_eclk {
groups = "gn_gnss_eclk_grp";
function = "gn_gnss_eclk";
};
};
gn_gnss_irq1_pmx0: gn_gnss_irq1@0 {
gn_gnss_irq1_0 {
groups = "gn_gnss_irq1_grp0";
function = "gn_gnss_irq1_m0";
};
};
gn_gnss_irq2_pmx0: gn_gnss_irq2@0 {
gn_gnss_irq2_0 {
groups = "gn_gnss_irq2_grp0";
function = "gn_gnss_irq2_m0";
};
};
gn_gnss_tm_pmx: gn_gnss_tm@0 {
gn_gnss_tm {
groups = "gn_gnss_tm_grp";
function = "gn_gnss_tm";
};
};
gn_gnss_tsync_pmx: gn_gnss_tsync@0 {
gn_gnss_tsync {
groups = "gn_gnss_tsync_grp";
function = "gn_gnss_tsync";
};
};
gn_io_gnsssys_sw_cfg_pmx: gn_io_gnsssys_sw_cfg@0 {
gn_io_gnsssys_sw_cfg {
groups = "gn_io_gnsssys_sw_cfg_grp";
function = "gn_io_gnsssys_sw_cfg";
};
};
gn_trg_pmx0: gn_trg@0 {
gn_trg_0 {
groups = "gn_trg_grp0";
function = "gn_trg_m0";
};
};
gn_trg_pmx1: gn_trg@1 {
gn_trg_1 {
groups = "gn_trg_grp1";
function = "gn_trg_m1";
};
};
gn_trg_shutdown_pmx0: gn_trg_shutdown@0 {
gn_trg_shutdown_0 {
groups = "gn_trg_shutdown_grp0";
function = "gn_trg_shutdown_m0";
};
};
gn_trg_shutdown_pmx1: gn_trg_shutdown@1 {
gn_trg_shutdown_1 {
groups = "gn_trg_shutdown_grp1";
function = "gn_trg_shutdown_m1";
};
};
gn_trg_shutdown_pmx2: gn_trg_shutdown@2 {
gn_trg_shutdown_2 {
groups = "gn_trg_shutdown_grp2";
function = "gn_trg_shutdown_m2";
};
};
gn_trg_shutdown_pmx3: gn_trg_shutdown@3 {
gn_trg_shutdown_3 {
groups = "gn_trg_shutdown_grp3";
function = "gn_trg_shutdown_m3";
};
};
i2c0_pmx: i2c0@0 {
i2c0 {
groups = "i2c0_grp";
function = "i2c0";
};
};
i2c1_pmx: i2c1@0 {
i2c1 {
groups = "i2c1_grp";
function = "i2c1";
};
};
jtag_pmx0: jtag@0 {
jtag_0 {
groups = "jtag_grp0";
function = "jtag_m0";
};
};
ks_kas_spi_pmx0: ks_kas_spi@0 {
ks_kas_spi_0 {
groups = "ks_kas_spi_grp0";
function = "ks_kas_spi_m0";
};
};
ld_ldd_pmx: ld_ldd@0 {
ld_ldd {
groups = "ld_ldd_grp";
function = "ld_ldd";
};
};
ld_ldd_16bit_pmx: ld_ldd_16bit@0 {
ld_ldd_16bit {
groups = "ld_ldd_16bit_grp";
function = "ld_ldd_16bit";
};
};
ld_ldd_fck_pmx: ld_ldd_fck@0 {
ld_ldd_fck {
groups = "ld_ldd_fck_grp";
function = "ld_ldd_fck";
};
};
ld_ldd_lck_pmx: ld_ldd_lck@0 {
ld_ldd_lck {
groups = "ld_ldd_lck_grp";
function = "ld_ldd_lck";
};
};
lr_lcdrom_pmx: lr_lcdrom@0 {
lr_lcdrom {
groups = "lr_lcdrom_grp";
function = "lr_lcdrom";
};
};
lvds_analog_pmx: lvds_analog@0 {
lvds_analog {
groups = "lvds_analog_grp";
function = "lvds_analog";
};
};
nd_df_pmx: nd_df@0 {
nd_df {
groups = "nd_df_grp";
function = "nd_df";
};
};
nd_df_nowp_pmx: nd_df_nowp@0 {
nd_df_nowp {
groups = "nd_df_nowp_grp";
function = "nd_df_nowp";
};
};
ps_pmx: ps@0 {
ps {
groups = "ps_grp";
function = "ps";
};
};
pwc_core_on_pmx: pwc_core_on@0 {
pwc_core_on {
groups = "pwc_core_on_grp";
function = "pwc_core_on";
};
};
pwc_ext_on_pmx: pwc_ext_on@0 {
pwc_ext_on {
groups = "pwc_ext_on_grp";
function = "pwc_ext_on";
};
};
pwc_gpio3_clk_pmx: pwc_gpio3_clk@0 {
pwc_gpio3_clk {
groups = "pwc_gpio3_clk_grp";
function = "pwc_gpio3_clk";
};
};
pwc_io_on_pmx: pwc_io_on@0 {
pwc_io_on {
groups = "pwc_io_on_grp";
function = "pwc_io_on";
};
};
pwc_lowbatt_b_pmx0: pwc_lowbatt_b@0 {
pwc_lowbatt_b_0 {
groups = "pwc_lowbatt_b_grp0";
function = "pwc_lowbatt_b_m0";
};
};
pwc_mem_on_pmx: pwc_mem_on@0 {
pwc_mem_on {
groups = "pwc_mem_on_grp";
function = "pwc_mem_on";
};
};
pwc_on_key_b_pmx0: pwc_on_key_b@0 {
pwc_on_key_b_0 {
groups = "pwc_on_key_b_grp0";
function = "pwc_on_key_b_m0";
};
};
pwc_wakeup_src0_pmx: pwc_wakeup_src0@0 {
pwc_wakeup_src0 {
groups = "pwc_wakeup_src0_grp";
function = "pwc_wakeup_src0";
};
};
pwc_wakeup_src1_pmx: pwc_wakeup_src1@0 {
pwc_wakeup_src1 {
groups = "pwc_wakeup_src1_grp";
function = "pwc_wakeup_src1";
};
};
pwc_wakeup_src2_pmx: pwc_wakeup_src2@0 {
pwc_wakeup_src2 {
groups = "pwc_wakeup_src2_grp";
function = "pwc_wakeup_src2";
};
};
pwc_wakeup_src3_pmx: pwc_wakeup_src3@0 {
pwc_wakeup_src3 {
groups = "pwc_wakeup_src3_grp";
function = "pwc_wakeup_src3";
};
};
pw_cko0_pmx0: pw_cko0@0 {
pw_cko0_0 {
groups = "pw_cko0_grp0";
function = "pw_cko0_m0";
};
};
pw_cko0_pmx1: pw_cko0@1 {
pw_cko0_1 {
groups = "pw_cko0_grp1";
function = "pw_cko0_m1";
};
};
pw_cko0_pmx2: pw_cko0@2 {
pw_cko0_2 {
groups = "pw_cko0_grp2";
function = "pw_cko0_m2";
};
};
pw_cko1_pmx0: pw_cko1@0 {
pw_cko1_0 {
groups = "pw_cko1_grp0";
function = "pw_cko1_m0";
};
};
pw_cko1_pmx1: pw_cko1@1 {
pw_cko1_1 {
groups = "pw_cko1_grp1";
function = "pw_cko1_m1";
};
};
pw_i2s01_clk_pmx0: pw_i2s01_clk@0 {
pw_i2s01_clk_0 {
groups = "pw_i2s01_clk_grp0";
function = "pw_i2s01_clk_m0";
};
};
pw_i2s01_clk_pmx1: pw_i2s01_clk@1 {
pw_i2s01_clk_1 {
groups = "pw_i2s01_clk_grp1";
function = "pw_i2s01_clk_m1";
};
};
pw_pwm0_pmx: pw_pwm0@0 {
pw_pwm0 {
groups = "pw_pwm0_grp";
function = "pw_pwm0";
};
};
pw_pwm1_pmx: pw_pwm1@0 {
pw_pwm1 {
groups = "pw_pwm1_grp";
function = "pw_pwm1";
};
};
pw_pwm2_pmx0: pw_pwm2@0 {
pw_pwm2_0 {
groups = "pw_pwm2_grp0";
function = "pw_pwm2_m0";
};
};
pw_pwm2_pmx1: pw_pwm2@1 {
pw_pwm2_1 {
groups = "pw_pwm2_grp1";
function = "pw_pwm2_m1";
};
};
pw_pwm3_pmx0: pw_pwm3@0 {
pw_pwm3_0 {
groups = "pw_pwm3_grp0";
function = "pw_pwm3_m0";
};
};
pw_pwm3_pmx1: pw_pwm3@1 {
pw_pwm3_1 {
groups = "pw_pwm3_grp1";
function = "pw_pwm3_m1";
};
};
pw_pwm_cpu_vol_pmx0: pw_pwm_cpu_vol@0 {
pw_pwm_cpu_vol_0 {
groups = "pw_pwm_cpu_vol_grp0";
function = "pw_pwm_cpu_vol_m0";
};
};
pw_pwm_cpu_vol_pmx1: pw_pwm_cpu_vol@1 {
pw_pwm_cpu_vol_1 {
groups = "pw_pwm_cpu_vol_grp1";
function = "pw_pwm_cpu_vol_m1";
};
};
pw_backlight_pmx0: pw_backlight@0 {
pw_backlight_0 {
groups = "pw_backlight_grp0";
function = "pw_backlight_m0";
};
};
pw_backlight_pmx1: pw_backlight@1 {
pw_backlight_1 {
groups = "pw_backlight_grp1";
function = "pw_backlight_m1";
};
};
rg_eth_mac_pmx: rg_eth_mac@0 {
rg_eth_mac {
groups = "rg_eth_mac_grp";
function = "rg_eth_mac";
};
};
rg_gmac_phy_intr_n_pmx: rg_gmac_phy_intr_n@0 {
rg_gmac_phy_intr_n {
groups = "rg_gmac_phy_intr_n_grp";
function = "rg_gmac_phy_intr_n";
};
};
rg_rgmii_mac_pmx: rg_rgmii_mac@0 {
rg_rgmii_mac {
groups = "rg_rgmii_mac_grp";
function = "rg_rgmii_mac";
};
};
rg_rgmii_phy_ref_clk_pmx0: rg_rgmii_phy_ref_clk@0 {
rg_rgmii_phy_ref_clk_0 {
groups =
"rg_rgmii_phy_ref_clk_grp0";
function =
"rg_rgmii_phy_ref_clk_m0";
};
};
rg_rgmii_phy_ref_clk_pmx1: rg_rgmii_phy_ref_clk@1 {
rg_rgmii_phy_ref_clk_1 {
groups =
"rg_rgmii_phy_ref_clk_grp1";
function =
"rg_rgmii_phy_ref_clk_m1";
};
};
sd0_pmx: sd0@0 {
sd0 {
groups = "sd0_grp";
function = "sd0";
};
};
sd0_4bit_pmx: sd0_4bit@0 {
sd0_4bit {
groups = "sd0_4bit_grp";
function = "sd0_4bit";
};
};
sd1_pmx: sd1@0 {
sd1 {
groups = "sd1_grp";
function = "sd1";
};
};
sd1_4bit_pmx0: sd1_4bit@0 {
sd1_4bit_0 {
groups = "sd1_4bit_grp0";
function = "sd1_4bit_m0";
};
};
sd1_4bit_pmx1: sd1_4bit@1 {
sd1_4bit_1 {
groups = "sd1_4bit_grp1";
function = "sd1_4bit_m1";
};
};
sd2_pmx0: sd2@0 {
sd2_0 {
groups = "sd2_grp0";
function = "sd2_m0";
};
};
sd2_no_cdb_pmx0: sd2_no_cdb@0 {
sd2_no_cdb_0 {
groups = "sd2_no_cdb_grp0";
function = "sd2_no_cdb_m0";
};
};
sd3_pmx: sd3@0 {
sd3 {
groups = "sd3_grp";
function = "sd3";
};
};
sd5_pmx: sd5@0 {
sd5 {
groups = "sd5_grp";
function = "sd5";
};
};
sd6_pmx0: sd6@0 {
sd6_0 {
groups = "sd6_grp0";
function = "sd6_m0";
};
};
sd6_pmx1: sd6@1 {
sd6_1 {
groups = "sd6_grp1";
function = "sd6_m1";
};
};
sp0_ext_ldo_on_pmx: sp0_ext_ldo_on@0 {
sp0_ext_ldo_on {
groups = "sp0_ext_ldo_on_grp";
function = "sp0_ext_ldo_on";
};
};
sp0_qspi_pmx: sp0_qspi@0 {
sp0_qspi {
groups = "sp0_qspi_grp";
function = "sp0_qspi";
};
};
sp1_spi_pmx: sp1_spi@0 {
sp1_spi {
groups = "sp1_spi_grp";
function = "sp1_spi";
};
};
tpiu_trace_pmx: tpiu_trace@0 {
tpiu_trace {
groups = "tpiu_trace_grp";
function = "tpiu_trace";
};
};
uart0_pmx: uart0@0 {
uart0 {
groups = "uart0_grp";
function = "uart0";
};
};
uart0_nopause_pmx: uart0_nopause@0 {
uart0_nopause {
groups = "uart0_nopause_grp";
function = "uart0_nopause";
};
};
uart1_pmx: uart1@0 {
uart1 {
groups = "uart1_grp";
function = "uart1";
};
};
uart2_pmx: uart2@0 {
uart2 {
groups = "uart2_grp";
function = "uart2";
};
};
uart3_pmx0: uart3@0 {
uart3_0 {
groups = "uart3_grp0";
function = "uart3_m0";
};
};
uart3_pmx1: uart3@1 {
uart3_1 {
groups = "uart3_grp1";
function = "uart3_m1";
};
};
uart3_pmx2: uart3@2 {
uart3_2 {
groups = "uart3_grp2";
function = "uart3_m2";
};
};
uart3_pmx3: uart3@3 {
uart3_3 {
groups = "uart3_grp3";
function = "uart3_m3";
};
};
uart3_nopause_pmx0: uart3_nopause@0 {
uart3_nopause_0 {
groups = "uart3_nopause_grp0";
function = "uart3_nopause_m0";
};
};
uart3_nopause_pmx1: uart3_nopause@1 {
uart3_nopause_1 {
groups = "uart3_nopause_grp1";
function = "uart3_nopause_m1";
};
};
uart4_pmx0: uart4@0 {
uart4_0 {
groups = "uart4_grp0";
function = "uart4_m0";
};
};
uart4_pmx1: uart4@1 {
uart4_1 {
groups = "uart4_grp1";
function = "uart4_m1";
};
};
uart4_pmx2: uart4@2 {
uart4_2 {
groups = "uart4_grp2";
function = "uart4_m2";
};
};
uart4_nopause_pmx: uart4_nopause@0 {
uart4_nopause {
groups = "uart4_nopause_grp";
function = "uart4_nopause";
};
};
usb0_drvvbus_pmx: usb0_drvvbus@0 {
usb0_drvvbus {
groups = "usb0_drvvbus_grp";
function = "usb0_drvvbus";
};
};
usb1_drvvbus_pmx: usb1_drvvbus@0 {
usb1_drvvbus {
groups = "usb1_drvvbus_grp";
function = "usb1_drvvbus";
};
};
visbus_dout_pmx: visbus_dout@0 {
visbus_dout {
groups = "visbus_dout_grp";
function = "visbus_dout";
};
};
vi_vip1_pmx: vi_vip1@0 {
vi_vip1 {
groups = "vi_vip1_grp";
function = "vi_vip1";
};
};
vi_vip1_ext_pmx: vi_vip1_ext@0 {
vi_vip1_ext {
groups = "vi_vip1_ext_grp";
function = "vi_vip1_ext";
};
};
vi_vip1_low8bit_pmx: vi_vip1_low8bit@0 {
vi_vip1_low8bit {
groups = "vi_vip1_low8bit_grp";
function = "vi_vip1_low8bit";
};
};
vi_vip1_high8bit_pmx: vi_vip1_high8bit@0 {
vi_vip1_high8bit {
groups = "vi_vip1_high8bit_grp";
function = "vi_vip1_high8bit";
};
};
}; };
pmipc { pmipc {
...@@ -356,6 +1375,12 @@ gpio_0: gpio_mediam@17040000 { ...@@ -356,6 +1375,12 @@ gpio_0: gpio_mediam@17040000 {
clock-names = "gpio0_io"; clock-names = "gpio0_io";
gpio-controller; gpio-controller;
interrupt-controller; interrupt-controller;
gpio-banks = <2>;
gpio-ranges = <&pinctrl 0 0 0>,
<&pinctrl 32 0 0>;
gpio-ranges-group-names = "lvds_gpio_grp",
"uart_nand_gpio_grp";
}; };
nand@17050000 { nand@17050000 {
...@@ -461,11 +1486,22 @@ gpio_1: gpio_vdifm@13300000 { ...@@ -461,11 +1486,22 @@ gpio_1: gpio_vdifm@13300000 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
compatible = "sirf,atlas7-gpio"; compatible = "sirf,atlas7-gpio";
reg = <0x13300000 0x1000>; reg = <0x13300000 0x1000>;
interrupts = <0 43 0>, <0 44 0>, <0 45 0>; interrupts = <0 43 0>, <0 44 0>,
<0 45 0>, <0 46 0>;
clocks = <&car 84>; clocks = <&car 84>;
clock-names = "gpio1_io"; clock-names = "gpio1_io";
gpio-controller; gpio-controller;
interrupt-controller; interrupt-controller;
gpio-banks = <4>;
gpio-ranges = <&pinctrl 0 0 0>,
<&pinctrl 32 0 0>,
<&pinctrl 64 0 0>,
<&pinctrl 96 0 0>;
gpio-ranges-group-names = "gnss_gpio_grp",
"lcd_vip_gpio_grp",
"sdio_i2s_gpio_grp",
"sp_rgmii_gpio_grp";
}; };
sd2: sdhci@14200000 { sd2: sdhci@14200000 {
...@@ -744,6 +1780,10 @@ gpio_2: gpio_rtcm@18890000 { ...@@ -744,6 +1780,10 @@ gpio_2: gpio_rtcm@18890000 {
interrupts = <0 47 0>; interrupts = <0 47 0>;
gpio-controller; gpio-controller;
interrupt-controller; interrupt-controller;
gpio-banks = <1>;
gpio-ranges = <&pinctrl 0 0 0>;
gpio-ranges-group-names = "rtc_gpio_grp";
}; };
rtc-iobg@18840000 { rtc-iobg@18840000 {
......
...@@ -150,6 +150,16 @@ cci_control2: slave-if@5000 { ...@@ -150,6 +150,16 @@ cci_control2: slave-if@5000 {
interface-type = "ace"; interface-type = "ace";
reg = <0x5000 0x1000>; reg = <0x5000 0x1000>;
}; };
pmu@9000 {
compatible = "arm,cci-400-pmu,r0";
reg = <0x9000 0x5000>;
interrupts = <0 105 4>,
<0 101 4>,
<0 102 4>,
<0 103 4>,
<0 104 4>;
};
}; };
memory-controller@7ffd0000 { memory-controller@7ffd0000 {
...@@ -187,11 +197,22 @@ timer { ...@@ -187,11 +197,22 @@ timer {
<1 10 0xf08>; <1 10 0xf08>;
}; };
pmu { pmu_a15 {
compatible = "arm,cortex-a15-pmu"; compatible = "arm,cortex-a15-pmu";
interrupts = <0 68 4>, interrupts = <0 68 4>,
<0 69 4>; <0 69 4>;
interrupt-affinity = <&cpu0>, <&cpu1>; interrupt-affinity = <&cpu0>,
<&cpu1>;
};
pmu_a7 {
compatible = "arm,cortex-a7-pmu";
interrupts = <0 128 4>,
<0 129 4>,
<0 130 4>;
interrupt-affinity = <&cpu2>,
<&cpu3>,
<&cpu4>;
}; };
oscclk6a: oscclk6a { oscclk6a: oscclk6a {
......
...@@ -353,7 +353,6 @@ CONFIG_POWER_RESET_AS3722=y ...@@ -353,7 +353,6 @@ CONFIG_POWER_RESET_AS3722=y
CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_POWER_RESET_KEYSTONE=y CONFIG_POWER_RESET_KEYSTONE=y
CONFIG_POWER_RESET_SUN6I=y
CONFIG_POWER_RESET_RMOBILE=y CONFIG_POWER_RESET_RMOBILE=y
CONFIG_SENSORS_LM90=y CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_LM95245=y CONFIG_SENSORS_LM95245=y
......
...@@ -2,6 +2,7 @@ CONFIG_NO_HZ=y ...@@ -2,6 +2,7 @@ CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y CONFIG_HIGH_RES_TIMERS=y
CONFIG_BLK_DEV_INITRD=y CONFIG_BLK_DEV_INITRD=y
CONFIG_PERF_EVENTS=y CONFIG_PERF_EVENTS=y
CONFIG_MODULES=y
CONFIG_ARCH_SUNXI=y CONFIG_ARCH_SUNXI=y
CONFIG_SMP=y CONFIG_SMP=y
CONFIG_NR_CPUS=8 CONFIG_NR_CPUS=8
...@@ -77,7 +78,6 @@ CONFIG_SPI_SUN6I=y ...@@ -77,7 +78,6 @@ CONFIG_SPI_SUN6I=y
CONFIG_GPIO_SYSFS=y CONFIG_GPIO_SYSFS=y
CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY=y
CONFIG_POWER_RESET=y CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SUN6I=y
CONFIG_THERMAL=y CONFIG_THERMAL=y
CONFIG_CPU_THERMAL=y CONFIG_CPU_THERMAL=y
CONFIG_WATCHDOG=y CONFIG_WATCHDOG=y
...@@ -87,6 +87,10 @@ CONFIG_REGULATOR=y ...@@ -87,6 +87,10 @@ CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_AXP20X=y CONFIG_REGULATOR_AXP20X=y
CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_GPIO=y
CONFIG_FB=y
CONFIG_FB_SIMPLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_USB_EHCI_HCD_PLATFORM=y
......
...@@ -117,7 +117,6 @@ static void omap2_show_dma_caps(void) ...@@ -117,7 +117,6 @@ static void omap2_show_dma_caps(void)
u8 revision = dma_read(REVISION, 0) & 0xff; u8 revision = dma_read(REVISION, 0) & 0xff;
printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
revision >> 4, revision & 0xf); revision >> 4, revision & 0xf);
return;
} }
static unsigned configure_dma_errata(void) static unsigned configure_dma_errata(void)
......
...@@ -4,6 +4,7 @@ menuconfig ARCH_SIRF ...@@ -4,6 +4,7 @@ menuconfig ARCH_SIRF
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
select GENERIC_IRQ_CHIP select GENERIC_IRQ_CHIP
select NO_IOPORT_MAP select NO_IOPORT_MAP
select REGMAP
select PINCTRL select PINCTRL
select PINCTRL_SIRF select PINCTRL_SIRF
help help
......
/* /*
* RTC I/O Bridge interfaces for CSR SiRFprimaII * RTC I/O Bridge interfaces for CSR SiRFprimaII/atlas7
* ARM access the registers of SYSRTC, GPSRTC and PWRC through this module * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module
* *
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/regmap.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/of_device.h> #include <linux/of_device.h>
...@@ -66,6 +67,7 @@ u32 sirfsoc_rtc_iobrg_readl(u32 addr) ...@@ -66,6 +67,7 @@ u32 sirfsoc_rtc_iobrg_readl(u32 addr)
{ {
unsigned long flags, val; unsigned long flags, val;
/* TODO: add hwspinlock to sync with M3 */
spin_lock_irqsave(&rtciobrg_lock, flags); spin_lock_irqsave(&rtciobrg_lock, flags);
val = __sirfsoc_rtc_iobrg_readl(addr); val = __sirfsoc_rtc_iobrg_readl(addr);
...@@ -90,6 +92,7 @@ void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr) ...@@ -90,6 +92,7 @@ void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr)
{ {
unsigned long flags; unsigned long flags;
/* TODO: add hwspinlock to sync with M3 */
spin_lock_irqsave(&rtciobrg_lock, flags); spin_lock_irqsave(&rtciobrg_lock, flags);
sirfsoc_rtc_iobrg_pre_writel(val, addr); sirfsoc_rtc_iobrg_pre_writel(val, addr);
...@@ -102,6 +105,45 @@ void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr) ...@@ -102,6 +105,45 @@ void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr)
} }
EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel); EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel);
static int regmap_iobg_regwrite(void *context, unsigned int reg,
unsigned int val)
{
sirfsoc_rtc_iobrg_writel(val, reg);
return 0;
}
static int regmap_iobg_regread(void *context, unsigned int reg,
unsigned int *val)
{
*val = (u32)sirfsoc_rtc_iobrg_readl(reg);
return 0;
}
static struct regmap_bus regmap_iobg = {
.reg_write = regmap_iobg_regwrite,
.reg_read = regmap_iobg_regread,
};
/**
* devm_regmap_init_iobg(): Initialise managed register map
*
* @iobg: Device that will be interacted with
* @config: Configuration for register map
*
* The return value will be an ERR_PTR() on error or a valid pointer
* to a struct regmap. The regmap will be automatically freed by the
* device management code.
*/
struct regmap *devm_regmap_init_iobg(struct device *dev,
const struct regmap_config *config)
{
const struct regmap_bus *bus = &regmap_iobg;
return devm_regmap_init(dev, bus, dev, config);
}
EXPORT_SYMBOL_GPL(devm_regmap_init_iobg);
static const struct of_device_id rtciobrg_ids[] = { static const struct of_device_id rtciobrg_ids[] = {
{ .compatible = "sirf,prima2-rtciobg" }, { .compatible = "sirf,prima2-rtciobg" },
{} {}
...@@ -132,7 +174,7 @@ static int __init sirfsoc_rtciobrg_init(void) ...@@ -132,7 +174,7 @@ static int __init sirfsoc_rtciobrg_init(void)
} }
postcore_initcall(sirfsoc_rtciobrg_init); postcore_initcall(sirfsoc_rtciobrg_init);
MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>, " MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>");
"Barry Song <baohua.song@csr.com>"); MODULE_AUTHOR("Barry Song <baohua.song@csr.com>");
MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge"); MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge");
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");
...@@ -35,7 +35,7 @@ config MACH_SUN7I ...@@ -35,7 +35,7 @@ config MACH_SUN7I
select SUN5I_HSTIMER select SUN5I_HSTIMER
config MACH_SUN8I config MACH_SUN8I
bool "Allwinner A23 (sun8i) SoCs support" bool "Allwinner sun8i Family SoCs support"
default ARCH_SUNXI default ARCH_SUNXI
select ARM_GIC select ARM_GIC
select MFD_SUN6I_PRCM select MFD_SUN6I_PRCM
......
...@@ -67,10 +67,13 @@ MACHINE_END ...@@ -67,10 +67,13 @@ MACHINE_END
static const char * const sun8i_board_dt_compat[] = { static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-a23", "allwinner,sun8i-a23",
"allwinner,sun8i-a33",
"allwinner,sun8i-h3",
NULL, NULL,
}; };
DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i (A23) Family") DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
.init_time = sun6i_timer_init,
.dt_compat = sun8i_board_dt_compat, .dt_compat = sun8i_board_dt_compat,
.init_late = sunxi_dt_cpufreq_init, .init_late = sunxi_dt_cpufreq_init,
MACHINE_END MACHINE_END
......
...@@ -23,6 +23,16 @@ memory { ...@@ -23,6 +23,16 @@ memory {
device_type = "memory"; device_type = "memory";
reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */ reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */
}; };
gpio-keys {
compatible = "gpio-keys";
button@1 {
label = "POWER";
linux,code = <116>;
linux,input-type = <0x1>;
interrupts = <0x0 0x2d 0x1>;
};
};
}; };
&pcie0clk { &pcie0clk {
......
dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
always := $(dtb-y) always := $(dtb-y)
subdir-y := $(dts-dirs) subdir-y := $(dts-dirs)
......
/*
* ARM Ltd. Versatile Express
*
* LogicTile Express 20MG
* V2F-1XV7
*
* Cortex-A53 (2 cores) Soft Macrocell Model
*
* HBI-0247C
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "V2F-1XV7 Cortex-A53x2 SMM";
arm,hbi = <0x247>;
arm,vexpress,site = <0xf>;
compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen {
stdout-path = "serial0:38400n8";
};
aliases {
serial0 = &v2m_serial0;
serial1 = &v2m_serial1;
serial2 = &v2m_serial2;
serial3 = &v2m_serial3;
i2c0 = &v2m_i2c_dvi;
i2c1 = &v2m_i2c_pcie;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0>;
next-level-cache = <&L2_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 1>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
};
gic: interrupt-controller@2c001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x2c001000 0 0x1000>,
<0 0x2c002000 0 0x2000>,
<0 0x2c004000 0 0x2000>,
<0 0x2c006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
};
dcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
smbclk: osc@4 {
/* SMC clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
freq-range = <40000000 40000000>;
#clock-cells = <0>;
clock-output-names = "smclk";
};
volt@0 {
/* VIO to expansion board above */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
regulator-name = "VIO_UP";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
volt@1 {
/* 12V from power connector J6 */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 1>;
regulator-name = "12";
regulator-always-on;
};
temp@0 {
/* FPGA temperature */
compatible = "arm,vexpress-temp";
arm,vexpress-sysreg,func = <4 0>;
label = "FPGA";
};
};
smb {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
/include/ "../../../../arm/boot/dts/vexpress-v2m-rs1.dtsi"
};
};
...@@ -376,10 +376,19 @@ refclk50mhz: refclk50mhz { ...@@ -376,10 +376,19 @@ refclk50mhz: refclk50mhz {
gic0: interrupt-controller@8010,00000000 { gic0: interrupt-controller@8010,00000000 {
compatible = "arm,gic-v3"; compatible = "arm,gic-v3";
#interrupt-cells = <3>; #interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller; interrupt-controller;
reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */ reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
<0x8010 0x80000000 0x0 0x600000>; /* GICR */ <0x8010 0x80000000 0x0 0x600000>; /* GICR */
interrupts = <1 9 0xf04>; interrupts = <1 9 0xf04>;
its: gic-its@8010,00020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x8010 0x20000 0x0 0x200000>;
};
}; };
uaa0: serial@87e0,24000000 { uaa0: serial@87e0,24000000 {
......
...@@ -1391,6 +1391,7 @@ static void __init sun6i_init_clocks(struct device_node *node) ...@@ -1391,6 +1391,7 @@ static void __init sun6i_init_clocks(struct device_node *node)
CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks); CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks); CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks); CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
static void __init sun9i_init_clocks(struct device_node *node) static void __init sun9i_init_clocks(struct device_node *node)
{ {
......
...@@ -2074,14 +2074,8 @@ static int gpmc_probe_dt(struct platform_device *pdev) ...@@ -2074,14 +2074,8 @@ static int gpmc_probe_dt(struct platform_device *pdev)
ret = gpmc_probe_nand_child(pdev, child); ret = gpmc_probe_nand_child(pdev, child);
else if (of_node_cmp(child->name, "onenand") == 0) else if (of_node_cmp(child->name, "onenand") == 0)
ret = gpmc_probe_onenand_child(pdev, child); ret = gpmc_probe_onenand_child(pdev, child);
else if (of_node_cmp(child->name, "ethernet") == 0 || else
of_node_cmp(child->name, "nor") == 0 ||
of_node_cmp(child->name, "uart") == 0)
ret = gpmc_probe_generic_child(pdev, child); ret = gpmc_probe_generic_child(pdev, child);
if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
__func__, child->full_name))
of_node_put(child);
} }
return 0; return 0;
......
...@@ -9,10 +9,14 @@ ...@@ -9,10 +9,14 @@
#ifndef _SIRFSOC_RTC_IOBRG_H_ #ifndef _SIRFSOC_RTC_IOBRG_H_
#define _SIRFSOC_RTC_IOBRG_H_ #define _SIRFSOC_RTC_IOBRG_H_
struct regmap_config;
extern void sirfsoc_rtc_iobrg_besyncing(void); extern void sirfsoc_rtc_iobrg_besyncing(void);
extern u32 sirfsoc_rtc_iobrg_readl(u32 addr); extern u32 sirfsoc_rtc_iobrg_readl(u32 addr);
extern void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr); extern void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr);
struct regmap *devm_regmap_init_iobg(struct device *dev,
const struct regmap_config *config);
#endif #endif
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