Commit 858e84a1 authored by Mark Brown's avatar Mark Brown

Merge remote-tracking branches 'asoc/topic/omap', 'asoc/topic/pxa',...

Merge remote-tracking branches 'asoc/topic/omap', 'asoc/topic/pxa', 'asoc/topic/rockchip' and 'asoc/topic/rt5514' into asoc-next
* Rockchip PDM controller
Required properties:
- compatible: "rockchip,pdm"
- reg: physical base address of the controller and length of memory mapped
region.
- dmas: DMA specifiers for rx dma. See the DMA client binding,
Documentation/devicetree/bindings/dma/dma.txt
- dma-names: should include "rx".
- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
- clock-names: should contain following:
- "pdm_hclk": clock for PDM BUS
- "pdm_clk" : clock for PDM controller
- pinctrl-names: Must contain a "default" entry.
- pinctrl-N: One property must exist for each entry in
pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
for details of the property values.
Example for rk3328 PDM controller:
pdm: pdm@ff040000 {
compatible = "rockchip,pdm";
reg = <0x0 0xff040000 0x0 0x1000>;
clocks = <&clk_pdm>, <&clk_gates28 0>;
clock-names = "pdm_clk", "pdm_hclk";
dmas = <&pdma 16>;
#dma-cells = <1>;
dma-names = "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pdmm0_clk
&pdmm0_fsync
&pdmm0_sdi0
&pdmm0_sdi1
&pdmm0_sdi2
&pdmm0_sdi3>;
pinctrl-1 = <&pdmm0_sleep>;
status = "disabled";
};
...@@ -9,7 +9,9 @@ Required properties: ...@@ -9,7 +9,9 @@ Required properties:
- compatible: should be one of the following: - compatible: should be one of the following:
- "rockchip,rk3066-spdif" - "rockchip,rk3066-spdif"
- "rockchip,rk3188-spdif" - "rockchip,rk3188-spdif"
- "rockchip,rk3228-spdif"
- "rockchip,rk3288-spdif" - "rockchip,rk3288-spdif"
- "rockchip,rk3328-spdif"
- "rockchip,rk3366-spdif" - "rockchip,rk3366-spdif"
- "rockchip,rk3368-spdif" - "rockchip,rk3368-spdif"
- "rockchip,rk3399-spdif" - "rockchip,rk3399-spdif"
......
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#include <linux/acpi.h>
#include <linux/fs.h> #include <linux/fs.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/moduleparam.h> #include <linux/moduleparam.h>
...@@ -906,9 +907,23 @@ static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, ...@@ -906,9 +907,23 @@ static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
if (rx_mask || tx_mask) if (rx_mask || tx_mask)
val |= RT5514_TDM_MODE; val |= RT5514_TDM_MODE;
if (slots == 4) switch (slots) {
case 4:
val |= RT5514_TDMSLOT_SEL_RX_4CH | RT5514_TDMSLOT_SEL_TX_4CH; val |= RT5514_TDMSLOT_SEL_RX_4CH | RT5514_TDMSLOT_SEL_TX_4CH;
break;
case 6:
val |= RT5514_TDMSLOT_SEL_RX_6CH | RT5514_TDMSLOT_SEL_TX_6CH;
break;
case 8:
val |= RT5514_TDMSLOT_SEL_RX_8CH | RT5514_TDMSLOT_SEL_TX_8CH;
break;
case 2:
default:
break;
}
switch (slot_width) { switch (slot_width) {
case 20: case 20:
...@@ -919,6 +934,10 @@ static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, ...@@ -919,6 +934,10 @@ static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
val |= RT5514_CH_LEN_RX_24 | RT5514_CH_LEN_TX_24; val |= RT5514_CH_LEN_RX_24 | RT5514_CH_LEN_TX_24;
break; break;
case 25:
val |= RT5514_TDM_MODE2;
break;
case 32: case 32:
val |= RT5514_CH_LEN_RX_32 | RT5514_CH_LEN_TX_32; val |= RT5514_CH_LEN_RX_32 | RT5514_CH_LEN_TX_32;
break; break;
...@@ -930,7 +949,8 @@ static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, ...@@ -930,7 +949,8 @@ static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_TDM_MODE | regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_TDM_MODE |
RT5514_TDMSLOT_SEL_RX_MASK | RT5514_TDMSLOT_SEL_TX_MASK | RT5514_TDMSLOT_SEL_RX_MASK | RT5514_TDMSLOT_SEL_TX_MASK |
RT5514_CH_LEN_RX_MASK | RT5514_CH_LEN_TX_MASK, val); RT5514_CH_LEN_RX_MASK | RT5514_CH_LEN_TX_MASK |
RT5514_TDM_MODE2, val);
return 0; return 0;
} }
...@@ -1076,6 +1096,14 @@ static const struct of_device_id rt5514_of_match[] = { ...@@ -1076,6 +1096,14 @@ static const struct of_device_id rt5514_of_match[] = {
MODULE_DEVICE_TABLE(of, rt5514_of_match); MODULE_DEVICE_TABLE(of, rt5514_of_match);
#endif #endif
#ifdef CONFIG_ACPI
static struct acpi_device_id rt5514_acpi_match[] = {
{ "10EC5514", 0},
{},
};
MODULE_DEVICE_TABLE(acpi, rt5514_acpi_match);
#endif
static int rt5514_parse_dt(struct rt5514_priv *rt5514, struct device *dev) static int rt5514_parse_dt(struct rt5514_priv *rt5514, struct device *dev)
{ {
device_property_read_u32(dev, "realtek,dmic-init-delay-ms", device_property_read_u32(dev, "realtek,dmic-init-delay-ms",
...@@ -1179,6 +1207,7 @@ static const struct dev_pm_ops rt5514_i2_pm_ops = { ...@@ -1179,6 +1207,7 @@ static const struct dev_pm_ops rt5514_i2_pm_ops = {
static struct i2c_driver rt5514_i2c_driver = { static struct i2c_driver rt5514_i2c_driver = {
.driver = { .driver = {
.name = "rt5514", .name = "rt5514",
.acpi_match_table = ACPI_PTR(rt5514_acpi_match),
.of_match_table = of_match_ptr(rt5514_of_match), .of_match_table = of_match_ptr(rt5514_of_match),
.pm = &rt5514_i2_pm_ops, .pm = &rt5514_i2_pm_ops,
}, },
......
...@@ -117,6 +117,8 @@ ...@@ -117,6 +117,8 @@
#define RT5514_POW_ADCFEDL_BIT 0 #define RT5514_POW_ADCFEDL_BIT 0
/* RT5514_I2S_CTRL1 (0x2010) */ /* RT5514_I2S_CTRL1 (0x2010) */
#define RT5514_TDM_MODE2 (0x1 << 30)
#define RT5514_TDM_MODE2_SFT 30
#define RT5514_TDM_MODE (0x1 << 28) #define RT5514_TDM_MODE (0x1 << 28)
#define RT5514_TDM_MODE_SFT 28 #define RT5514_TDM_MODE_SFT 28
#define RT5514_I2S_LR_MASK (0x1 << 26) #define RT5514_I2S_LR_MASK (0x1 << 26)
...@@ -136,6 +138,8 @@ ...@@ -136,6 +138,8 @@
#define RT5514_TDMSLOT_SEL_RX_MASK (0x3 << 10) #define RT5514_TDMSLOT_SEL_RX_MASK (0x3 << 10)
#define RT5514_TDMSLOT_SEL_RX_SFT 10 #define RT5514_TDMSLOT_SEL_RX_SFT 10
#define RT5514_TDMSLOT_SEL_RX_4CH (0x1 << 10) #define RT5514_TDMSLOT_SEL_RX_4CH (0x1 << 10)
#define RT5514_TDMSLOT_SEL_RX_6CH (0x2 << 10)
#define RT5514_TDMSLOT_SEL_RX_8CH (0x3 << 10)
#define RT5514_CH_LEN_RX_MASK (0x3 << 8) #define RT5514_CH_LEN_RX_MASK (0x3 << 8)
#define RT5514_CH_LEN_RX_SFT 8 #define RT5514_CH_LEN_RX_SFT 8
#define RT5514_CH_LEN_RX_16 (0x0 << 8) #define RT5514_CH_LEN_RX_16 (0x0 << 8)
...@@ -145,6 +149,8 @@ ...@@ -145,6 +149,8 @@
#define RT5514_TDMSLOT_SEL_TX_MASK (0x3 << 6) #define RT5514_TDMSLOT_SEL_TX_MASK (0x3 << 6)
#define RT5514_TDMSLOT_SEL_TX_SFT 6 #define RT5514_TDMSLOT_SEL_TX_SFT 6
#define RT5514_TDMSLOT_SEL_TX_4CH (0x1 << 6) #define RT5514_TDMSLOT_SEL_TX_4CH (0x1 << 6)
#define RT5514_TDMSLOT_SEL_TX_6CH (0x2 << 6)
#define RT5514_TDMSLOT_SEL_TX_8CH (0x3 << 6)
#define RT5514_CH_LEN_TX_MASK (0x3 << 4) #define RT5514_CH_LEN_TX_MASK (0x3 << 4)
#define RT5514_CH_LEN_TX_SFT 4 #define RT5514_CH_LEN_TX_SFT 4
#define RT5514_CH_LEN_TX_16 (0x0 << 4) #define RT5514_CH_LEN_TX_16 (0x0 << 4)
......
...@@ -835,15 +835,11 @@ static ssize_t dma_op_mode_store(struct device *dev, ...@@ -835,15 +835,11 @@ static ssize_t dma_op_mode_store(struct device *dev,
const char *buf, size_t size) const char *buf, size_t size)
{ {
struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
const char * const *s; int i;
int i = 0;
for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
if (sysfs_streq(buf, *s))
break;
if (i == ARRAY_SIZE(dma_op_modes)) i = sysfs_match_string(dma_op_modes, buf);
return -EINVAL; if (i < 0)
return i;
spin_lock_irq(&mcbsp->lock); spin_lock_irq(&mcbsp->lock);
if (!mcbsp->free) { if (!mcbsp->free) {
......
config SND_PXA2XX_SOC config SND_PXA2XX_SOC
tristate "SoC Audio for the Intel PXA2xx chip" tristate "SoC Audio for the Intel PXA2xx chip"
depends on ARCH_PXA depends on ARCH_PXA || COMPILE_TEST
select SND_PXA2XX_LIB select SND_PXA2XX_LIB
help help
Say Y or M if you want to add support for codecs attached to Say Y or M if you want to add support for codecs attached to
......
...@@ -15,6 +15,15 @@ config SND_SOC_ROCKCHIP_I2S ...@@ -15,6 +15,15 @@ config SND_SOC_ROCKCHIP_I2S
Rockchip I2S device. The device supports upto maximum of Rockchip I2S device. The device supports upto maximum of
8 channels each for play and record. 8 channels each for play and record.
config SND_SOC_ROCKCHIP_PDM
tristate "Rockchip PDM Controller Driver"
depends on CLKDEV_LOOKUP && SND_SOC_ROCKCHIP
select SND_SOC_GENERIC_DMAENGINE_PCM
help
Say Y or M if you want to add support for PDM driver for
Rockchip PDM Controller. The Controller supports up to maximum of
8 channels record.
config SND_SOC_ROCKCHIP_SPDIF config SND_SOC_ROCKCHIP_SPDIF
tristate "Rockchip SPDIF Device Driver" tristate "Rockchip SPDIF Device Driver"
depends on CLKDEV_LOOKUP && SND_SOC_ROCKCHIP depends on CLKDEV_LOOKUP && SND_SOC_ROCKCHIP
......
# ROCKCHIP Platform Support # ROCKCHIP Platform Support
snd-soc-rockchip-i2s-objs := rockchip_i2s.o snd-soc-rockchip-i2s-objs := rockchip_i2s.o
snd-soc-rockchip-pdm-objs := rockchip_pdm.o
snd-soc-rockchip-spdif-objs := rockchip_spdif.o snd-soc-rockchip-spdif-objs := rockchip_spdif.o
obj-$(CONFIG_SND_SOC_ROCKCHIP_I2S) += snd-soc-rockchip-i2s.o obj-$(CONFIG_SND_SOC_ROCKCHIP_I2S) += snd-soc-rockchip-i2s.o
obj-$(CONFIG_SND_SOC_ROCKCHIP_PDM) += snd-soc-rockchip-pdm.o
obj-$(CONFIG_SND_SOC_ROCKCHIP_SPDIF) += snd-soc-rockchip-spdif.o obj-$(CONFIG_SND_SOC_ROCKCHIP_SPDIF) += snd-soc-rockchip-spdif.o
snd-soc-rockchip-max98090-objs := rockchip_max98090.o snd-soc-rockchip-max98090-objs := rockchip_max98090.o
......
...@@ -206,7 +206,21 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, ...@@ -206,7 +206,21 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
mask = I2S_TXCR_IBM_MASK; mask = I2S_CKR_CKP_MASK;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
val = I2S_CKR_CKP_NEG;
break;
case SND_SOC_DAIFMT_IB_NF:
val = I2S_CKR_CKP_POS;
break;
default:
return -EINVAL;
}
regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J: case SND_SOC_DAIFMT_RIGHT_J:
val = I2S_TXCR_IBM_RSJM; val = I2S_TXCR_IBM_RSJM;
...@@ -217,13 +231,19 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, ...@@ -217,13 +231,19 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
case SND_SOC_DAIFMT_I2S: case SND_SOC_DAIFMT_I2S:
val = I2S_TXCR_IBM_NORMAL; val = I2S_TXCR_IBM_NORMAL;
break; break;
case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
val = I2S_TXCR_TFS_PCM;
break;
case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
break;
default: default:
return -EINVAL; return -EINVAL;
} }
regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val); regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
mask = I2S_RXCR_IBM_MASK; mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J: case SND_SOC_DAIFMT_RIGHT_J:
val = I2S_RXCR_IBM_RSJM; val = I2S_RXCR_IBM_RSJM;
...@@ -234,6 +254,12 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, ...@@ -234,6 +254,12 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
case SND_SOC_DAIFMT_I2S: case SND_SOC_DAIFMT_I2S:
val = I2S_RXCR_IBM_NORMAL; val = I2S_RXCR_IBM_NORMAL;
break; break;
case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
val = I2S_RXCR_TFS_PCM;
break;
case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
break;
default: default:
return -EINVAL; return -EINVAL;
} }
...@@ -617,12 +643,13 @@ static int rockchip_i2s_probe(struct platform_device *pdev) ...@@ -617,12 +643,13 @@ static int rockchip_i2s_probe(struct platform_device *pdev)
goto err_pm_disable; goto err_pm_disable;
} }
soc_dai = devm_kzalloc(&pdev->dev, soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_dai,
sizeof(*soc_dai), GFP_KERNEL); sizeof(*soc_dai), GFP_KERNEL);
if (!soc_dai) if (!soc_dai) {
return -ENOMEM; ret = -ENOMEM;
goto err_pm_disable;
}
memcpy(soc_dai, &rockchip_i2s_dai, sizeof(*soc_dai));
if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) { if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
if (val >= 2 && val <= 8) if (val >= 2 && val <= 8)
soc_dai->playback.channels_max = val; soc_dai->playback.channels_max = val;
......
...@@ -41,6 +41,7 @@ ...@@ -41,6 +41,7 @@
#define I2S_TXCR_TFS_SHIFT 5 #define I2S_TXCR_TFS_SHIFT 5
#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT) #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT) #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
#define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT)
#define I2S_TXCR_VDW_SHIFT 0 #define I2S_TXCR_VDW_SHIFT 0
#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT) #define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT) #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
...@@ -70,6 +71,7 @@ ...@@ -70,6 +71,7 @@
#define I2S_RXCR_TFS_SHIFT 5 #define I2S_RXCR_TFS_SHIFT 5
#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT) #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT) #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
#define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT)
#define I2S_RXCR_VDW_SHIFT 0 #define I2S_RXCR_VDW_SHIFT 0
#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT) #define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT) #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
...@@ -91,6 +93,7 @@ ...@@ -91,6 +93,7 @@
#define I2S_CKR_CKP_SHIFT 26 #define I2S_CKR_CKP_SHIFT 26
#define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT) #define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT)
#define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT) #define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT)
#define I2S_CKR_CKP_MASK (1 << I2S_CKR_CKP_SHIFT)
#define I2S_CKR_RLP_SHIFT 25 #define I2S_CKR_RLP_SHIFT 25
#define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT) #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)
#define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT) #define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT)
......
This diff is collapsed.
/*
* Rockchip PDM ALSA SoC Digital Audio Interface(DAI) driver
*
* Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _ROCKCHIP_PDM_H
#define _ROCKCHIP_PDM_H
/* PDM REGS */
#define PDM_SYSCONFIG (0x0000)
#define PDM_CTRL0 (0x0004)
#define PDM_CTRL1 (0x0008)
#define PDM_CLK_CTRL (0x000c)
#define PDM_HPF_CTRL (0x0010)
#define PDM_FIFO_CTRL (0x0014)
#define PDM_DMA_CTRL (0x0018)
#define PDM_INT_EN (0x001c)
#define PDM_INT_CLR (0x0020)
#define PDM_INT_ST (0x0024)
#define PDM_RXFIFO_DATA (0x0030)
#define PDM_DATA_VALID (0x0054)
#define PDM_VERSION (0x0058)
/* PDM_SYSCONFIG */
#define PDM_RX_MASK (0x1 << 2)
#define PDM_RX_START (0x1 << 2)
#define PDM_RX_STOP (0x0 << 2)
#define PDM_RX_CLR_MASK (0x1 << 0)
#define PDM_RX_CLR_WR (0x1 << 0)
#define PDM_RX_CLR_DONE (0x0 << 0)
/* PDM CTRL0 */
#define PDM_PATH_MSK (0xf << 27)
#define PDM_PATH3_EN BIT(30)
#define PDM_PATH2_EN BIT(29)
#define PDM_PATH1_EN BIT(28)
#define PDM_PATH0_EN BIT(27)
#define PDM_HWT_EN BIT(26)
#define PDM_VDW_MSK (0x1f << 0)
#define PDM_VDW(X) ((X - 1) << 0)
/* PDM CLK CTRL */
#define PDM_CLK_MSK BIT(5)
#define PDM_CLK_EN BIT(5)
#define PDM_CLK_DIS (0x0 << 5)
#define PDM_CKP_MSK BIT(3)
#define PDM_CKP_NORMAL (0x0 << 3)
#define PDM_CKP_INVERTED BIT(3)
#define PDM_DS_RATIO_MSK (0x7 << 0)
#define PDM_CLK_320FS (0x0 << 0)
#define PDM_CLK_640FS (0x1 << 0)
#define PDM_CLK_1280FS (0x2 << 0)
#define PDM_CLK_2560FS (0x3 << 0)
#define PDM_CLK_5120FS (0x4 << 0)
/* PDM HPF CTRL */
#define PDM_HPF_LE BIT(3)
#define PDM_HPF_RE BIT(2)
#define PDM_HPF_CF_MSK (0x3 << 0)
#define PDM_HPF_3P79HZ (0x0 << 0)
#define PDM_HPF_60HZ (0x1 << 0)
#define PDM_HPF_243HZ (0x2 << 0)
#define PDM_HPF_493HZ (0x3 << 0)
/* PDM DMA CTRL */
#define PDM_DMA_RD_MSK BIT(8)
#define PDM_DMA_RD_EN BIT(8)
#define PDM_DMA_RD_DIS (0x0 << 8)
#define PDM_DMA_RDL_MSK (0x7f << 0)
#define PDM_DMA_RDL(X) ((X - 1) << 0)
#endif /* _ROCKCHIP_PDM_H */
...@@ -49,8 +49,12 @@ static const struct of_device_id rk_spdif_match[] = { ...@@ -49,8 +49,12 @@ static const struct of_device_id rk_spdif_match[] = {
.data = (void *)RK_SPDIF_RK3066 }, .data = (void *)RK_SPDIF_RK3066 },
{ .compatible = "rockchip,rk3188-spdif", { .compatible = "rockchip,rk3188-spdif",
.data = (void *)RK_SPDIF_RK3188 }, .data = (void *)RK_SPDIF_RK3188 },
{ .compatible = "rockchip,rk3228-spdif",
.data = (void *)RK_SPDIF_RK3366 },
{ .compatible = "rockchip,rk3288-spdif", { .compatible = "rockchip,rk3288-spdif",
.data = (void *)RK_SPDIF_RK3288 }, .data = (void *)RK_SPDIF_RK3288 },
{ .compatible = "rockchip,rk3328-spdif",
.data = (void *)RK_SPDIF_RK3366 },
{ .compatible = "rockchip,rk3366-spdif", { .compatible = "rockchip,rk3366-spdif",
.data = (void *)RK_SPDIF_RK3366 }, .data = (void *)RK_SPDIF_RK3366 },
{ .compatible = "rockchip,rk3368-spdif", { .compatible = "rockchip,rk3368-spdif",
......
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