Commit 86bfa5ea authored by Jeff Garzik's avatar Jeff Garzik

Update starfire and tulip net drivers to use new PCI API functions

pci_set_mwi and pci_clear_mwi.
parent 018a69a1
...@@ -96,9 +96,10 @@ ...@@ -96,9 +96,10 @@
LK1.3.5 (jgarzik) LK1.3.5 (jgarzik)
- ethtool NWAY_RST, GLINK, [GS]MSGLVL support - ethtool NWAY_RST, GLINK, [GS]MSGLVL support
LK1.3.6 (Ion Badulescu) LK1.3.6:
- Sparc64 support and fixes - Sparc64 support and fixes (Ion Badulescu)
- Better stats and error handling - Better stats and error handling (Ion Badulescu)
- Use new pci_set_mwi() PCI API function (jgarzik)
TODO: TODO:
- implement tx_timeout() properly - implement tx_timeout() properly
...@@ -107,7 +108,7 @@ ...@@ -107,7 +108,7 @@
#define DRV_NAME "starfire" #define DRV_NAME "starfire"
#define DRV_VERSION "1.03+LK1.3.6" #define DRV_VERSION "1.03+LK1.3.6"
#define DRV_RELDATE "March 6, 2002" #define DRV_RELDATE "March 7, 2002"
#include <linux/version.h> #include <linux/version.h>
#include <linux/module.h> #include <linux/module.h>
...@@ -617,8 +618,10 @@ static int __devinit starfire_init_one(struct pci_dev *pdev, ...@@ -617,8 +618,10 @@ static int __devinit starfire_init_one(struct pci_dev *pdev,
long ioaddr; long ioaddr;
int drv_flags, io_size; int drv_flags, io_size;
int boguscnt; int boguscnt;
#ifndef HAVE_PCI_SET_MWI
u16 cmd; u16 cmd;
u8 cache; u8 cache;
#endif
/* when built into the kernel, we only print version if device is found */ /* when built into the kernel, we only print version if device is found */
#ifndef MODULE #ifndef MODULE
...@@ -665,6 +668,9 @@ static int __devinit starfire_init_one(struct pci_dev *pdev, ...@@ -665,6 +668,9 @@ static int __devinit starfire_init_one(struct pci_dev *pdev,
pci_set_master(pdev); pci_set_master(pdev);
#ifdef HAVE_PCI_SET_MWI
pci_set_mwi(pdev);
#else
/* enable MWI -- it vastly improves Rx performance on sparc64 */ /* enable MWI -- it vastly improves Rx performance on sparc64 */
pci_read_config_word(pdev, PCI_COMMAND, &cmd); pci_read_config_word(pdev, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_INVALIDATE; cmd |= PCI_COMMAND_INVALIDATE;
...@@ -679,6 +685,7 @@ static int __devinit starfire_init_one(struct pci_dev *pdev, ...@@ -679,6 +685,7 @@ static int __devinit starfire_init_one(struct pci_dev *pdev,
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
SMP_CACHE_BYTES >> 2); SMP_CACHE_BYTES >> 2);
} }
#endif
#ifdef ZEROCOPY #ifdef ZEROCOPY
/* Starfire can do SG and TCP/UDP checksumming */ /* Starfire can do SG and TCP/UDP checksumming */
......
2002-03-07 Jeff Garzik <jgarzik@mandrakesoft.com>
* tulip_core (tulip_mwi_config): Use new PCI API functions
for enabling and disabled Memory-Write-Invalidate
PCI transaction.
Fix bugs in tulip MWI config also.
2002-01-28 Stefan Rompf <srompf@isg.de>, 2002-01-28 Stefan Rompf <srompf@isg.de>,
Jeff Garzik <jgarzik@mandrakesoft.com> Jeff Garzik <jgarzik@mandrakesoft.com>
......
...@@ -15,8 +15,8 @@ ...@@ -15,8 +15,8 @@
*/ */
#define DRV_NAME "tulip" #define DRV_NAME "tulip"
#define DRV_VERSION "1.1.11" #define DRV_VERSION "1.1.12"
#define DRV_RELDATE "Feb 08, 2002" #define DRV_RELDATE "Mar 07, 2002"
#include <linux/config.h> #include <linux/config.h>
#include <linux/module.h> #include <linux/module.h>
...@@ -1164,7 +1164,7 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev, ...@@ -1164,7 +1164,7 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev,
{ {
struct tulip_private *tp = dev->priv; struct tulip_private *tp = dev->priv;
u8 cache; u8 cache;
u16 pci_command, new_command; u16 pci_command;
u32 csr0; u32 csr0;
if (tulip_debug > 3) if (tulip_debug > 3)
...@@ -1172,24 +1172,6 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev, ...@@ -1172,24 +1172,6 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev,
tp->csr0 = csr0 = 0; tp->csr0 = csr0 = 0;
/* check for sane cache line size. from acenic.c. */
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
if ((cache << 2) != SMP_CACHE_BYTES) {
printk(KERN_WARNING "%s: PCI cache line size set incorrectly "
"(%i bytes) by BIOS/FW, correcting to %i\n",
pdev->slot_name, (cache << 2), SMP_CACHE_BYTES);
pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
SMP_CACHE_BYTES >> 2);
udelay(5);
}
/* read cache line size again, hardware may not have accepted
* our cache line size change
*/
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
if (!cache)
goto out;
/* if we have any cache line size at all, we can do MRM */ /* if we have any cache line size at all, we can do MRM */
csr0 |= MRM; csr0 |= MRM;
...@@ -1200,15 +1182,19 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev, ...@@ -1200,15 +1182,19 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev,
/* set or disable MWI in the standard PCI command bit. /* set or disable MWI in the standard PCI command bit.
* Check for the case where mwi is desired but not available * Check for the case where mwi is desired but not available
*/ */
pci_read_config_word(pdev, PCI_COMMAND, &pci_command); if (csr0 & MWI) pci_set_mwi(pdev);
if (csr0 & MWI) new_command = pci_command | PCI_COMMAND_INVALIDATE; else pci_clear_mwi(pdev);
else new_command = pci_command & ~PCI_COMMAND_INVALIDATE;
if (new_command != pci_command) { /* read result from hardware (in case bit refused to enable) */
pci_write_config_word(pdev, PCI_COMMAND, new_command);
udelay(5);
pci_read_config_word(pdev, PCI_COMMAND, &pci_command); pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE))) if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
csr0 &= ~MWI; csr0 &= ~MWI;
/* if cache line size hardwired to zero, no MWI */
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
if ((csr0 & MWI) && (cache == 0)) {
csr0 &= ~MWI;
pci_clear_mwi(pdev);
} }
/* assign per-cacheline-size cache alignment and /* assign per-cacheline-size cache alignment and
...@@ -1225,20 +1211,29 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev, ...@@ -1225,20 +1211,29 @@ static void __devinit tulip_mwi_config (struct pci_dev *pdev,
csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift); csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
break; break;
default: default:
goto out; cache = 0;
break;
} }
tp->csr0 = csr0; /* if we have a good cache line size, we by now have a good
* csr0, so save it and exit
*/
if (cache)
goto out; goto out;
/* we don't have a good csr0 or cache line size, disable MWI */
if (csr0 & MWI) { if (csr0 & MWI) {
pci_command &= ~PCI_COMMAND_INVALIDATE; pci_clear_mwi(pdev);
pci_write_config_word(pdev, PCI_COMMAND, pci_command);
csr0 &= ~MWI; csr0 &= ~MWI;
} }
tp->csr0 = csr0 | (8 << BurstLenShift) | (1 << CALShift);
/* sane defaults for burst length and cache alignment
* originally from de4x5 driver
*/
csr0 |= (8 << BurstLenShift) | (1 << CALShift);
out: out:
tp->csr0 = csr0;
if (tulip_debug > 2) if (tulip_debug > 2)
printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n", printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
pdev->slot_name, cache, csr0); pdev->slot_name, cache, csr0);
......
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