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Commit 87dc3464 authored by Shannon Nelson's avatar Shannon Nelson Committed by Jeff Kirsher
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i40e/i40evf: Add base address registers to aq struct 

Add the Base Address High and Low to the admin queue struct to simplify
another bit of "which context" logic in the config routines.

Change-ID: Iae195a7da3baffc1a9d522119e1e2b427068ad07
Signed-off-by: default avatarShannon Nelson <shannon.nelson@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 4135ab82
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Showing with 44 additions and 76 deletions
drivers/net/ethernet/intel/i40e/i40e_adminq.c
View file @ 87dc3464
...@@ -55,16 +55,24 @@ static void i40e_adminq_init_regs(struct i40e_hw *hw) ...@@ -55,16 +55,24 @@ static void i40e_adminq_init_regs(struct i40e_hw *hw)
hw->aq.asq.tail = I40E_VF_ATQT1; hw->aq.asq.tail = I40E_VF_ATQT1;
hw->aq.asq.head = I40E_VF_ATQH1; hw->aq.asq.head = I40E_VF_ATQH1;
hw->aq.asq.len = I40E_VF_ATQLEN1; hw->aq.asq.len = I40E_VF_ATQLEN1;
hw->aq.asq.bal = I40E_VF_ATQBAL1;
hw->aq.asq.bah = I40E_VF_ATQBAH1;
hw->aq.arq.tail = I40E_VF_ARQT1; hw->aq.arq.tail = I40E_VF_ARQT1;
hw->aq.arq.head = I40E_VF_ARQH1; hw->aq.arq.head = I40E_VF_ARQH1;
hw->aq.arq.len = I40E_VF_ARQLEN1; hw->aq.arq.len = I40E_VF_ARQLEN1;
hw->aq.arq.bal = I40E_VF_ARQBAL1;
hw->aq.arq.bah = I40E_VF_ARQBAH1;
} else { } else {
hw->aq.asq.tail = I40E_PF_ATQT; hw->aq.asq.tail = I40E_PF_ATQT;
hw->aq.asq.head = I40E_PF_ATQH; hw->aq.asq.head = I40E_PF_ATQH;
hw->aq.asq.len = I40E_PF_ATQLEN; hw->aq.asq.len = I40E_PF_ATQLEN;
hw->aq.asq.bal = I40E_PF_ATQBAL;
hw->aq.asq.bah = I40E_PF_ATQBAH;
hw->aq.arq.tail = I40E_PF_ARQT; hw->aq.arq.tail = I40E_PF_ARQT;
hw->aq.arq.head = I40E_PF_ARQH; hw->aq.arq.head = I40E_PF_ARQH;
hw->aq.arq.len = I40E_PF_ARQLEN; hw->aq.arq.len = I40E_PF_ARQLEN;
hw->aq.arq.bal = I40E_PF_ARQBAL;
hw->aq.arq.bah = I40E_PF_ARQBAH;
} }
} }
...@@ -300,27 +308,14 @@ static i40e_status i40e_config_asq_regs(struct i40e_hw *hw) ...@@ -300,27 +308,14 @@ static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
wr32(hw, hw->aq.asq.head, 0); wr32(hw, hw->aq.asq.head, 0);
wr32(hw, hw->aq.asq.tail, 0); wr32(hw, hw->aq.asq.tail, 0);
if (hw->mac.type == I40E_MAC_VF) { /* set starting point */
/* configure the transmit queue */ wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
wr32(hw, I40E_VF_ATQBAH1, I40E_PF_ATQLEN_ATQENABLE_MASK));
upper_32_bits(hw->aq.asq.desc_buf.pa)); wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
wr32(hw, I40E_VF_ATQBAL1, wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
lower_32_bits(hw->aq.asq.desc_buf.pa));
wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries |
I40E_VF_ATQLEN1_ATQENABLE_MASK));
reg = rd32(hw, I40E_VF_ATQBAL1);
} else {
/* configure the transmit queue */
wr32(hw, I40E_PF_ATQBAH,
upper_32_bits(hw->aq.asq.desc_buf.pa));
wr32(hw, I40E_PF_ATQBAL,
lower_32_bits(hw->aq.asq.desc_buf.pa));
wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
I40E_PF_ATQLEN_ATQENABLE_MASK));
reg = rd32(hw, I40E_PF_ATQBAL);
}
/* Check one register to verify that config was applied */ /* Check one register to verify that config was applied */
reg = rd32(hw, hw->aq.asq.bal);
if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
...@@ -342,30 +337,17 @@ static i40e_status i40e_config_arq_regs(struct i40e_hw *hw) ...@@ -342,30 +337,17 @@ static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
wr32(hw, hw->aq.arq.head, 0); wr32(hw, hw->aq.arq.head, 0);
wr32(hw, hw->aq.arq.tail, 0); wr32(hw, hw->aq.arq.tail, 0);
if (hw->mac.type == I40E_MAC_VF) { /* set starting point */
/* configure the receive queue */ wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
wr32(hw, I40E_VF_ARQBAH1, I40E_PF_ARQLEN_ARQENABLE_MASK));
upper_32_bits(hw->aq.arq.desc_buf.pa)); wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
wr32(hw, I40E_VF_ARQBAL1, wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
lower_32_bits(hw->aq.arq.desc_buf.pa));
wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries |
I40E_VF_ARQLEN1_ARQENABLE_MASK));
reg = rd32(hw, I40E_VF_ARQBAL1);
} else {
/* configure the receive queue */
wr32(hw, I40E_PF_ARQBAH,
upper_32_bits(hw->aq.arq.desc_buf.pa));
wr32(hw, I40E_PF_ARQBAL,
lower_32_bits(hw->aq.arq.desc_buf.pa));
wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
I40E_PF_ARQLEN_ARQENABLE_MASK));
reg = rd32(hw, I40E_PF_ARQBAL);
}
/* Update tail in the HW to post pre-allocated buffers */ /* Update tail in the HW to post pre-allocated buffers */
wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
/* Check one register to verify that config was applied */ /* Check one register to verify that config was applied */
reg = rd32(hw, hw->aq.arq.bal);
if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
......
drivers/net/ethernet/intel/i40e/i40e_adminq.h
View file @ 87dc3464
...@@ -56,6 +56,8 @@ struct i40e_adminq_ring { ...@@ -56,6 +56,8 @@ struct i40e_adminq_ring {
u32 head; u32 head;
u32 tail; u32 tail;
u32 len; u32 len;
u32 bah;
u32 bal;
}; };
/* ASQ transaction details */ /* ASQ transaction details */
......
drivers/net/ethernet/intel/i40evf/i40e_adminq.c
View file @ 87dc3464
...@@ -53,16 +53,24 @@ static void i40e_adminq_init_regs(struct i40e_hw *hw) ...@@ -53,16 +53,24 @@ static void i40e_adminq_init_regs(struct i40e_hw *hw)
hw->aq.asq.tail = I40E_VF_ATQT1; hw->aq.asq.tail = I40E_VF_ATQT1;
hw->aq.asq.head = I40E_VF_ATQH1; hw->aq.asq.head = I40E_VF_ATQH1;
hw->aq.asq.len = I40E_VF_ATQLEN1; hw->aq.asq.len = I40E_VF_ATQLEN1;
hw->aq.asq.bal = I40E_VF_ATQBAL1;
hw->aq.asq.bah = I40E_VF_ATQBAH1;
hw->aq.arq.tail = I40E_VF_ARQT1; hw->aq.arq.tail = I40E_VF_ARQT1;
hw->aq.arq.head = I40E_VF_ARQH1; hw->aq.arq.head = I40E_VF_ARQH1;
hw->aq.arq.len = I40E_VF_ARQLEN1; hw->aq.arq.len = I40E_VF_ARQLEN1;
hw->aq.arq.bal = I40E_VF_ARQBAL1;
hw->aq.arq.bah = I40E_VF_ARQBAH1;
} else { } else {
hw->aq.asq.tail = I40E_PF_ATQT; hw->aq.asq.tail = I40E_PF_ATQT;
hw->aq.asq.head = I40E_PF_ATQH; hw->aq.asq.head = I40E_PF_ATQH;
hw->aq.asq.len = I40E_PF_ATQLEN; hw->aq.asq.len = I40E_PF_ATQLEN;
hw->aq.asq.bal = I40E_PF_ATQBAL;
hw->aq.asq.bah = I40E_PF_ATQBAH;
hw->aq.arq.tail = I40E_PF_ARQT; hw->aq.arq.tail = I40E_PF_ARQT;
hw->aq.arq.head = I40E_PF_ARQH; hw->aq.arq.head = I40E_PF_ARQH;
hw->aq.arq.len = I40E_PF_ARQLEN; hw->aq.arq.len = I40E_PF_ARQLEN;
hw->aq.arq.bal = I40E_PF_ARQBAL;
hw->aq.arq.bah = I40E_PF_ARQBAH;
} }
} }
...@@ -298,27 +306,14 @@ static i40e_status i40e_config_asq_regs(struct i40e_hw *hw) ...@@ -298,27 +306,14 @@ static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
wr32(hw, hw->aq.asq.head, 0); wr32(hw, hw->aq.asq.head, 0);
wr32(hw, hw->aq.asq.tail, 0); wr32(hw, hw->aq.asq.tail, 0);
if (hw->mac.type == I40E_MAC_VF) { /* set starting point */
/* configure the transmit queue */ wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
wr32(hw, I40E_VF_ATQBAH1, I40E_PF_ATQLEN_ATQENABLE_MASK));
upper_32_bits(hw->aq.asq.desc_buf.pa)); wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
wr32(hw, I40E_VF_ATQBAL1, wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
lower_32_bits(hw->aq.asq.desc_buf.pa));
wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries |
I40E_VF_ATQLEN1_ATQENABLE_MASK));
reg = rd32(hw, I40E_VF_ATQBAL1);
} else {
/* configure the transmit queue */
wr32(hw, I40E_PF_ATQBAH,
upper_32_bits(hw->aq.asq.desc_buf.pa));
wr32(hw, I40E_PF_ATQBAL,
lower_32_bits(hw->aq.asq.desc_buf.pa));
wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
I40E_PF_ATQLEN_ATQENABLE_MASK));
reg = rd32(hw, I40E_PF_ATQBAL);
}
/* Check one register to verify that config was applied */ /* Check one register to verify that config was applied */
reg = rd32(hw, hw->aq.asq.bal);
if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa)) if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
...@@ -340,30 +335,17 @@ static i40e_status i40e_config_arq_regs(struct i40e_hw *hw) ...@@ -340,30 +335,17 @@ static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
wr32(hw, hw->aq.arq.head, 0); wr32(hw, hw->aq.arq.head, 0);
wr32(hw, hw->aq.arq.tail, 0); wr32(hw, hw->aq.arq.tail, 0);
if (hw->mac.type == I40E_MAC_VF) { /* set starting point */
/* configure the receive queue */ wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
wr32(hw, I40E_VF_ARQBAH1, I40E_PF_ARQLEN_ARQENABLE_MASK));
upper_32_bits(hw->aq.arq.desc_buf.pa)); wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
wr32(hw, I40E_VF_ARQBAL1, wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
lower_32_bits(hw->aq.arq.desc_buf.pa));
wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries |
I40E_VF_ARQLEN1_ARQENABLE_MASK));
reg = rd32(hw, I40E_VF_ARQBAL1);
} else {
/* configure the receive queue */
wr32(hw, I40E_PF_ARQBAH,
upper_32_bits(hw->aq.arq.desc_buf.pa));
wr32(hw, I40E_PF_ARQBAL,
lower_32_bits(hw->aq.arq.desc_buf.pa));
wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
I40E_PF_ARQLEN_ARQENABLE_MASK));
reg = rd32(hw, I40E_PF_ARQBAL);
}
/* Update tail in the HW to post pre-allocated buffers */ /* Update tail in the HW to post pre-allocated buffers */
wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
/* Check one register to verify that config was applied */ /* Check one register to verify that config was applied */
reg = rd32(hw, hw->aq.arq.bal);
if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa)) if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
ret_code = I40E_ERR_ADMIN_QUEUE_ERROR; ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
......
drivers/net/ethernet/intel/i40evf/i40e_adminq.h
View file @ 87dc3464
...@@ -56,6 +56,8 @@ struct i40e_adminq_ring { ...@@ -56,6 +56,8 @@ struct i40e_adminq_ring {
u32 head; u32 head;
u32 tail; u32 tail;
u32 len; u32 len;
u32 bah;
u32 bal;
}; };
/* ASQ transaction details */ /* ASQ transaction details */
......
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