Commit 889facbe authored by Len Brown's avatar Len Brown

tools/power turbostat: v3.0: monitor Watts and Temperature

Show power in Watts and temperature in Celsius
when hardware support is present.

Intel's Sandy Bridge and Ivy Bridge processor generations support RAPL
(Run-Time-Average-Power-Limiting).  Per the Intel SDM
(Intel® 64 and IA-32 Architectures Software Developer Manual)
RAPL provides hardware energy counters and power control MSRs
(Model Specific Registers).  RAPL MSRs are designed primarily
as a method to implement power capping.  However, they are useful
for monitoring system power whether or not power capping is used.

In addition, Turbostat now shows temperature from DTS
(Digital Thermal Sensor) and PTM (Package Thermal Monitor) hardware,
if present.

As before, turbostat reads MSRs, and never writes MSRs.

New columns are present in turbostat output:

The Pkg_W column shows Watts for each package (socket) in the system.
On multi-socket systems, the system summary on the 1st row shows the sum
for all sockets together.

The Cor_W column shows Watts due to processors cores.
Note that Core_W is included in Pkg_W.

The optional GFX_W column shows Watts due to the graphics "un-core".
Note that GFX_W is included in Pkg_W.

The optional RAM_W column on server processors shows Watts due to DRAM DIMMS.
As DRAM DIMMs are outside the processor package, RAM_W is not included in Pkg_W.

The optional PKG_% and RAM_% columns on server processors shows the % of time
in the measurement interval that RAPL power limiting is in effect on the
package and on DRAM.

Note that the RAPL energy counters have some limitations.

First, hardware updates the counters about once every milli-second.
This is fine for typical turbostat measurement intervals > 1 sec.
However, when turbostat is used to measure events that approach
1ms, the counters are less useful.

Second, the 32-bit energy counters are subject to wrapping.
For example, a counter incrementing 15 micro-Joule units
on a 130 Watt TDP server processor could (in theory)
roll over in about 9 minutes.  Turbostat detects and handles
up to 1 counter overflow per measurement interval.
But when the measurement interval exceeds the guaranteed
counter range, we can't detect if more than 1 overflow occured.
So in this case turbostat indicates that the results are
in question by replacing the fractional part of the Watts
in the output with "**":

Pkg_W  Cor_W GFX_W
  3**    0**   0**

Third, the RAPL counters are energy (Joule) counters -- they sum up
weighted events in the package to estimate energy consumed.  They are
not analong power (Watt) meters.  In practice, they tend to under-count
because they don't cover every possible use of energy in the package.
The accuracy of the RAPL counters will vary between product generations,
and between SKU's in the same product generation, and with temperature.

turbostat's -v (verbose) option now displays more power and thermal configuration
information -- as shown on the turbostat.8 manual page.
For example, it now displays the Package and DRAM Thermal Design Power (TDP):

cpu0: MSR_PKG_POWER_INFO: 0x2f064001980410 (130 W TDP, RAPL 51 - 200 W, 0.045898 sec.)
cpu0: MSR_DRAM_POWER_INFO,: 0x28025800780118 (35 W TDP, RAPL 15 - 75 W, 0.039062 sec.)
cpu8: MSR_PKG_POWER_INFO: 0x2f064001980410 (130 W TDP, RAPL 51 - 200 W, 0.045898 sec.)
cpu8: MSR_DRAM_POWER_INFO,: 0x28025800780118 (35 W TDP, RAPL 15 - 75 W, 0.039062 sec.)
Signed-off-by: default avatarLen Brown <len.brown@intel.com>
parent ddac0d68
......@@ -11,16 +11,16 @@ turbostat \- Report processor frequency and idle statistics
.RB [ Options ]
.RB [ "\-i interval_sec" ]
.SH DESCRIPTION
\fBturbostat \fP reports processor topology, frequency
and idle power state statistics on modern X86 processors.
\fBturbostat \fP reports processor topology, frequency,
idle power-state statistics, temperature and power on modern X86 processors.
Either \fBcommand\fP is forked and statistics are printed
upon its completion, or statistics are printed periodically.
\fBturbostat \fP
requires that the processor
must be run on root, and
minimally requires that the processor
supports an "invariant" TSC, plus the APERF and MPERF MSRs.
\fBturbostat \fP will report idle cpu power state residency
on processors that additionally support C-state residency counters.
Additional information is reported depending on hardware counter support.
.SS Options
The \fB-p\fP option limits output to the 1st thread in 1st core of each package.
......@@ -57,7 +57,15 @@ Note that multiple CPUs per core indicate support for Intel(R) Hyper-Threading T
\fBGHz\fP average clock rate while the CPU was in c0 state.
\fBTSC\fP average GHz that the TSC ran during the entire interval.
\fB%c1, %c3, %c6, %c7\fP show the percentage residency in hardware core idle states.
\fBCTMP\fP Degrees Celsius reported by the per-core Digital Thermal Sensor.
\fBPTMP\fP Degrees Celsius reported by the per-package Package Thermal Monitor.
\fB%pc2, %pc3, %pc6, %pc7\fP percentage residency in hardware package idle states.
\fBPkg_W\fP Watts consumed by the whole package.
\fBCor_W\fP Watts consumed by the core part of the package.
\fBGFX_W\fP Watts consumed by the Graphics part of the package -- available only on client processors.
\fBRAM_W\fP Watts consumed by the DRAM DIMMS -- available only on server processors.
\fBPKG_%\fP percent of the interval that RAPL throttling was active on the Package.
\fBRAM_%\fP percent of the interval that RAPL throttling was active on DRAM.
.fi
.PP
.SH EXAMPLE
......@@ -66,50 +74,73 @@ Without any parameters, turbostat prints out counters ever 5 seconds.
for turbostat to fork).
The first row of statistics is a summary for the entire system.
Note that the summary is a weighted average.
For residency % columns, the summary is a weighted average.
For Temperature columns, the summary is the column maximum.
For Watts columns, the summary is a system total.
Subsequent rows show per-CPU statistics.
.nf
[root@x980]# ./turbostat
cor CPU %c0 GHz TSC %c1 %c3 %c6 %pc3 %pc6
0.09 1.62 3.38 1.83 0.32 97.76 1.26 83.61
0 0 0.15 1.62 3.38 10.23 0.05 89.56 1.26 83.61
0 6 0.05 1.62 3.38 10.34
1 2 0.03 1.62 3.38 0.07 0.05 99.86
1 8 0.03 1.62 3.38 0.06
2 4 0.21 1.62 3.38 0.10 1.49 98.21
2 10 0.02 1.62 3.38 0.29
8 1 0.04 1.62 3.38 0.04 0.08 99.84
8 7 0.01 1.62 3.38 0.06
9 3 0.53 1.62 3.38 0.10 0.20 99.17
9 9 0.02 1.62 3.38 0.60
10 5 0.01 1.62 3.38 0.02 0.04 99.92
10 11 0.02 1.62 3.38 0.02
[root@sandy]# ./turbostat
cor CPU %c0 GHz TSC %c1 %c3 %c6 %c7 CTMP PTMP %pc2 %pc3 %pc6 %pc7 Pkg_W Cor_W GFX_W
0.06 0.80 2.29 0.11 0.00 0.00 99.83 47 40 0.26 0.01 0.44 98.78 3.49 0.12 0.14
0 0 0.07 0.80 2.29 0.07 0.00 0.00 99.86 40 40 0.26 0.01 0.44 98.78 3.49 0.12 0.14
0 4 0.03 0.80 2.29 0.12
1 1 0.04 0.80 2.29 0.25 0.01 0.00 99.71 40
1 5 0.16 0.80 2.29 0.13
2 2 0.05 0.80 2.29 0.06 0.01 0.00 99.88 40
2 6 0.03 0.80 2.29 0.08
3 3 0.05 0.80 2.29 0.08 0.00 0.00 99.87 47
3 7 0.04 0.84 2.29 0.09
.fi
.SH SUMMARY EXAMPLE
The "-s" option prints the column headers just once,
and then the one line system summary for each sample interval.
.nf
[root@x980]# ./turbostat -s
%c0 GHz TSC %c1 %c3 %c6 %pc3 %pc6
0.23 1.67 3.38 2.00 0.30 97.47 1.07 82.12
0.10 1.62 3.38 1.87 2.25 95.77 12.02 72.60
0.20 1.64 3.38 1.98 0.11 97.72 0.30 83.36
0.11 1.70 3.38 1.86 1.81 96.22 9.71 74.90
[root@wsm]# turbostat -S
%c0 GHz TSC %c1 %c3 %c6 CTMP %pc3 %pc6
1.40 2.81 3.38 10.78 43.47 44.35 42 13.67 2.09
1.34 2.90 3.38 11.48 58.96 28.23 41 19.89 0.15
1.55 2.72 3.38 26.73 37.66 34.07 42 2.53 2.80
1.37 2.83 3.38 16.95 60.05 21.63 42 5.76 0.20
.fi
.SH VERBOSE EXAMPLE
The "-v" option adds verbosity to the output:
.nf
GenuineIntel 11 CPUID levels; family:model:stepping 0x6:2c:2 (6:44:2)
12 * 133 = 1600 MHz max efficiency
25 * 133 = 3333 MHz TSC frequency
26 * 133 = 3467 MHz max turbo 4 active cores
26 * 133 = 3467 MHz max turbo 3 active cores
27 * 133 = 3600 MHz max turbo 2 active cores
27 * 133 = 3600 MHz max turbo 1 active cores
[root@ivy]# turbostat -v
turbostat v3.0 November 23, 2012 - Len Brown <lenb@kernel.org>
CPUID(0): GenuineIntel 13 CPUID levels; family:model:stepping 0x6:3a:9 (6:58:9)
CPUID(6): APERF, DTS, PTM, EPB
RAPL: 851 sec. Joule Counter Range
cpu0: MSR_NHM_PLATFORM_INFO: 0x81010f0012300
16 * 100 = 1600 MHz max efficiency
35 * 100 = 3500 MHz TSC frequency
cpu0: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x1e008402 (UNdemote-C3, UNdemote-C1, demote-C3, demote-C1, locked: pkg-cstate-limit=2: pc6-noret)
cpu0: MSR_NHM_TURBO_RATIO_LIMIT: 0x25262727
37 * 100 = 3700 MHz max turbo 4 active cores
38 * 100 = 3800 MHz max turbo 3 active cores
39 * 100 = 3900 MHz max turbo 2 active cores
39 * 100 = 3900 MHz max turbo 1 active cores
cpu0: MSR_IA32_ENERGY_PERF_BIAS: 0x00000006 (balanced)
cpu0: MSR_RAPL_POWER_UNIT: 0x000a1003 (0.125000 Watts, 0.000015 Joules, 0.000977 sec.)
cpu0: MSR_PKG_POWER_INFO: 0x01e00268 (77 W TDP, RAPL 60 - 0 W, 0.000000 sec.)
cpu0: MSR_PKG_POWER_LIMIT: 0x830000148268 (UNlocked)
cpu0: PKG Limit #1: ENabled (77.000000 Watts, 1.000000 sec, clamp DISabled)
cpu0: PKG Limit #2: ENabled (96.000000 Watts, 0.000977* sec, clamp DISabled)
cpu0: MSR_PP0_POLICY: 0
cpu0: MSR_PP0_POWER_LIMIT: 0x00000000 (UNlocked)
cpu0: Cores Limit: DISabled (0.000000 Watts, 0.000977 sec, clamp DISabled)
cpu0: MSR_PP1_POLICY: 0
cpu0: MSR_PP1_POWER_LIMIT: 0x00000000 (UNlocked)
cpu0: GFX Limit: DISabled (0.000000 Watts, 0.000977 sec, clamp DISabled)
cpu0: MSR_IA32_TEMPERATURE_TARGET: 0x00691400 (105 C)
cpu0: MSR_IA32_PACKAGE_THERM_STATUS: 0x884e0000 (27 C)
cpu0: MSR_IA32_THERM_STATUS: 0x88560000 (19 C +/- 1)
cpu1: MSR_IA32_THERM_STATUS: 0x88560000 (19 C +/- 1)
cpu2: MSR_IA32_THERM_STATUS: 0x88540000 (21 C +/- 1)
cpu3: MSR_IA32_THERM_STATUS: 0x884e0000 (27 C +/- 1)
...
.fi
The \fBmax efficiency\fP frequency, a.k.a. Low Frequency Mode, is the frequency
available at the minimum package voltage. The \fBTSC frequency\fP is the nominal
......@@ -142,7 +173,7 @@ cor CPU %c0 GHz TSC %c1 %c3 %c6 %pc3 %pc6
10 5 1.42 3.43 3.38 2.14 30.99 65.44
10 11 0.16 2.88 3.38 3.40
.fi
Above the cycle soaker drives cpu7 up its 3.6 Ghz turbo limit
Above the cycle soaker drives cpu7 up its 3.6 GHz turbo limit
while the other processors are generally in various states of idle.
Note that cpu1 and cpu7 are HT siblings within core8.
......
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