Commit 89a82ef8 authored by Cyrille Pitchen's avatar Cyrille Pitchen Committed by Herbert Xu

crypto: atmel-authenc - add support to authenc(hmac(shaX), Y(aes)) modes

This patchs allows to combine the AES and SHA hardware accelerators on
some Atmel SoCs. Doing so, AES blocks are only written to/read from the
AES hardware. Those blocks are also transferred from the AES to the SHA
accelerator internally, without additionnal accesses to the system busses.

Hence, the AES and SHA accelerators work in parallel to process all the
data blocks, instead of serializing the process by (de)crypting those
blocks first then authenticating them after like the generic
crypto/authenc.c driver does.

Of course, both the AES and SHA hardware accelerators need to be available
before we can start to process the data blocks. Hence we use their crypto
request queue to synchronize both drivers.
Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent a1f613f1
...@@ -415,6 +415,18 @@ config CRYPTO_DEV_BFIN_CRC ...@@ -415,6 +415,18 @@ config CRYPTO_DEV_BFIN_CRC
Newer Blackfin processors have CRC hardware. Select this if you Newer Blackfin processors have CRC hardware. Select this if you
want to use the Blackfin CRC module. want to use the Blackfin CRC module.
config CRYPTO_DEV_ATMEL_AUTHENC
tristate "Support for Atmel IPSEC/SSL hw accelerator"
depends on (ARCH_AT91 && HAS_DMA) || COMPILE_TEST
select CRYPTO_AUTHENC
select CRYPTO_DEV_ATMEL_AES
select CRYPTO_DEV_ATMEL_SHA
help
Some Atmel processors can combine the AES and SHA hw accelerators
to enhance support of IPSEC/SSL.
Select this if you want to use the Atmel modules for
authenc(hmac(shaX),Y(cbc)) algorithms.
config CRYPTO_DEV_ATMEL_AES config CRYPTO_DEV_ATMEL_AES
tristate "Support for Atmel AES hw accelerator" tristate "Support for Atmel AES hw accelerator"
depends on HAS_DMA depends on HAS_DMA
......
...@@ -68,6 +68,22 @@ ...@@ -68,6 +68,22 @@
#define AES_CTRR 0x98 #define AES_CTRR 0x98
#define AES_GCMHR(x) (0x9c + ((x) * 0x04)) #define AES_GCMHR(x) (0x9c + ((x) * 0x04))
#define AES_EMR 0xb0
#define AES_EMR_APEN BIT(0) /* Auto Padding Enable */
#define AES_EMR_APM BIT(1) /* Auto Padding Mode */
#define AES_EMR_APM_IPSEC 0x0
#define AES_EMR_APM_SSL BIT(1)
#define AES_EMR_PLIPEN BIT(4) /* PLIP Enable */
#define AES_EMR_PLIPD BIT(5) /* PLIP Decipher */
#define AES_EMR_PADLEN_MASK (0xFu << 8)
#define AES_EMR_PADLEN_OFFSET 8
#define AES_EMR_PADLEN(padlen) (((padlen) << AES_EMR_PADLEN_OFFSET) &\
AES_EMR_PADLEN_MASK)
#define AES_EMR_NHEAD_MASK (0xFu << 16)
#define AES_EMR_NHEAD_OFFSET 16
#define AES_EMR_NHEAD(nhead) (((nhead) << AES_EMR_NHEAD_OFFSET) &\
AES_EMR_NHEAD_MASK)
#define AES_TWR(x) (0xc0 + ((x) * 0x04)) #define AES_TWR(x) (0xc0 + ((x) * 0x04))
#define AES_ALPHAR(x) (0xd0 + ((x) * 0x04)) #define AES_ALPHAR(x) (0xd0 + ((x) * 0x04))
......
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/*
* API for Atmel Secure Protocol Layers Improved Performances (SPLIP)
*
* Copyright (C) 2016 Atmel Corporation
*
* Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*
* This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
*/
#ifndef __ATMEL_AUTHENC_H__
#define __ATMEL_AUTHENC_H__
#ifdef CONFIG_CRYPTO_DEV_ATMEL_AUTHENC
#include <crypto/authenc.h>
#include <crypto/hash.h>
#include <crypto/sha.h>
#include "atmel-sha-regs.h"
struct atmel_aes_dev;
typedef int (*atmel_aes_authenc_fn_t)(struct atmel_aes_dev *, int, bool);
struct atmel_sha_authenc_ctx;
bool atmel_sha_authenc_is_ready(void);
unsigned int atmel_sha_authenc_get_reqsize(void);
struct atmel_sha_authenc_ctx *atmel_sha_authenc_spawn(unsigned long mode);
void atmel_sha_authenc_free(struct atmel_sha_authenc_ctx *auth);
int atmel_sha_authenc_setkey(struct atmel_sha_authenc_ctx *auth,
const u8 *key, unsigned int keylen,
u32 *flags);
int atmel_sha_authenc_schedule(struct ahash_request *req,
struct atmel_sha_authenc_ctx *auth,
atmel_aes_authenc_fn_t cb,
struct atmel_aes_dev *dd);
int atmel_sha_authenc_init(struct ahash_request *req,
struct scatterlist *assoc, unsigned int assoclen,
unsigned int textlen,
atmel_aes_authenc_fn_t cb,
struct atmel_aes_dev *dd);
int atmel_sha_authenc_final(struct ahash_request *req,
u32 *digest, unsigned int digestlen,
atmel_aes_authenc_fn_t cb,
struct atmel_aes_dev *dd);
void atmel_sha_authenc_abort(struct ahash_request *req);
#endif /* CONFIG_CRYPTO_DEV_ATMEL_AUTHENC */
#endif /* __ATMEL_AUTHENC_H__ */
...@@ -29,6 +29,20 @@ ...@@ -29,6 +29,20 @@
#define SHA_MR_HMAC (1 << 11) #define SHA_MR_HMAC (1 << 11)
#define SHA_MR_DUALBUFF (1 << 16) #define SHA_MR_DUALBUFF (1 << 16)
#define SHA_FLAGS_ALGO_MASK SHA_MR_ALGO_MASK
#define SHA_FLAGS_SHA1 SHA_MR_ALGO_SHA1
#define SHA_FLAGS_SHA256 SHA_MR_ALGO_SHA256
#define SHA_FLAGS_SHA384 SHA_MR_ALGO_SHA384
#define SHA_FLAGS_SHA512 SHA_MR_ALGO_SHA512
#define SHA_FLAGS_SHA224 SHA_MR_ALGO_SHA224
#define SHA_FLAGS_HMAC SHA_MR_HMAC
#define SHA_FLAGS_HMAC_SHA1 (SHA_FLAGS_HMAC | SHA_FLAGS_SHA1)
#define SHA_FLAGS_HMAC_SHA256 (SHA_FLAGS_HMAC | SHA_FLAGS_SHA256)
#define SHA_FLAGS_HMAC_SHA384 (SHA_FLAGS_HMAC | SHA_FLAGS_SHA384)
#define SHA_FLAGS_HMAC_SHA512 (SHA_FLAGS_HMAC | SHA_FLAGS_SHA512)
#define SHA_FLAGS_HMAC_SHA224 (SHA_FLAGS_HMAC | SHA_FLAGS_SHA224)
#define SHA_FLAGS_MODE_MASK (SHA_FLAGS_HMAC | SHA_FLAGS_ALGO_MASK)
#define SHA_IER 0x10 #define SHA_IER 0x10
#define SHA_IDR 0x14 #define SHA_IDR 0x14
#define SHA_IMR 0x18 #define SHA_IMR 0x18
......
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