Commit 8ac1696b authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher

drm/amd/pm: a quick fix for "divided by zero" error

Considering Arcturus is a dedicated ASIC for computing, it
will be more proper to drop the support for fan speed reading
and setting. That's on the TODO list.
Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reported-by: default avatarRui Teng <rui.teng@amd.com>
Reviewed-by: default avatarGuchun Chen <guchun.chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 36a7aee0
...@@ -1227,8 +1227,12 @@ static int arcturus_get_fan_speed_rpm(struct smu_context *smu, ...@@ -1227,8 +1227,12 @@ static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000; tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT); tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT);
if (tach_status) {
do_div(tmp64, tach_status); do_div(tmp64, tach_status);
*speed = (uint32_t)tmp64; *speed = (uint32_t)tmp64;
} else {
*speed = 0;
}
break; break;
} }
...@@ -1303,12 +1307,14 @@ static int arcturus_get_fan_speed_pwm(struct smu_context *smu, ...@@ -1303,12 +1307,14 @@ static int arcturus_get_fan_speed_pwm(struct smu_context *smu,
CG_FDO_CTRL1, FMAX_DUTY100); CG_FDO_CTRL1, FMAX_DUTY100);
duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT), duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT),
CG_THERMAL_STATUS, FDO_PWM_DUTY); CG_THERMAL_STATUS, FDO_PWM_DUTY);
if (!duty100)
return -EINVAL;
if (duty100) {
tmp64 = (uint64_t)duty * 255; tmp64 = (uint64_t)duty * 255;
do_div(tmp64, duty100); do_div(tmp64, duty100);
*speed = MIN((uint32_t)tmp64, 255); *speed = MIN((uint32_t)tmp64, 255);
} else {
*speed = 0;
}
return 0; return 0;
} }
......
...@@ -1306,8 +1306,13 @@ int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu, ...@@ -1306,8 +1306,13 @@ int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000; tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS); tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);
if (tach_status) {
do_div(tmp64, tach_status); do_div(tmp64, tach_status);
*speed = (uint32_t)tmp64; *speed = (uint32_t)tmp64;
} else {
dev_warn_once(adev->dev, "Got zero output on CG_TACH_STATUS reading!\n");
*speed = 0;
}
return 0; return 0;
} }
......
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