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Commit 8ac3f64f authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/devinit: switch to device pri macros 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 822ad79f
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Showing with 185 additions and 175 deletions
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c
View file @ 8ac3f64f
......@@ -27,11 +27,11 @@
#include <subdev/bios/init.h>
static u64
g84_devinit_disable(struct nvkm_devinit *devinit)
g84_devinit_disable(struct nvkm_devinit *init)
{
struct nv50_devinit *init = (void *)devinit;
u32 r001540 = nv_rd32(init, 0x001540);
u32 r00154c = nv_rd32(init, 0x00154c);
struct nvkm_device *device = init->subdev.device;
u32 r001540 = nvkm_rd32(device, 0x001540);
u32 r00154c = nvkm_rd32(device, 0x00154c);
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
View file @ 8ac3f64f
......@@ -27,11 +27,11 @@
#include <subdev/bios/init.h>
static u64
g98_devinit_disable(struct nvkm_devinit *devinit)
g98_devinit_disable(struct nvkm_devinit *init)
{
struct nv50_devinit *init = (void *)devinit;
u32 r001540 = nv_rd32(init, 0x001540);
u32 r00154c = nv_rd32(init, 0x00154c);
struct nvkm_device *device = init->subdev.device;
u32 r001540 = nvkm_rd32(device, 0x001540);
u32 r00154c = nvkm_rd32(device, 0x00154c);
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
View file @ 8ac3f64f
......@@ -29,19 +29,19 @@
#include <subdev/clk/pll.h>
int
gf100_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
gf100_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq)
{
struct nv50_devinit *init = (void *)devinit;
struct nvkm_bios *bios = nvkm_bios(init);
struct nvkm_subdev *subdev = &init->subdev;
struct nvkm_device *device = subdev->device;
struct nvbios_pll info;
int N, fN, M, P;
int ret;
ret = nvbios_pll_parse(bios, type, &info);
ret = nvbios_pll_parse(device->bios, type, &info);
if (ret)
return ret;
ret = gt215_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P);
ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P);
if (ret < 0)
return ret;
......@@ -50,9 +50,9 @@ gf100_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
case PLL_VPLL1:
case PLL_VPLL2:
case PLL_VPLL3:
nv_mask(init, info.reg + 0x0c, 0x00000000, 0x00000100);
nv_wr32(init, info.reg + 0x04, (P << 16) | (N << 8) | M);
nv_wr32(init, info.reg + 0x10, fN << 16);
nvkm_mask(device, info.reg + 0x0c, 0x00000000, 0x00000100);
nvkm_wr32(device, info.reg + 0x04, (P << 16) | (N << 8) | M);
nvkm_wr32(device, info.reg + 0x10, fN << 16);
break;
default:
nv_warn(init, "0x%08x/%dKhz unimplemented\n", type, freq);
......@@ -64,10 +64,10 @@ gf100_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
}
static u64
gf100_devinit_disable(struct nvkm_devinit *devinit)
gf100_devinit_disable(struct nvkm_devinit *init)
{
struct nv50_devinit *init = (void *)devinit;
u32 r022500 = nv_rd32(init, 0x022500);
struct nvkm_device *device = init->subdev.device;
u32 r022500 = nvkm_rd32(device, 0x022500);
u64 disable = 0ULL;
if (r022500 & 0x00000001)
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c
View file @ 8ac3f64f
......@@ -27,11 +27,11 @@
#include <subdev/bios/init.h>
u64
gm107_devinit_disable(struct nvkm_devinit *devinit)
gm107_devinit_disable(struct nvkm_devinit *init)
{
struct nv50_devinit *init = (void *)devinit;
u32 r021c00 = nv_rd32(init, 0x021c00);
u32 r021c04 = nv_rd32(init, 0x021c04);
struct nvkm_device *device = init->subdev.device;
u32 r021c00 = nvkm_rd32(device, 0x021c00);
u32 r021c04 = nvkm_rd32(device, 0x021c04);
u64 disable = 0ULL;
if (r021c00 & 0x00000001)
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm204.c
View file @ 8ac3f64f
......@@ -30,18 +30,19 @@
static void
pmu_code(struct nv50_devinit *init, u32 pmu, u32 img, u32 len, bool sec)
{
struct nvkm_bios *bios = nvkm_bios(init);
struct nvkm_device *device = init->base.subdev.device;
struct nvkm_bios *bios = device->bios;
int i;
nv_wr32(init, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu);
nvkm_wr32(device, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu);
for (i = 0; i < len; i += 4) {
if ((i & 0xff) == 0)
nv_wr32(init, 0x10a188, (pmu + i) >> 8);
nv_wr32(init, 0x10a184, nv_ro32(bios, img + i));
nvkm_wr32(device, 0x10a188, (pmu + i) >> 8);
nvkm_wr32(device, 0x10a184, nv_ro32(bios, img + i));
}
while (i & 0xff) {
nv_wr32(init, 0x10a184, 0x00000000);
nvkm_wr32(device, 0x10a184, 0x00000000);
i += 4;
}
}
......@@ -49,28 +50,31 @@ pmu_code(struct nv50_devinit *init, u32 pmu, u32 img, u32 len, bool sec)
static void
pmu_data(struct nv50_devinit *init, u32 pmu, u32 img, u32 len)
{
struct nvkm_bios *bios = nvkm_bios(init);
struct nvkm_device *device = init->base.subdev.device;
struct nvkm_bios *bios = device->bios;
int i;
nv_wr32(init, 0x10a1c0, 0x01000000 | pmu);
nvkm_wr32(device, 0x10a1c0, 0x01000000 | pmu);
for (i = 0; i < len; i += 4)
nv_wr32(init, 0x10a1c4, nv_ro32(bios, img + i));
nvkm_wr32(device, 0x10a1c4, nv_ro32(bios, img + i));
}
static u32
pmu_args(struct nv50_devinit *init, u32 argp, u32 argi)
{
nv_wr32(init, 0x10a1c0, argp);
nv_wr32(init, 0x10a1c0, nv_rd32(init, 0x10a1c4) + argi);
return nv_rd32(init, 0x10a1c4);
struct nvkm_device *device = init->base.subdev.device;
nvkm_wr32(device, 0x10a1c0, argp);
nvkm_wr32(device, 0x10a1c0, nvkm_rd32(device, 0x10a1c4) + argi);
return nvkm_rd32(device, 0x10a1c4);
}
static void
pmu_exec(struct nv50_devinit *init, u32 init_addr)
{
nv_wr32(init, 0x10a104, init_addr);
nv_wr32(init, 0x10a10c, 0x00000000);
nv_wr32(init, 0x10a100, 0x00000002);
struct nvkm_device *device = init->base.subdev.device;
nvkm_wr32(device, 0x10a104, init_addr);
nvkm_wr32(device, 0x10a10c, 0x00000000);
nvkm_wr32(device, 0x10a100, 0x00000002);
}
static int
......@@ -105,7 +109,8 @@ static int
gm204_devinit_post(struct nvkm_subdev *subdev, bool post)
{
struct nv50_devinit *init = (void *)nvkm_devinit(subdev);
struct nvkm_bios *bios = nvkm_bios(init);
struct nvkm_device *device = init->base.subdev.device;
struct nvkm_bios *bios = device->bios;
struct bit_entry bit_I;
u32 exec, args;
int ret;
......@@ -118,10 +123,10 @@ gm204_devinit_post(struct nvkm_subdev *subdev, bool post)
/* reset PMU and load init table parser ucode */
if (post) {
nv_mask(init, 0x000200, 0x00002000, 0x00000000);
nv_mask(init, 0x000200, 0x00002000, 0x00002000);
nv_rd32(init, 0x000200);
while (nv_rd32(init, 0x10a10c) & 0x00000006) {
nvkm_mask(device, 0x000200, 0x00002000, 0x00000000);
nvkm_mask(device, 0x000200, 0x00002000, 0x00002000);
nvkm_rd32(device, 0x000200);
while (nvkm_rd32(device, 0x10a10c) & 0x00000006) {
}
}
......@@ -147,9 +152,9 @@ gm204_devinit_post(struct nvkm_subdev *subdev, bool post)
/* execute init tables */
if (post) {
nv_wr32(init, 0x10a040, 0x00005000);
nvkm_wr32(device, 0x10a040, 0x00005000);
pmu_exec(init, exec);
while (!(nv_rd32(init, 0x10a040) & 0x00002000)) {
while (!(nvkm_rd32(device, 0x10a040) & 0x00002000)) {
}
}
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
View file @ 8ac3f64f
......@@ -29,29 +29,29 @@
#include <subdev/clk/pll.h>
int
gt215_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
gt215_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq)
{
struct nv50_devinit *init = (void *)devinit;
struct nvkm_bios *bios = nvkm_bios(init);
struct nvkm_subdev *subdev = &init->subdev;
struct nvkm_device *device = subdev->device;
struct nvbios_pll info;
int N, fN, M, P;
int ret;
ret = nvbios_pll_parse(bios, type, &info);
ret = nvbios_pll_parse(device->bios, type, &info);
if (ret)
return ret;
ret = gt215_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P);
ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P);
if (ret < 0)
return ret;
switch (info.type) {
case PLL_VPLL0:
case PLL_VPLL1:
nv_wr32(init, info.reg + 0, 0x50000610);
nv_mask(init, info.reg + 4, 0x003fffff,
nvkm_wr32(device, info.reg + 0, 0x50000610);
nvkm_mask(device, info.reg + 4, 0x003fffff,
(P << 16) | (M << 8) | N);
nv_wr32(init, info.reg + 8, fN);
nvkm_wr32(device, info.reg + 8, fN);
break;
default:
nv_warn(init, "0x%08x/%dKhz unimplemented\n", type, freq);
......@@ -63,11 +63,11 @@ gt215_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
}
static u64
gt215_devinit_disable(struct nvkm_devinit *devinit)
gt215_devinit_disable(struct nvkm_devinit *init)
{
struct nv50_devinit *init = (void *)devinit;
u32 r001540 = nv_rd32(init, 0x001540);
u32 r00154c = nv_rd32(init, 0x00154c);
struct nvkm_device *device = init->subdev.device;
u32 r001540 = nvkm_rd32(device, 0x001540);
u32 r00154c = nvkm_rd32(device, 0x00154c);
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
......@@ -99,9 +99,10 @@ gt215_devinit_mmio_part[] = {
};
static u32
gt215_devinit_mmio(struct nvkm_devinit *devinit, u32 addr)
gt215_devinit_mmio(struct nvkm_devinit *obj, u32 addr)
{
struct nv50_devinit *init = (void *)devinit;
struct nv50_devinit *init = container_of(obj, typeof(*init), base);
struct nvkm_device *device = init->base.subdev.device;
u32 *mmio = gt215_devinit_mmio_part;
/* the init tables on some boards have INIT_RAM_RESTRICT_ZM_REG_GROUP
......@@ -123,7 +124,7 @@ gt215_devinit_mmio(struct nvkm_devinit *devinit, u32 addr)
if (addr >= mmio[0] && addr <= mmio[1]) {
u32 part = (addr / mmio[2]) & 7;
if (!init->r001540)
init->r001540 = nv_rd32(init, 0x001540);
init->r001540 = nvkm_rd32(device, 0x001540);
if (part >= hweight8((init->r001540 >> 16) & 0xff))
return ~0;
return addr;
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
View file @ 8ac3f64f
......@@ -27,11 +27,11 @@
#include <subdev/bios/init.h>
static u64
mcp89_devinit_disable(struct nvkm_devinit *devinit)
mcp89_devinit_disable(struct nvkm_devinit *init)
{
struct nv50_devinit *init = (void *)devinit;
u32 r001540 = nv_rd32(init, 0x001540);
u32 r00154c = nv_rd32(init, 0x00154c);
struct nvkm_device *device = init->subdev.device;
u32 r001540 = nvkm_rd32(device, 0x001540);
u32 r00154c = nvkm_rd32(device, 0x00154c);
u64 disable = 0;
if (!(r001540 & 0x40000000)) {
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.c
View file @ 8ac3f64f
......@@ -32,7 +32,7 @@
#include <subdev/vga.h>
static void
nv05_devinit_meminit(struct nvkm_devinit *devinit)
nv05_devinit_meminit(struct nvkm_devinit *init)
{
static const u8 default_config_tab[][2] = {
{ 0x24, 0x00 },
......@@ -44,8 +44,8 @@ nv05_devinit_meminit(struct nvkm_devinit *devinit)
{ 0x06, 0x00 },
{ 0x00, 0x00 }
};
struct nv04_devinit *init = (void *)devinit;
struct nvkm_bios *bios = nvkm_bios(init);
struct nvkm_device *device = init->subdev.device;
struct nvkm_bios *bios = device->bios;
struct io_mapping *fb;
u32 patt = 0xdeadbeef;
u16 data;
......@@ -53,13 +53,13 @@ nv05_devinit_meminit(struct nvkm_devinit *devinit)
int i, v;
/* Map the framebuffer aperture */
fb = fbmem_init(nv_device(init));
fb = fbmem_init(device);
if (!fb) {
nv_error(init, "failed to map fb\n");
return;
}
strap = (nv_rd32(init, 0x101000) & 0x0000003c) >> 2;
strap = (nvkm_rd32(device, 0x101000) & 0x0000003c) >> 2;
if ((data = bmp_mem_init_table(bios))) {
ramcfg[0] = nv_ro08(bios, data + 2 * strap + 0);
ramcfg[1] = nv_ro08(bios, data + 2 * strap + 1);
......@@ -71,52 +71,52 @@ nv05_devinit_meminit(struct nvkm_devinit *devinit)
/* Sequencer off */
nv_wrvgas(init, 0, 1, nv_rdvgas(init, 0, 1) | 0x20);
if (nv_rd32(init, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
if (nvkm_rd32(device, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
goto out;
nv_mask(init, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
nvkm_mask(device, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
/* If present load the hardcoded scrambling table */
if (data) {
for (i = 0, data += 0x10; i < 8; i++, data += 4) {
u32 scramble = nv_ro32(bios, data);
nv_wr32(init, NV04_PFB_SCRAMBLE(i), scramble);
nvkm_wr32(device, NV04_PFB_SCRAMBLE(i), scramble);
}
}
/* Set memory type/width/length defaults depending on the straps */
nv_mask(init, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
nvkm_mask(device, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
if (ramcfg[1] & 0x80)
nv_mask(init, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
nvkm_mask(device, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
nv_mask(init, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
nv_mask(init, NV04_PFB_CFG1, 0, 1);
nvkm_mask(device, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
nvkm_mask(device, NV04_PFB_CFG1, 0, 1);
/* Probe memory bus width */
for (i = 0; i < 4; i++)
fbmem_poke(fb, 4 * i, patt);
if (fbmem_peek(fb, 0xc) != patt)
nv_mask(init, NV04_PFB_BOOT_0,
nvkm_mask(device, NV04_PFB_BOOT_0,
NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
/* Probe memory length */
v = nv_rd32(init, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
v = nvkm_rd32(device, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
(!fbmem_readback(fb, 0x1000000, ++patt) ||
!fbmem_readback(fb, 0, ++patt)))
nv_mask(init, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
!fbmem_readback(fb, 0x800000, ++patt))
nv_mask(init, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
if (!fbmem_readback(fb, 0x400000, ++patt))
nv_mask(init, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
out:
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c
View file @ 8ac3f64f
......@@ -30,33 +30,32 @@
#include <subdev/bios/init.h>
static void
nv10_devinit_meminit(struct nvkm_devinit *devinit)
nv10_devinit_meminit(struct nvkm_devinit *init)
{
struct nv04_devinit *init = (void *)devinit;
struct nvkm_device *device = init->subdev.device;
static const int mem_width[] = { 0x10, 0x00, 0x20 };
int mem_width_count;
uint32_t patt = 0xdeadbeef;
struct io_mapping *fb;
int i, j, k;
if (nv_device(init)->card_type >= NV_11 &&
nv_device(init)->chipset >= 0x17)
if (device->card_type >= NV_11 && device->chipset >= 0x17)
mem_width_count = 3;
else
mem_width_count = 2;
/* Map the framebuffer aperture */
fb = fbmem_init(nv_device(init));
fb = fbmem_init(device);
if (!fb) {
nv_error(init, "failed to map fb\n");
return;
}
nv_wr32(init, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
nvkm_wr32(device, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
/* Probe memory bus width */
for (i = 0; i < mem_width_count; i++) {
nv_mask(init, NV04_PFB_CFG0, 0x30, mem_width[i]);
nvkm_mask(device, NV04_PFB_CFG0, 0x30, mem_width[i]);
for (j = 0; j < 4; j++) {
for (k = 0; k < 4; k++)
......@@ -75,7 +74,7 @@ nv10_devinit_meminit(struct nvkm_devinit *devinit)
/* Probe amount of installed memory */
for (i = 0; i < 4; i++) {
int off = nv_rd32(init, 0x10020c) - 0x100000;
int off = nvkm_rd32(device, 0x10020c) - 0x100000;
fbmem_poke(fb, off, patt);
fbmem_poke(fb, 0, 0);
......@@ -90,7 +89,7 @@ nv10_devinit_meminit(struct nvkm_devinit *devinit)
}
/* IC missing - disable the upper half memory space. */
nv_mask(init, NV04_PFB_CFG0, 0x1000, 0);
nvkm_mask(device, NV04_PFB_CFG0, 0x1000, 0);
amount_found:
fbmem_fini(fb);
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c
View file @ 8ac3f64f
......@@ -45,19 +45,19 @@ nv20_devinit_meminit(struct nvkm_devinit *devinit)
return;
}
nv_wr32(init, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
nvkm_wr32(device, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
/* Allow full addressing */
nv_mask(init, NV04_PFB_CFG0, 0, mask);
nvkm_mask(device, NV04_PFB_CFG0, 0, mask);
amount = nv_rd32(init, 0x10020c);
amount = nvkm_rd32(device, 0x10020c);
for (off = amount; off > 0x2000000; off -= 0x2000000)
fbmem_poke(fb, off - 4, off);
amount = nv_rd32(init, 0x10020c);
amount = nvkm_rd32(device, 0x10020c);
if (amount != fbmem_peek(fb, amount - 4))
/* IC missing - disable the upper half memory space. */
nv_mask(init, NV04_PFB_CFG0, mask, 0);
nvkm_mask(device, NV04_PFB_CFG0, mask, 0);
fbmem_fini(fb);
}
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c
View file @ 8ac3f64f
......@@ -33,43 +33,45 @@
#include <subdev/vga.h>
int
nv50_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
nv50_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq)
{
struct nv50_devinit *init = (void *)devinit;
struct nvkm_bios *bios = nvkm_bios(init);
struct nvkm_subdev *subdev = &init->subdev;
struct nvkm_device *device = subdev->device;
struct nvkm_bios *bios = device->bios;
struct nvbios_pll info;
int N1, M1, N2, M2, P;
int ret;
ret = nvbios_pll_parse(bios, type, &info);
if (ret) {
nv_error(devinit, "failed to retrieve pll data, %d\n", ret);
nv_error(subdev, "failed to retrieve pll data, %d\n", ret);
return ret;
}
ret = nv04_pll_calc(nv_subdev(devinit), &info, freq, &N1, &M1, &N2, &M2, &P);
ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
if (!ret) {
nv_error(devinit, "failed pll calculation\n");
nv_error(subdev, "failed pll calculation\n");
return ret;
}
switch (info.type) {
case PLL_VPLL0:
case PLL_VPLL1:
nv_wr32(init, info.reg + 0, 0x10000611);
nv_mask(init, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
nv_mask(init, info.reg + 8, 0x7fff00ff, (P << 28) |
nvkm_wr32(device, info.reg + 0, 0x10000611);
nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
nvkm_mask(device, info.reg + 8, 0x7fff00ff, (P << 28) |
(M2 << 16) | N2);
break;
case PLL_MEMORY:
nv_mask(init, info.reg + 0, 0x01ff0000, (P << 22) |
nvkm_mask(device, info.reg + 0, 0x01ff0000,
(P << 22) |
(info.bias_p << 19) |
(P << 16));
nv_wr32(init, info.reg + 4, (N1 << 8) | M1);
nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1);
break;
default:
nv_mask(init, info.reg + 0, 0x00070000, (P << 16));
nv_wr32(init, info.reg + 4, (N1 << 8) | M1);
nvkm_mask(device, info.reg + 0, 0x00070000, (P << 16));
nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1);
break;
}
......@@ -77,10 +79,10 @@ nv50_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
}
static u64
nv50_devinit_disable(struct nvkm_devinit *devinit)
nv50_devinit_disable(struct nvkm_devinit *init)
{
struct nv50_devinit *init = (void *)devinit;
u32 r001540 = nv_rd32(init, 0x001540);
struct nvkm_device *device = init->subdev.device;
u32 r001540 = nvkm_rd32(device, 0x001540);
u64 disable = 0ULL;
if (!(r001540 & 0x40000000))
......
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