Commit 8ae980d2 authored by John Fraker's avatar John Fraker Committed by Jakub Kicinski

gve: Deprecate adminq_pfn for pci revision 0x1.

adminq_pfn assumes a page size of 4k, causing this mechanism to break in
kernels compiled with different page sizes. A new PCI device revision was
needed for the device to be able to communicate with the driver how to
set up the admin queue prior to having access to the admin queue.
Signed-off-by: default avatarJordan Kimbrough <jrkim@google.com>
Signed-off-by: default avatarJohn Fraker <jfraker@google.com>
Reviewed-by: default avatarWillem de Bruijn <willemb@google.com>
Link: https://lore.kernel.org/r/20231128002648.320892-3-jfraker@google.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 955f4d3b
...@@ -225,9 +225,20 @@ int gve_adminq_alloc(struct device *dev, struct gve_priv *priv) ...@@ -225,9 +225,20 @@ int gve_adminq_alloc(struct device *dev, struct gve_priv *priv)
priv->adminq_get_ptype_map_cnt = 0; priv->adminq_get_ptype_map_cnt = 0;
/* Setup Admin queue with the device */ /* Setup Admin queue with the device */
if (priv->pdev->revision < 0x1) {
iowrite32be(priv->adminq_bus_addr / PAGE_SIZE, iowrite32be(priv->adminq_bus_addr / PAGE_SIZE,
&priv->reg_bar0->adminq_pfn); &priv->reg_bar0->adminq_pfn);
} else {
iowrite16be(GVE_ADMINQ_BUFFER_SIZE,
&priv->reg_bar0->adminq_length);
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
iowrite32be(priv->adminq_bus_addr >> 32,
&priv->reg_bar0->adminq_base_address_hi);
#endif
iowrite32be(priv->adminq_bus_addr,
&priv->reg_bar0->adminq_base_address_lo);
iowrite32be(GVE_DRIVER_STATUS_RUN_MASK, &priv->reg_bar0->driver_status);
}
gve_set_admin_queue_ok(priv); gve_set_admin_queue_ok(priv);
return 0; return 0;
} }
...@@ -237,6 +248,7 @@ void gve_adminq_release(struct gve_priv *priv) ...@@ -237,6 +248,7 @@ void gve_adminq_release(struct gve_priv *priv)
int i = 0; int i = 0;
/* Tell the device the adminq is leaving */ /* Tell the device the adminq is leaving */
if (priv->pdev->revision < 0x1) {
iowrite32be(0x0, &priv->reg_bar0->adminq_pfn); iowrite32be(0x0, &priv->reg_bar0->adminq_pfn);
while (ioread32be(&priv->reg_bar0->adminq_pfn)) { while (ioread32be(&priv->reg_bar0->adminq_pfn)) {
/* If this is reached the device is unrecoverable and still /* If this is reached the device is unrecoverable and still
...@@ -248,6 +260,16 @@ void gve_adminq_release(struct gve_priv *priv) ...@@ -248,6 +260,16 @@ void gve_adminq_release(struct gve_priv *priv)
i++; i++;
msleep(GVE_ADMINQ_SLEEP_LEN); msleep(GVE_ADMINQ_SLEEP_LEN);
} }
} else {
iowrite32be(GVE_DRIVER_STATUS_RESET_MASK, &priv->reg_bar0->driver_status);
while (!(ioread32be(&priv->reg_bar0->device_status)
& GVE_DEVICE_STATUS_DEVICE_IS_RESET)) {
if (i == GVE_MAX_ADMINQ_RELEASE_CHECK)
WARN(1, "Unrecoverable platform error!");
i++;
msleep(GVE_ADMINQ_SLEEP_LEN);
}
}
gve_clear_device_rings_ok(priv); gve_clear_device_rings_ok(priv);
gve_clear_device_resources_ok(priv); gve_clear_device_resources_ok(priv);
gve_clear_admin_queue_ok(priv); gve_clear_admin_queue_ok(priv);
......
...@@ -18,11 +18,20 @@ struct gve_registers { ...@@ -18,11 +18,20 @@ struct gve_registers {
__be32 adminq_event_counter; __be32 adminq_event_counter;
u8 reserved[3]; u8 reserved[3];
u8 driver_version; u8 driver_version;
__be32 adminq_base_address_hi;
__be32 adminq_base_address_lo;
__be16 adminq_length;
}; };
enum gve_device_status_flags { enum gve_device_status_flags {
GVE_DEVICE_STATUS_RESET_MASK = BIT(1), GVE_DEVICE_STATUS_RESET_MASK = BIT(1),
GVE_DEVICE_STATUS_LINK_STATUS_MASK = BIT(2), GVE_DEVICE_STATUS_LINK_STATUS_MASK = BIT(2),
GVE_DEVICE_STATUS_REPORT_STATS_MASK = BIT(3), GVE_DEVICE_STATUS_REPORT_STATS_MASK = BIT(3),
GVE_DEVICE_STATUS_DEVICE_IS_RESET = BIT(4),
};
enum gve_driver_status_flags {
GVE_DRIVER_STATUS_RUN_MASK = BIT(0),
GVE_DRIVER_STATUS_RESET_MASK = BIT(1),
}; };
#endif /* _GVE_REGISTER_H_ */ #endif /* _GVE_REGISTER_H_ */
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