Commit 8c9b7db0 authored by Stefan Kristiansson's avatar Stefan Kristiansson Committed by Stafford Horne

openrisc: head: refactor out tlb flush into it's own function

This brings it inline with the other setup oprations done like the cache
enables _ic_enable and _dc_enable.  Also, this is going to make it
easier to initialize additional cpu's when smp is introduced.
Signed-off-by: default avatarStefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: Added commit body]
Signed-off-by: default avatarStafford Horne <shorne@gmail.com>
parent c2dc7243
...@@ -522,22 +522,8 @@ enable_dc: ...@@ -522,22 +522,8 @@ enable_dc:
l.nop l.nop
flush_tlb: flush_tlb:
/* l.jal _flush_tlb
* I N V A L I D A T E T L B e n t r i e s l.nop
*/
LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
l.addi r7,r0,128 /* Maximum number of sets */
1:
l.mtspr r5,r0,0x0
l.mtspr r6,r0,0x0
l.addi r5,r5,1
l.addi r6,r6,1
l.sfeq r7,r0
l.bnf 1b
l.addi r7,r7,-1
/* The MMU needs to be enabled before or32_early_setup is called */ /* The MMU needs to be enabled before or32_early_setup is called */
...@@ -629,6 +615,26 @@ jump_start_kernel: ...@@ -629,6 +615,26 @@ jump_start_kernel:
l.jr r30 l.jr r30
l.nop l.nop
_flush_tlb:
/*
* I N V A L I D A T E T L B e n t r i e s
*/
LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
l.addi r7,r0,128 /* Maximum number of sets */
1:
l.mtspr r5,r0,0x0
l.mtspr r6,r0,0x0
l.addi r5,r5,1
l.addi r6,r6,1
l.sfeq r7,r0
l.bnf 1b
l.addi r7,r7,-1
l.jr r9
l.nop
/* ========================================[ cache ]=== */ /* ========================================[ cache ]=== */
/* aligment here so we don't change memory offsets with /* aligment here so we don't change memory offsets with
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment