Commit 8e1cc0e4 authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Mark Brown

ASoC: davinci-mcasp: Fix dra7 DMA offset when using CFG port

The TX and RX offset is different for each serializers when using the CFG
port for DMA access.
When using the CFG port only one serializer can be used per direction so
print error message and only configure the first serializer's offset.
Reported-by: default avatarMisael Lopez Cruz <misael.lopez@ti.com>
Suggested-by: default avatarMisael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 1a695a90
...@@ -1513,8 +1513,9 @@ static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { ...@@ -1513,8 +1513,9 @@ static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
}; };
static struct davinci_mcasp_pdata dra7_mcasp_pdata = { static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
.tx_dma_offset = 0x200, /* The CFG port offset will be calculated if it is needed */
.rx_dma_offset = 0x284, .tx_dma_offset = 0,
.rx_dma_offset = 0,
.version = MCASP_VERSION_4, .version = MCASP_VERSION_4,
}; };
...@@ -1734,6 +1735,52 @@ static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) ...@@ -1734,6 +1735,52 @@ static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
return PCM_EDMA; return PCM_EDMA;
} }
static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
{
int i;
u32 offset = 0;
if (pdata->version != MCASP_VERSION_4)
return pdata->tx_dma_offset;
for (i = 0; i < pdata->num_serializer; i++) {
if (pdata->serial_dir[i] == TX_MODE) {
if (!offset) {
offset = DAVINCI_MCASP_TXBUF_REG(i);
} else {
pr_err("%s: Only one serializer allowed!\n",
__func__);
break;
}
}
}
return offset;
}
static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
{
int i;
u32 offset = 0;
if (pdata->version != MCASP_VERSION_4)
return pdata->rx_dma_offset;
for (i = 0; i < pdata->num_serializer; i++) {
if (pdata->serial_dir[i] == RX_MODE) {
if (!offset) {
offset = DAVINCI_MCASP_RXBUF_REG(i);
} else {
pr_err("%s: Only one serializer allowed!\n",
__func__);
break;
}
}
}
return offset;
}
static int davinci_mcasp_probe(struct platform_device *pdev) static int davinci_mcasp_probe(struct platform_device *pdev)
{ {
struct snd_dmaengine_dai_dma_data *dma_data; struct snd_dmaengine_dai_dma_data *dma_data;
...@@ -1862,7 +1909,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev) ...@@ -1862,7 +1909,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
if (dat) if (dat)
dma_data->addr = dat->start; dma_data->addr = dat->start;
else else
dma_data->addr = mem->start + pdata->tx_dma_offset; dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
res = platform_get_resource(pdev, IORESOURCE_DMA, 0); res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
...@@ -1883,7 +1930,8 @@ static int davinci_mcasp_probe(struct platform_device *pdev) ...@@ -1883,7 +1930,8 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
if (dat) if (dat)
dma_data->addr = dat->start; dma_data->addr = dat->start;
else else
dma_data->addr = mem->start + pdata->rx_dma_offset; dma_data->addr =
mem->start + davinci_mcasp_rxdma_offset(pdata);
dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE]; dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
res = platform_get_resource(pdev, IORESOURCE_DMA, 1); res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
......
...@@ -85,9 +85,9 @@ ...@@ -85,9 +85,9 @@
(n << 2)) (n << 2))
/* Transmit Buffer for Serializer n */ /* Transmit Buffer for Serializer n */
#define DAVINCI_MCASP_TXBUF_REG 0x200 #define DAVINCI_MCASP_TXBUF_REG(n) (0x200 + (n << 2))
/* Receive Buffer for Serializer n */ /* Receive Buffer for Serializer n */
#define DAVINCI_MCASP_RXBUF_REG 0x280 #define DAVINCI_MCASP_RXBUF_REG(n) (0x280 + (n << 2))
/* McASP FIFO Registers */ /* McASP FIFO Registers */
#define DAVINCI_MCASP_V2_AFIFO_BASE (0x1010) #define DAVINCI_MCASP_V2_AFIFO_BASE (0x1010)
......
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