Commit 8e2f3bce authored by Doug Smythies's avatar Doug Smythies Committed by Rafael J. Wysocki

cpufreq: x86: Disable interrupts during MSRs reading

According to Intel 64 and IA-32 Architectures SDM, Volume 3,
Chapter 14.2, "Software needs to exercise care to avoid delays
between the two RDMSRs (for example interrupts)".

So, disable interrupts during reading MSRs IA32_APERF and IA32_MPERF.

See also: commit 4ab60c3f (cpufreq: intel_pstate: Disable
interrupts during MSRs reading).
Signed-off-by: default avatarDoug Smythies <dsmythies@telus.net>
Reviewed-by: default avatarLen Brown <len.brown@intel.com>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent aae4e7a8
...@@ -40,13 +40,16 @@ static void aperfmperf_snapshot_khz(void *dummy) ...@@ -40,13 +40,16 @@ static void aperfmperf_snapshot_khz(void *dummy)
struct aperfmperf_sample *s = this_cpu_ptr(&samples); struct aperfmperf_sample *s = this_cpu_ptr(&samples);
ktime_t now = ktime_get(); ktime_t now = ktime_get();
s64 time_delta = ktime_ms_delta(now, s->time); s64 time_delta = ktime_ms_delta(now, s->time);
unsigned long flags;
/* Don't bother re-computing within the cache threshold time. */ /* Don't bother re-computing within the cache threshold time. */
if (time_delta < APERFMPERF_CACHE_THRESHOLD_MS) if (time_delta < APERFMPERF_CACHE_THRESHOLD_MS)
return; return;
local_irq_save(flags);
rdmsrl(MSR_IA32_APERF, aperf); rdmsrl(MSR_IA32_APERF, aperf);
rdmsrl(MSR_IA32_MPERF, mperf); rdmsrl(MSR_IA32_MPERF, mperf);
local_irq_restore(flags);
aperf_delta = aperf - s->aperf; aperf_delta = aperf - s->aperf;
mperf_delta = mperf - s->mperf; mperf_delta = mperf - s->mperf;
......
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